thc63lvd1023b rev.3.0 e · pdf file160mhz 67bits lvds transmitter ... setting the prbs pin...

THC63LVD1023B_Rev.3.0_ECopyright2011 THine Electronics, Inc.
1/26 THine Electronics, Inc.
THC63LVD1023B160MHz 67Bits LVDS Transmitter
General DescriptionThe THC63LVD1023B transmitter is designed to suportSingle Link transmission between Host and Flat PanelDisplay up to 1080p(60Hz) resolutions and Dual Linktransmission between Host and Flat Panel Display up to1080p(120Hz). The THC63LVD1023B converts 67bits of CMOS/TTLdata into LVDS (Low Voltage Differential Signaling)data stream. The transmitter can be programmed for ris-ing edge or falling edge clocks through a dedicated pin,and support double edge inputs.In Dual Link, the transmit clock frequency of 160MHz,67bits of RGB data are transmitted at an effective rateof 1.12Gbps per LVDS channel.In Asynchronous mode, the THC63LVD1023B has 2independent 35Bits Transmitter.
Features Wide dot clock range suited for TV Signal (480i-
1080p), PC Signal (VGA-QXGA)TTL/CMOS Input: 10-160MHzLVDS Output: 20-160MHz
PLL requires No external components Flexible Input/Output mode
1. Single/Dual TTL IN, Single/Dual LVDS OUT2. Double edge input for Single TTL IN/Dual LVDS OUT3. Input port SW for Single TTL IN/Dual LVDS OUT4. Asynchronous Dual TTL IN/Dual LVDS OUT
Clock edge selectable 3 LVDS data mapping for simplifying PCB layout. Pseudo Random pattern generation circuit Supports Reduced swing LVDS for Low EMI Power down mode Low power single 3.3V CMOS design Backward compatible with THC63LVD1023 144pin LQFP
Block Diagram
PAR
ALLE
L TO
SER
IAL
PLL
TA1 +/-
TB1 +/-
TC1 +/-
TD1 +/-
TCLK1 +/-
/PDWN
(20 to 160MHz)TRANSMITTER CLOCK IN
(10 to 160MHz)
R1[9:0]
LVDS OUTPUT
TE1 +/-
32DATA Port1
PAR
ALLE
L TO
SER
IAL
TA2 +/-
TB2 +/-
TC2 +/-
TD2 +/-
TE2 +/-
TCLK2 +/-
Port1
LVDS OUTPUTPort2
G1[9:0]B1[9:0]
CONT1[2:1]
Hsync1
35
Dat
a Fo
rmat
ter
35
R/F
1) D
EM
UX
2) M
UX
3) D
istri
butio
n
Vsync1DE1
MAP
R2[9:0]
32DATA Port2G2[9:0]B2[9:0]
CONT2[2:1]
6
RS
MODE[3:0]
PRBS
4) D
DR
CLKIN1CLKIN2
MUX
Hsync2Vsync2
DE2
5) In
put P
ort S
W6)
Cro
sspo
int
ASYNC

Pin Out (top view)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
727170696867666564636261605958575655545352515049484746454443424140393837
108
107
106
105
104
103
102
101
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144
B27/
TD21
VC
C
B28/
TD22
B29/
TD23
HS
YN
C2/
TE20
VS
YN
C2/
TE21
DE
2/TE
22V
CC
GN
DC
LKIN
1C
LKIN
2C
ON
T11
/TE
23C
ON
T12
/TE
24C
ON
T21
/TE
25C
ON
T22
/TE
26R
/FR
SM
OD
E3
MO
DE
1M
OD
E0
MO
DE2
ASY
NC
/PD
WN
PRB
SR
eser
ved
PGN
DPV
CC
PGN
D
LGND
TE2+TE2-TD2+TD2-
LGND
TCLK2-TC2+TC2-
LGNDLVCC
TB2+TB2-TA2+TA2-LGND
LGND
LGND
LGND
B16
/TD
15B
15/T
D14
B14
/TD
13G
ND
VC
CB
13/T
D12
B12
/TD
11B
11/T
D10
B10
/TC
16G
19/T
C15
G18
/TC
14G
17/T
C13
G16
/TC
12G
15/T
C11
GN
DV
CC
G14
/TC
10G
13/T
B16
G12
/TB
15G
11/T
B14
G10
/TB
13R
19/T
B12
R18
/TB
11R
17/T
B10
R16
/TA
16G
ND
VC
CR
15/T
A15
R14
/TA
14R
13/T
A13
R12
/TA
12
R10
/TA
10P
GN
DP
VC
CP
GN
D
N/CB17/TD16B18/TE10B19/TE11
VCCGND
R20/TE12R21/TE13R22/TE14R23/TE15R24/TE16R25/TA20R26/TA21R27/TA22R28/TA23R29/TA24
VCCGND
G20/TA25G21/TA26G22/TB20G23/TB21G24/TB22G25/TB23G26/TB24G27/TB25G28/TB26G29/TC20
VCCGND
B20/TC21B21/TC22B22/TC23B23/TC24B24/TC25B25/TC26
TCLK2+
TE1+TE1-TD1+TD1-
TC1+TC1-
TCLK1+TCLK1-
TB1+TB1-
TA1-TA1+
LVCC
LVCC
LVCC
LVCC
R11
/TA
11
B26/
TD20
GN
D
DE1
/TD
26VS
YN
C1/
TD25
HS
YN
C1/
TD24
N/C
MA
P
N/C

Pin Description
Pin Name
Pin # Type DescriptionASYNC=L ASYNC=HTA1+, TA1- 70, 71
LVDSOUT
The 1st Link. The 1st pixel output data when Dual-Link.
TB1+, TB1- 68, 69TC1+, TC1- 64, 65TD1+, TD1- 58, 59TE1+, TE1- 56, 57
TCLK1+, TCLK1- 62, 63 LVDS Clock Out for 1st and 2nd Link.TA2+, TA2- 52, 53
The 2nd Link. These pins are disabled when Single Link.
TB2+, TB2- 50, 51TC2+, TC2- 46, 47TD2+, TD2- 40, 41TE2+, TE2- 38, 39
TCLK2+, TCLK2- 44, 45
See following table.
Case1: LVDS Clock out for 2nd link.Case2: LVDS Clock out for 1st link.Case3: Additional LVDS Clock out.
Identical to TCLK1+/-Case4: Not available (High-Impedance)
R19 ~ R10 TB12~TB10,TA16~TA1087 - 84,81 - 76
IN
ASYNC=L The 1st Pixel Data Inputs.ASYNC=H Data Inputs.
G19 ~ G10 TC15~TC10,TB16~TB1399 - 95,92 - 88
B19 ~ B10TE11~TE10,TD16~TD10,
TC16
112 -110, 108 -106,103 - 100
R29 ~ R20 TA24~TA20,TE16~TE12 124 - 115
IN
ASYNC=L The 2nd Pixel Data Inputs.ASYNC=H Data Inputs.
G29 ~ G20TC20,
TB26~TB20,TA26~TA25
136 - 127
B29 ~ B20 TD23~TD20,TC26~TC216, 5, 2, 1,144 - 139
ASYNC MODE0 MODE1 MODE2 Description
H x x L Case1
H x x H Case2
L L x x Case3
L H L x Case4
L H H L Case4
L H H H Case3

CONT11 *1,
CONT12 *1TE23,TE24 17, 18
INASYNC=L: CONTROL Data Inputs.ASYNC=H: Data Inputs.CONT21 *1,
CONT22 *1TE25,TE26 19, 20
DE1,DE2 TD26,TE22 9,12 INASYNC=L: Data Enable Inputs.ASYNC=H: Data Inputs.
VSYNC1,VSYNC2
TD25,TE21 8,11 INASYNC=L: Vsync Inputs.ASYNC=H: Data Inputs
HSYNC1,HSYNC2
TD24,TE20 7,10 INASYNC=L: Hsync Inputs.ASYNC=H: Data Inputs
CLKIN1 15 IN
Clock Input of following cases.
CLKIN2 16 IN
Clock Input of following cases.
R/F 21 INInput Clock Triggering Edge Select.H: Rising edge, L: Falling edge
RS 22 IN
LVDS swing mode, VREF select. See Fig4, 5.
MAP(See Fig7 to 9 and
Table4 to10)24 IN
LVDS mapping table select.
MODE1, MODE0 25, 26 IN
Pin Name
Pin # Type DescriptionASYNC=L ASYNC=H
ASYNC MODE1 MODE0 MODE3
H x x x
L L x x
L H L H
L H H x
ASYNC MODE1 MODE0 MODE3
H x x x
L H L L
RS LVDS SwingSmall Swing Input Support
VIHM 350mV N/A
VIMM 350mV RS=VREFa
VILM 200mV N/A
a. VREF is Input Reference Voltage.
MAP Mapping ModeVIHM Mapping MODE1VILM Mapping MODE2VIMM Mapping MODE3
Pixel Data Mode.MODE1 MODE0 Mode
L L Dual Link (Dual-in/Dual-out)H L Dual Link (Single-in/Dual-out)L H Single Link (Dual-in/Single-out)H H Single Link (Single-in/Single-out)
Pin Description (Continued)
*1: CONT## are DATA pins that user can use as data like RGB data.

*2: Setting the PRBS pin high enables the internal test pattern generator. It generates Pseudo-Random Bit Sequence of223-1. The generated PRBS is fed into input data latches, formatted as VGA video like data, encoded and serializedinto TXOUT output. This function is normally to be used for analyzing the signal integrity of the transmissionchannel including PCB traces, connectors, and cables.
MODE2(See Fig.5)
27 IN
The use of these multi-function depends on the setting of MODE or ASYNC. ASYNC=H(MODE=Dont care.)
H: Cross point switching enable. L: Cross point switching disable. ASYNC=L
MODE=HH(Single-in/Single-out Mode) H: Distribution function enable.
L: Distribution function disable. MODE=HL(Single-in/Dual-out Mode)
H: DDR (Double Edge input) function enable. L: DDR (Double Edge input) function disable.
MODE3 23 IN
Input port switching function enable when MODE=HL(Single-in/Dual-out Mode). H or Open: Port switch disable. L: Port switch enable.
ASYNC 28 INAsynchronous function enable. H: Asynchronous mode enable.(MODE=Disable) L: Asynchronous mode disable.(MODE=Enable)
/PDWN 30 INH: Normal operation,L: Power down (all outputs are Hi-Z)
PRBS *2 31 IN
PRBS (Pseudo-Random Binary Sequence) generator is active in order to evaluate eye patterns when M

thc63lvd1023b rev.3.0 e · pdf file160mhz 67bits lvds transmitter ... setting the prbs pin...

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