texas a&m university department of computer science cpsc 321 computer architecture introduction...

Texas A&M UniversityDepartment of Computer Science

CPSC 321 Computer Architecture

Introduction to Courseand

Five Components of a Computer

Instructor Michael E. Thomadakis

http://courses.cs.tamu.edu/cpsc321/miket/

CPSC321 Computer Architecture Lec 1.2 Michael Thomadakis tamu

Course Overview° CPSC 321 – Computer Architecture

•Course Information- The Crew- Objectives- Scope- Type Material

•Assignment Types•Reporting Work

° Intro to Computer Architecture

° Organization and Anatomy of a Computer


CPSC 321 –— Course Information – The Crew

° Instructor:• Who: Dr. Michael E. Thomadakis• e-mail: [email protected]• Room:315B HRBB; tel: 845-3907• OH: Friday: 12:30–14:30 or at other times by appointment.

° TAs / GANT1) Praveen Bhojwani; [email protected] ;

- HRBB 514B; 458-0833 ;- TBA or by appointment.

2) Di - Wu; [email protected] ; - HRBB 522; 845-4365 ;- TBA or by appointment.

3) Subrata Acharya; [email protected] ;

° Contact as regularly to obtain your scores.

° Contact as early in case you have questions on assignments or the material.


° Homework will be included with laboratory assignments• HW is done together by all people doing lab.

° Labs (8 – 10)• 1 or 2 persons to do the lab work (number will be explicitly stated),• preparation for projects and hands-on for class material,• print from web page for current week,• complete during lab period, obtain TA check-off same day for grade,• if can’t finish, due start of next lab.

CPSC 321 –— Course Information – Assignment Structure – I


° Projects• Major assignments, typically to 2+ weeks to complete• 3 -- 5 in number.

° Teams?• each assignment will clearly state if you can work with partner(s) or

individually,• partners turn in one set of deliverables (reports, files, code, etc.) with

both names; receive grade commensurate with their fair contribution to the project,

• intent: enhanced learning experience,• NOT an opportunity to let partner do all the work (why not? Exams

and peer evaluation)

CPSC 321 –— Course Information – Assignment Structure – II


Course Requirements

° 100 course points awarded for: examinations, labs, projects, homework, as follows:

Item Percentage

Two Midterm Exams 30% Final Exam 25% Projects 30% Labs 15% Homework 05%

° Labs: Groups of two people (max).

° Projects: Groups of four people (max).

° Homework: Part of labs.


Cheating - Plagiarism

° What is cheating?• Studying together in groups is encouraged• BUT, submitted work must be your own• Common examples of cheating:

- find homework solution on Web; - ask to borrow solution “just to take a look”; - copy solution from classmate and modify so it looks different.

• It is very easy to spot copied work.

° Penalty?• We have to report incident to Computer Science Department Head, as per

TAMU regulations:• Department head’s action includes:

- F in course, - suspension, or - expulsion

• are possible outcomes


Excused Absence and Make-ups

°Excused Absences: defined by the University; consult the Student's Handbook.

° Usually a condition that objectively impacts the capacity of the student to perform assignments.

• such as, a DOCUMENTED medical reason.

° Can’t make a midterm, or final?• Tell me ahead of time and we will schedule alternate time before exam

° “Forgot to turn in homework / Dog ate computer, etc.”• Late assignments are not accepted after the deadline.

° NO LATE LAB, Projects accepted unless a University sanctioned excuse is provided.

• Proper documentation must be furnished.


Textbooks and Other Material ° Course material: See course homepage and newsgroup

http://courses.cs.tamu.edu/cpsc321/miketOR

http://faculty.cs.tamu.edu/miket/teachingAND

news:tamu.classes.cpsc321° Main Text:

• [PaHe1998] Patterson and Hennessy, Computer Organization and Design: The Hardware/Software Interface, Second Edition, Morgan Kaufmann Publishers, Inc., 1998, ISBN 1-55860-428-6.

- Get 2nd Edition ( >> 50% text changed; try to get ³ 3rd printing)

° Verilog Hardware Description Language (HDL) and Digital Design:• [MMM2002] M. Morris Mano, Digital Design, 3rd Edition, Prentice

Hall, Upper-Saddle River, 2002.• [BroVra2003] Stephen Brown and Zvonko Vranesic, Fundamentals of

Digital Logic with Verilog Design, McGraw-Hill, 2003.

° Other Notes, Transparencies, as appropriate.


CPSC321: Course Content Focus

Computer Architecture and Engineering

Instruction Set Design Computer Organization

Interfaces Hardware Components

Compiler/System View Logic Designer’s View

“Building Architect” “Construction Engineer”


Course Organization

° Design Intensive Class --- 75 to 150 hours per semester per student

MIPS Instruction Set ---> “Standard-Cell” (partial) implementation

° HDL System (Verilog):

Specification and Simulation

Design Description Computer-based "breadboard"

• Behavior over time

• Before construction

° Lectures (tentative breakdown):• Review• 2 ½ weeks on Intro, ISA, MIPS, CMIPS translation;• 2 weeks on technology, HDL, and computer arithmetic (int, FP);• 3 weeks on standard Proc. Design and pipelining• 1 weeks on advanced pipelining and modern superscalar design• 1 weeks on memory and caches• 1 1/2 weeks on Memory and I/O• ?? Special lectures (parallel processing, supercomputing?)


CPSC321: So what's in it for me? (1 / 2)

° In-depth understanding of the inner-workings of modern computers, their evolution, and trade-offs present at the hardware/software boundary.

• discussion of fast/slow operations and why they are easy/hard to implement in hardware

• “out of order execution,” branch-prediction and other techniques to increase the average execution rate of instructions

° Experience with the design process in the context of a large complex (hardware) design.

• Functional Spec ® Control & Datapath ® “Physical” implementation• Modern CAD tools (later on ?)

° Designer's "Conceptual" toolbox.


CPSC 321: So what's in it for me? (2 / 2)

° Teach Computer Architecture from a software developer’s point of view• What the programmer specifies, how it is translated to machine language

(ML), how the machine interprets the ML code.• Performance impact of s/w and h/w designs; what makes programs run

slowly, what h/w features can speed up the execution of programs.

° Learn perenial ideas in computer science and engineering• Principle of abstraction, used to study and build complex systems as layers• Use Hardware Description Languages (Verilog) to design and study

correctness and performance of hardware blocks at various detail levels;- Structural vs. Behavioral Specification

• Stored program concept: instructions and data stored in memory• Raw data (binary bit patterns) “mean” different things (integers, floating

point numbers, chars, etc.); program determines what the meaning is.• Principle of Locality, exploited in a memory hierarchy• Greater performance by exploiting instruction parallelism (pipelining)• Compilation vs. interpretation to move down the layers of the computer

system• Principles/Pitfalls of Performance Measurement


Topics

° Intro to Performance Evaluation Techniques (Measurement)

° Instruction Set Architecture: specification vs. implementation.

° Translation process (e.g., Compilation, Assembly)

° Levels of Interpretation (e.g., Microprogramming)

° Memory Hierarchy (e.g., registers, cache, mem, disk, tape)

° Pipelining and Parallelism (ILP)

° Static vs. Dynamic Scheduling of Instructions (partial coverage)

° Indirection and Address Translation

° Synchronous and Asynchronous Control Transfer

° Timing, Clocking, and Latching

° CAD Programs, Hardware Description Languages, Simulation

° Physical Building Blocks (e.g., CLA, CSA)

° Understanding Technology Trends


What is really “Computer Architecture”

° Computer Architecture =

Instruction Set Architecture (ISA) +

Machine Organization (MO) + •••

° ISA ≡ Definition of What the Machine Does,- Logical View;- What the executable perceives as the capabilities of the

underlying H/W.

° MO ≡ How Machine Implements ISA,- Physical Implementation;- Logic Gates;- Higher Level Structures (registers, ALUs, memories,

etc.)

° In CPSC321 we will study both


Instruction Set Architecture (ISA)

“... the attributes of a [computing] system as seen by the programmer, i.e., the conceptual structure and functional behavior, as distinct from the organization of the data flows and controls the logic design, and the physical implementation.” – Amdahl, Blaaw, and Brooks, 1964

An ISA encompasses:-- Organization of Storage (registers, memory)-- Primitive Data Types & Data “Structures”:Encodings & Representations (how the particular values are represented in the memory) integer, floating point, fixed point, character, arrays, etc.

-- Instruction Set

-- Instruction Formats

-- Modes of Addressing and Accessing Data Items and Instructions

-- Exceptional Conditions and their Handling Modes


The Instruction Set: a (the?) Critical Interface

instruction set

Applications/Systems Software: executable code

Hardware: actual machine


What is “Computer Architecture”?

I/O system

Processor

CompilerOperating System

(UNIX, W2k,VAX/VMS)

Applications (Netscape)

Digital DesignCircuit Design

Instruction Set Architecture

Datapath & Control

TransistorsIC layout

MemoryHardware

Software Assembler

CPSC 321

° Coordination of many levels of abstraction• hide unnecessary implementation details• helps us cope with enormous complexity of real systems

° Under a rapidly changing set of forces

° Design, Measurement, and Evaluation


Example ISAs (Instruction Set Architectures)

° Digital Alpha (v1, v3) 1992-98

° HP PA-RISC (v1.1, v2.0) 1986-96

° Sun Sparc (v8, v9) 1987-97

° SGI MIPS (MIPS I, II, III, IV, V) 1986-96

° Intel (8086,80286,80386, 1978-99 80486,Pentium, MMX, ia64)


Impact of changing an ISA

° Early 1990’s Apple switched instruction set architecture of the Macintosh

• From Motorola 68000-based machines• To PowerPC architecture• Upside? Downside?

° Intel 80x86 Family: many implementations of same architecture• Upside: program written in 1978 for 8086 can be run on latest Pentium chip• Downside?


Example: MIPS R3000 Instruction Set Architecture

° Instruction Classes:• Load/Store;• Computational;• Jump and Branch;• Floating Point

- via coprocessor;• Memory Management;• Special, System Support.

° 3 Instruction Formats: all 32 bits wide

OP Rs Rt rd sa funct

OP Rs Rt Immediate

OP jump target

R0 - R31

PC

HI

LO

32 GeneralPurposeRegisters32 bits wide

01234

...

...

.

.

.

.

.

.

.

.

.2n-1 Main Memory:

Total Size: 2n

Word Size: 4 bytes (32bits)


The Big Picture

Control

Datapath

Memory

Processor“CPU”Datapath+ControlUnit

Input

Output

1 Since 1946 all computers have had 5 components (Von Newmann Architecture)

Interconnection Structures (buses)


Forces Shapping Computer Architecture Trends

ComputerArchitecture

Technology ProgrammingLanguages

Systems Software OrganizationHistory

Applications

Cleverness


Forces Acting on Computer Architecture

° R-a-p-i-d Improvement in Implementation Technology:• IC: integrated circuit; invented 1959• SSI ® MSI ® LSI ® VLSI: dramatic growth in number transistors/chip Þ

ability to create more (and bigger) FUs per processor; • bigger memory Þ more sophisticated applications, larger databases

° Tomorrow’s Science Fiction: ubiquitous computing: computers embedded everywhere

° New Languages: Java, C++ ...


Technology Trends

° In ~1985 the single-chip processor (32-bit) and the single-board computer emerged

• Workstations, personal computers, multiprocessors have been riding this wave since

° In the 2002+ timeframe, these look like mainframes compared to single-chip computer (maybe 2 chips)

DRAMYear Size1980 64 Kb1983 256 Kb1986 1 Mb1989 4 Mb1992 16 Mb1996 64 Mb1999 256 Mb2002 1 Gb

DRAM chip capacity

i4004

i8086

i80386

Pentium

i80486

i80286

SU MIPS

R3010

R4400

R10000

1000

10000

100000

1000000

10000000

100000000

1965 1970 1975 1980 1985 1990 1995 2000 2005

Transistors

i80x86

M68K

MIPS

Alpha

uP-Name

Microprocessor Logic Density


Trends: Processor Performance

0100200300400500600700800900

87 88 89 90 91 92 93 94 95 96 97

DEC Alpha 21264/600Intel VC820 (Pentium III, 1.0 GHz)

DEC Alpha 5/500

DEC Alpha 5/300

DEC Alpha 4/266

IBM POWER 100

DEC AXP/500

HP 9000/750

Sun-4/

260

IBMRS/

6000

MIPS M/

120

MIPS M

2000

1.54x/year

10001100

° Performance with respect to performance of VAX-11/780


Performance Trends

Microprocessors

Minicomputers

MainframesSupercomputers

1995

Year

19901970 1975 1980 1985

Lo

g o

f P

erfo

rma

nce

• Technology Power: 1.2 x 1.2 x 1.2 = 1.7 x / year–Feature Size: shrinks 10% / yr. ® Switching speed improves 1.2 / yr.–Density: improves 1.2 x / yr.–Die Area: 1.2x / yr.

• The lesson of RISC is to keep the ISA as simple as possible:–Shorter design cycle ® fully exploit the advancing technology (~3yr)–Advanced branch prediction and pipeline techniques–Bigger and more sophisticated on-chip caches


Technology Þ Dramatic Changes

° Processor• logic capacity: 2 ´ in performance every 1.5 years; • clock rate: about 30% per year• overall performance: 1000 ´ in last decade

° Main Memory• DRAM capacity: 2 ´ / 2 years; 1000 ´ size in last decade• memory speed: about 10% per year• cost / bit: improves about 25% per year

° Disk• capacity: > 2 ´ in size every 1.5 years• cost / bit: improves about 60% per year• 120 ´ size in last decade

° Network Bandwidth• Bandwidth: increasing more than 100% per year!


The PC in 2003

° State-of-the-art PC two—three years from now:• Processor clock speed:

- 4-6000 MegaHertz (6.0 GigaHertz)• Memory capacity:

- 512 MegaBytes (0.5 GigaBytes)• Disk capacity:

- 240 GigaBytes (0.24 TeraBytes)• Will need new units!

- Mega Þ Giga Þ Tera Þ Peta


Computer Architecture Measurement and Evaluation

Architecture design is iterative: – “searching” the space of possible designs – at all levels of computer systemsDesign

Analysis

Good IdeasGood Ideas

Mediocre IdeasBad Ideas

Cost /PerformanceAnalysis

Creativity


Processor Performance (SPEC)

Year

Perf

orm

ance

0

50

100

150

200

250

30019

82

19

83

19

84

19

85

19

86

19

87

19

88

19

89

19

90

19

91

19

92

19

93

19

94

19

95

RISC

Intel x86

35%/yr

RISCintroduction

Did RISC win the technology battle and lose the market war?

performance now improves ~60% per year (2x every 1.5 years)


Applications and Languages

° CAD, CAM, CAE, . . .

° Lotus, DOS, . . .

° Multimedia, . . .

° The Web, . . .

° JAVA, . . .

° The Net Þ Ubiquitous Computing

° ???


Hierarchy of Abstractions

temp = v[k];v[k] = v[k+1];v[k+1] = temp;

lw $15, 0($2)lw $16, 4($2)sw $16, 0($2)sw $15, 4($2)

0000 1001 1100 0110 1010 1111 0101 10001010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111

IR Imem[PC]; PC PC + 4

High Level Language Program (e.g., C)

Assembly Language Program (e.g., MIPS)

Machine Language Program (MIPS)

Datapath Transfer Specification

Compiler

Assembler

Machine Interpretation

°°

• reasons to use HLL language?

C code

Assemblycode

Machinecode

ALUOP[0:3] InstReg[9:11] & MASK


Levels of Organization

SPARCstation 20 Processor

Computer

Control

Datapath

Memory Devices

Input

Output

(passive)(where programs, & data live whenrunning)

Workstation Design Target:25% of cost on Processor25% of cost on Memory(minimum memory size)Rest on I/O devices,power supplies, box

Any computer, no matter how primitive or advanced, can be divided into five parts:1. The input devices bring the data from the outside world into the computer.2. These data are kept in the computer’s memory until ...3. The datapath request and process them.4. The operation of the datapath is controlled by the computer’s controller (control unit).5. Getting the data back to the outside world is the job of the output devices.6. The most COMMON way to connect these 5 components together is to use a network of busses.


Computer Organization

Logic Designer's View

ISA Level

FUs & Interconnect

° Capabilities & Performance Characteristics of Principal Functional Units

• (e.g., Registers, ALU, Shifters, Logic Units, ...)

° Ways in which these components are interconnected to support the ISA

° Choreography of FUs to realize the ISA° Information flows between components° Logic and means by which such information flow is controlled.° Register Transfer Level (RTL) Description

° Levels of Machine Description• Register Transfer Level (RTL) • Gate Level (Digital Design)


Basic Instruction Execution Cycle

Obtain instruction from program storage

Determine required actions and instruction size

Locate and obtain operand data

Compute result value or status

Deposit results in storage for later use

Determine successor instruction

Instruction

Fetch

Instruction

Decode

Operand

Fetch

Execute

Result

Store

Next

Instruction


What needs to be specified for an ISA

° Instruction Format or Encoding• how is it decoded?

° Location of operands and result• where other than memory?• how many explicit operands?• how are memory operands located?• which can or cannot be in memory?

° Data type and Size° Operations

• what are supported° Successor instruction

• jumps, conditions, branches• fetch-decode-execute is implicit!

Instruction

Fetch

Instruction

Decode

Operand

Fetch

Execute

Result

Store

Next

Instruction


Example Organization: SPARC20

° TI SuperSPARCtm TMS390Z50 in Sun SPARCstation20

° Popular Architecture

Floating-point Unit

Integer Unit

InstCache

RefMMU

DataCache

StoreBuffer

Bus Interface

SuperSPARC

L2$ CC

MBus Module

Mbus

L64852 MBus controlM-S Adapter

SBus

DRAM Controller

SBusDMA

SCSIEthernet

STDIO

serialkbdmouseaudioRTCBoot PROMFloppy

SBusCards


Assignments

° Readings (textbook [PeHa])• Chapter 1 [quick overview];

° Lab #1 is already out. It is due the following week (one full week after your lab session)

° Projects teach architecture concepts AND system building skills• project works correctly first time?• If not, must use your analytical and deductive skills to find/fix bugs• repeat until all bugs found/fixed• debugging may take 1/2 of project time or more!


The SPARCstation 20

MemoryController SIMM Bus

Memory SIMMs

Slot 1Mbus

Slot 0Mbus

MSBI

Slot 1SBus

Slot 0SBus

Slot 3SBus

Slot 2SBus

MBus

SEC MACIO

Disk

Tape

SCSIBusSBus

Keyboard

& Mouse

Floppy

Disk

External Bus

SPARCstation 20


The Underlying Interconnect

SPARCstation 20

MemoryController

SIMM Bus

MSBI

Processor/Mem Bus:MBus

SEC MACIO

Standard I/O Bus:

Sun’s High Speed I/O Bus:SBus

Low Speed I/O Bus:External Bus

SCSI Bus


Processor and Caches

SPARCstation 20

Slot 1MBus

Slot 0MBus

MBus

MBus Module

External Cache

DatapathRegisters

InternalCache Control

Processor


Main Memory

SPARCstation 20

MemoryController

Memory SIMM Bus

SIM

M S

lot

0

SIM

M S

lot

1

SIM

M S

lot

2

SIM

M S

lot

3

SIM

M S

lot

4

SIM

M S

lot

5

SIM

M S

lot

6

SIM

M S

lot

7

DRAM SIMM

DRAM

DRAM

DRAM

DRAMDRAMDRAMDRAM

DRAMDRAMDRAM


Input and Output (I/O) Devices

SPARCstation 20

Slot 1SBus

Slot 0SBus

Slot 3SBus

Slot 2SBus

SEC MACIO

Disk

Tape

SCSIBus

SBus

Keyboard

& Mouse

Floppy

Disk

External Bus

° SCSI Bus: Standard I/O Devices

° SBus: High Speed I/O Devices

° External Bus: Low Speed I/O Device


Standard I/O Devices

SPARCstation 20

Disk

Tape

SCSIBus

° SCSI = Small Computer Systems Interface

° A standard interface (IBM, Apple, HP, Sun ... etc.)

° Computers and I/O devices communicate with each other

° The hard disk is one I/O device resides on the SCSI Bus


High Speed I/O Devices

SPARCstation 20

Slot 1SBus

Slot 0SBus

Slot 3SBus

Slot 2SBus

SBus

° SBus is SUN’s own high speed I/O bus

° SS20 has four SBus slots where we can plug- in fast I/O devices

° Example: graphics accelerator, video adaptor, ..., etc.

° High speed and low speed are relative terms


Slow Speed I/O Devices

SPARCstation 20

Keyboard

& Mouse

Floppy

Disk

External Bus

° The are only four SBus slots in SS20--``seats'' are expensive

° The speed of some I/O devices is limited by human reaction time--very very slow by computer standard

° Examples: Keyboard and mouse

° No reason to use up one of the expensive SBus slot


Summary

° All computers consist of five components• Processor: (1) datapath and (2) control• (3) Memory• (4) Input devices and (5) Output devices

° Memory Types• Cache: fast (expensive) memory are placed closer to the

processor• Main memory: less expensive memory--we can have more

° Interfaces are where the problems are – between functional units and between the computer and the outside world

° Need to design against constraints of performance, power, area and cost


Summary: Computer System Components

Proc

CachesBusses

Memory

I/O Devices:

Controllers

adapters

DisksDisplaysKeyboards

Networks

° All have interfaces & organizations

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