testing of digital circuits at ritlffeee/test_dig.pdftesting of digital circuits page 3 problem...
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![Page 1: Testing of Digital Circuits at RITlffeee/TEST_DIG.pdfTesting of Digital Circuits Page 3 PROBLEM STATEMENT We design and build a variety of digital circuits which can not be tested](https://reader034.vdocuments.us/reader034/viewer/2022042023/5e7bb17370bea1264001f859/html5/thumbnails/1.jpg)
© August 28, 2006 Dr. Lynn Fuller, Motorola Professor
Rochester Institute of Technology
Microelectronic Engineering
Testing of Digital Circuits
Page 1
ROCHESTER INSTITUTE OF TECHNOLOGYMICROELECTRONIC ENGINEERING
Testing of Digital Circuits at RIT
Dr. Lynn Fuller, Motorola Professor, Kekuut Hoomkwap, Sushil Shayka, Suebphong Yenrudee
Microelectronic EngineeringRochester Institute of Technology
82 Lomb Memorial DriveRochester, NY 14623-5604
Tel (585) 475-2035Fax (585) 475-5041
Email: [email protected] Webpage: http://www.microe.rit.edu
8-28-2006 test_dig.ppt
* Graduate Students in Microelectronic Engineering
Webpage: http://www.rit.edu/~lffeee
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© August 28, 2006 Dr. Lynn Fuller, Motorola Professor
Rochester Institute of Technology
Microelectronic Engineering
Testing of Digital Circuits
Page 2
OUTLINE
Problem Statement
Digital Circuits
Tester Hardware
Tester Software
2 Input 1 Output
..
6 input 6 Output
Summary
References
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© August 28, 2006 Dr. Lynn Fuller, Motorola Professor
Rochester Institute of Technology
Microelectronic Engineering
Testing of Digital Circuits
Page 3
PROBLEM STATEMENT
We design and build a variety of digital circuits which can not be
tested using the HP-4145 Semiconductor Parameter Analyzer.
These digital circuits often have a large number of inputs and
outputs. For example a full adder has 3 inputs and 2 outputs. A 2-
bit multiplexer has 6 inputs and 1 output. The chip technology
could be PMOS, NMOS, CMOS, TTL or Analog each requiring
different supply voltages. It is desirable to have a test system that
can be easily understood with a simple graphical interface that can
exercise these digital circuits. Test results in a format similar to the
simulation results would be useful.
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© August 28, 2006 Dr. Lynn Fuller, Motorola Professor
Rochester Institute of Technology
Microelectronic Engineering
Testing of Digital Circuits
Page 4
LIST OF DIGITAL CIRCUITS ON RIT TESTCHIPS
Inverters
2 Input NOR
XOR
2 Input NAND
RS Flip Flop
Multiplexer
Demultiplexer
Encoder
Decoder
Adder
PLA
For these types of devices a truth
table type test at low frequencies
would be sufficient.
A B Out
0 0 0
0 1 1
1 0 1
1 1 0 Out
B
A
Similar to QUICKSIM output
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© August 28, 2006 Dr. Lynn Fuller, Motorola Professor
Rochester Institute of Technology
Microelectronic Engineering
Testing of Digital Circuits
Page 5
NOR GATE AND NOR FLIP FLOP
PMOS 2 INPUT NOR PMOS
NOR RS Flip Flop
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© August 28, 2006 Dr. Lynn Fuller, Motorola Professor
Rochester Institute of Technology
Microelectronic Engineering
Testing of Digital Circuits
Page 6
PMOS TEST CHIP
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© August 28, 2006 Dr. Lynn Fuller, Motorola Professor
Rochester Institute of Technology
Microelectronic Engineering
Testing of Digital Circuits
Page 7
OTHER DIGITAL CIRCUITS
CMOS Demultiplexer CMOS 2 INPUT NAND
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© August 28, 2006 Dr. Lynn Fuller, Motorola Professor
Rochester Institute of Technology
Microelectronic Engineering
Testing of Digital Circuits
Page 8
FOUR INPUT MULTIPLEXER
Four Input Multiplexer
select output
A B Q
0 0 I0
0 1 I1
1 0 I2
1 1 I3
Q = A’B’I0 + A’BI1 + AB’I2 + ABI3
3 input AND
4 input OR3 input AND
0
1
0
1
0
1
0
1
I0
I1
I2
I3
Q
A
B
A’
B’
A’B’I0
A’BI1
AB’I2
ABI3
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© August 28, 2006 Dr. Lynn Fuller, Motorola Professor
Rochester Institute of Technology
Microelectronic Engineering
Testing of Digital Circuits
Page 9
1:4 DEMULTIPLEXER
A B Q0 Q1 Q2 Q3
0 0 I 0 0 0
0 1 0 I 0 0
1 0 0 0 I 0
1 1 0 0 0 I
Q0 = A’B’I so that when I=0 Q0 =0
or when I=1 Q0 = 1
similarly for Q1, Q2 and Q3 Q1 = A’BI
Demultiplexer
INPUTS OUTPUTS
A
B
I
Q0
Q1
Q2
Q3
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© August 28, 2006 Dr. Lynn Fuller, Motorola Professor
Rochester Institute of Technology
Microelectronic Engineering
Testing of Digital Circuits
Page 10
FULL ADDER CIRCUIT REALIZATION OF SUM
SUM COUTBA
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
CIN
TRUTH TABLE
FOR ADDITION
RULES
A
SUM
CinB
Sum = A’B’Cin + A’BCin’ +AB’Cin’ + ABCin
A
COUT
CinB
Carry Out = A’BCin + AB’Cin + ABCin’ + ABCin
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© August 28, 2006 Dr. Lynn Fuller, Motorola Professor
Rochester Institute of Technology
Microelectronic Engineering
Testing of Digital Circuits
Page 11
DIGITAL CIRCUIT TESTING
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© August 28, 2006 Dr. Lynn Fuller, Motorola Professor
Rochester Institute of Technology
Microelectronic Engineering
Testing of Digital Circuits
Page 12
LAB VIEW SOFTWARE
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© August 28, 2006 Dr. Lynn Fuller, Motorola Professor
Rochester Institute of Technology
Microelectronic Engineering
Testing of Digital Circuits
Page 13
HARDWARE FOR OUTPUT
6 Analog Outputs
Ribbon Cable
Terminal Board
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© August 28, 2006 Dr. Lynn Fuller, Motorola Professor
Rochester Institute of Technology
Microelectronic Engineering
Testing of Digital Circuits
Page 14
HARDWARE FOR INPUT
16 Analog Inputs
Ribbon Cable
Terminal Board
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© August 28, 2006 Dr. Lynn Fuller, Motorola Professor
Rochester Institute of Technology
Microelectronic Engineering
Testing of Digital Circuits
Page 15
FINAL SYSTEM
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© August 28, 2006 Dr. Lynn Fuller, Motorola Professor
Rochester Institute of Technology
Microelectronic Engineering
Testing of Digital Circuits
Page 16
CUSTOM SOFTWARE INTERFACE
Click on digital
testing icon to
invoke the lab view
software and this
main menu.
Click to select the
type of test you
wish to run.
MAIN MENU
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© August 28, 2006 Dr. Lynn Fuller, Motorola Professor
Rochester Institute of Technology
Microelectronic Engineering
Testing of Digital Circuits
Page 17
TESTING TWO INPUT ONE OUTPUT LOGIC GATES
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© August 28, 2006 Dr. Lynn Fuller, Motorola Professor
Rochester Institute of Technology
Microelectronic Engineering
Testing of Digital Circuits
Page 18
FOUR CHOICES FOR SUPPLY VOLTAGES
CLICK TO SELECT ONE
CMOS/TTL Vcc = +5 Volts
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© August 28, 2006 Dr. Lynn Fuller, Motorola Professor
Rochester Institute of Technology
Microelectronic Engineering
Testing of Digital Circuits
Page 19
PROBE CARD/WIRE CONNECTIONS
8
6
1012141618
24 2 420 22
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© August 28, 2006 Dr. Lynn Fuller, Motorola Professor
Rochester Institute of Technology
Microelectronic Engineering
Testing of Digital Circuits
Page 20
SWITCH MATRIX (MANUAL)
Supply
Vcc -V GndInputs
a b c d e f
Outputs
a b c d e f
Wire #17
Wire #8
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© August 28, 2006 Dr. Lynn Fuller, Motorola Professor
Rochester Institute of Technology
Microelectronic Engineering
Testing of Digital Circuits
Page 21
CMOS XOR GATE TESTING
Click to
Select
When
Output is
High or
Low
Click to Start TestStop Test
Test Results
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© August 28, 2006 Dr. Lynn Fuller, Motorola Professor
Rochester Institute of Technology
Microelectronic Engineering
Testing of Digital Circuits
Page 22
TESTING THREE INPUT TWO OUTPUT LOGIC GATES
3 Input OR, AND, NOR, NAND
Full Adder
CMOS Full Adder
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© August 28, 2006 Dr. Lynn Fuller, Motorola Professor
Rochester Institute of Technology
Microelectronic Engineering
Testing of Digital Circuits
Page 23
THREE INPUT TWO OUTPUT
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© August 28, 2006 Dr. Lynn Fuller, Motorola Professor
Rochester Institute of Technology
Microelectronic Engineering
Testing of Digital Circuits
Page 24
DEFINE INPUT SIGNALS / SELECT SUPPLY VOLTAGE
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© August 28, 2006 Dr. Lynn Fuller, Motorola Professor
Rochester Institute of Technology
Microelectronic Engineering
Testing of Digital Circuits
Page 25
ADDER TEST RESULTS
SUM
CARRY OUT
CARRY IN
B
A
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© August 28, 2006 Dr. Lynn Fuller, Motorola Professor
Rochester Institute of Technology
Microelectronic Engineering
Testing of Digital Circuits
Page 26
TESTING SIX INPUT SIX OUTPUT DEVICES
Multiplexer (6 inputs, 1 output)
Demultiplexer (3 inputs, 4 outputs)
Encoder
Decoder
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© August 28, 2006 Dr. Lynn Fuller, Motorola Professor
Rochester Institute of Technology
Microelectronic Engineering
Testing of Digital Circuits
Page 27
MULTIPLEXER TEST SIGNALS
Out
I0
I1
I2
I3
A
BInput Signal I0, I1, I2 or I3 is directed to the output depending on the A and B select line values
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© August 28, 2006 Dr. Lynn Fuller, Motorola Professor
Rochester Institute of Technology
Microelectronic Engineering
Testing of Digital Circuits
Page 28
MUX LAYOUT AND GATE LEVEL SCHEMATIC
I0
I1
I2
I3
Q
A
B
A’
B’
A’B’I0
A’BI1
AB’I2
ABI3
25 Transistors
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© August 28, 2006 Dr. Lynn Fuller, Motorola Professor
Rochester Institute of Technology
Microelectronic Engineering
Testing of Digital Circuits
Page 29
PMOS 4-INPUT MULTIPLEXER
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© August 28, 2006 Dr. Lynn Fuller, Motorola Professor
Rochester Institute of Technology
Microelectronic Engineering
Testing of Digital Circuits
Page 30
MUX TEST RESULTS
ABI3I2I1I0
ABI3I2I1I0
In PMOS logic low is 0 volts, logic high is -Vcc
A
B
I3
I2
I1
I0
A
B
I3
I2
I1
I0
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© August 28, 2006 Dr. Lynn Fuller, Motorola Professor
Rochester Institute of Technology
Microelectronic Engineering
Testing of Digital Circuits
Page 31
MUX TEST RESULTS
ABI3I2I1I0
ABI3I2I1I0
In PMOS logic low is 0 volts, logic high is -Vcc
A
B
I3
I2
I1
I0
A
B
I3
I2
I1
I0
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© August 28, 2006 Dr. Lynn Fuller, Motorola Professor
Rochester Institute of Technology
Microelectronic Engineering
Testing of Digital Circuits
Page 32
PMOS DEMULTIPLEXER
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© August 28, 2006 Dr. Lynn Fuller, Motorola Professor
Rochester Institute of Technology
Microelectronic Engineering
Testing of Digital Circuits
Page 33
PMOS INVERTER GAIN=4
In PMOS logic low is 0 volts, logic high is -Vcc
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© August 28, 2006 Dr. Lynn Fuller, Motorola Professor
Rochester Institute of Technology
Microelectronic Engineering
Testing of Digital Circuits
Page 34
PMOS 2-INPUT NOR
Test for PMOS Two Input NOR, Gain = 4 or 8
In PMOS logic low is 0 volts, logic high is -Vcc
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© August 28, 2006 Dr. Lynn Fuller, Motorola Professor
Rochester Institute of Technology
Microelectronic Engineering
Testing of Digital Circuits
Page 35
PMOS 2-INPUT XOR
In PMOS logic low is 0 volts, logic high is -Vcc
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© August 28, 2006 Dr. Lynn Fuller, Motorola Professor
Rochester Institute of Technology
Microelectronic Engineering
Testing of Digital Circuits
Page 36
PMOS 3-INPUT NOR
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© August 28, 2006 Dr. Lynn Fuller, Motorola Professor
Rochester Institute of Technology
Microelectronic Engineering
Testing of Digital Circuits
Page 37
PMOS 4-INPUT NOR
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© August 28, 2006 Dr. Lynn Fuller, Motorola Professor
Rochester Institute of Technology
Microelectronic Engineering
Testing of Digital Circuits
Page 38
PMOS 2-INPUT NAND
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© August 28, 2006 Dr. Lynn Fuller, Motorola Professor
Rochester Institute of Technology
Microelectronic Engineering
Testing of Digital Circuits
Page 39
PMOS 3-INPUT NAND
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© August 28, 2006 Dr. Lynn Fuller, Motorola Professor
Rochester Institute of Technology
Microelectronic Engineering
Testing of Digital Circuits
Page 40
PMOS 4-INPUT NAND
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© August 28, 2006 Dr. Lynn Fuller, Motorola Professor
Rochester Institute of Technology
Microelectronic Engineering
Testing of Digital Circuits
Page 41
PMOS NOR RS FLIP FLOP
Input R
Input S
Q
Q`
PMOS Nor RS Flipflop
In PMOS logic low is 0 volts, logic high is -Vcc
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© August 28, 2006 Dr. Lynn Fuller, Motorola Professor
Rochester Institute of Technology
Microelectronic Engineering
Testing of Digital Circuits
Page 42
PMOS NAND RS FLIP FLOP
PMOS 2 - Input Nand RS - Flip Flop
R
S
Q
Q’
In PMOS logic low is 0 volts, logic high is -Vcc
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© August 28, 2006 Dr. Lynn Fuller, Motorola Professor
Rochester Institute of Technology
Microelectronic Engineering
Testing of Digital Circuits
Page 43
PMOS CLOCKED DATA LATCH
PMOS Clocked Data Latch
C
D
Q
Q`
In PMOS logic low is 0 volts, logic high is -Vcc
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© August 28, 2006 Dr. Lynn Fuller, Motorola Professor
Rochester Institute of Technology
Microelectronic Engineering
Testing of Digital Circuits
Page 44
JK FLIP FLOP
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© August 28, 2006 Dr. Lynn Fuller, Motorola Professor
Rochester Institute of Technology
Microelectronic Engineering
Testing of Digital Circuits
Page 45
PMOS FULL ADDER
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© August 28, 2006 Dr. Lynn Fuller, Motorola Professor
Rochester Institute of Technology
Microelectronic Engineering
Testing of Digital Circuits
Page 46
PMOS CLOCKED DATA LATCH
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© August 28, 2006 Dr. Lynn Fuller, Motorola Professor
Rochester Institute of Technology
Microelectronic Engineering
Testing of Digital Circuits
Page 47
PMOS ANALOG MUX
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© August 28, 2006 Dr. Lynn Fuller, Motorola Professor
Rochester Institute of Technology
Microelectronic Engineering
Testing of Digital Circuits
Page 48
SUMMARY
1. The system works great.
2. Direct comparison between QUICKSIM output and tester
output is possible.
3. Easy to use graphical interface. (Freshman to Graduate
Students have used the system successfully)
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© August 28, 2006 Dr. Lynn Fuller, Motorola Professor
Rochester Institute of Technology
Microelectronic Engineering
Testing of Digital Circuits
Page 49
REFERENCES
1. LabView Software, National Instruments,
http://www.natinst.com