tcu status a.di cicco, m.della pietra, g.fiorillo,p.parascandolo adele di cicconapoli, 27 novembre...
TRANSCRIPT
TCU STATUS
A.Di Cicco, M.Della Pietra, G.Fiorillo,P.Parascandolo
Adele DI CICCOAdele DI CICCO Napoli, 27 Novembre 2003Napoli, 27 Novembre 2003
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Flow Chart
PMTTrigger condition logic
Global trigger request
Local trigger request
Global drift or busy?
Acquire all crates
No trigger
Acquire only fired
pixels
Local drift or busy?
PMT-pixels coincidences logic
Pixels Majority/Pattern logic
PMT local trigger request?
Wire planes coincidence Logic (pixel fired)
No Trigger request
AWS
Discriminator
LTCU - PMT AWS - LTCU
Discriminator
TCU
TS
PMT
Adele DI CICCOAdele DI CICCO Napoli, 27 Novembre 2003Napoli, 27 Novembre 2003
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GLOBAL/LOCAL trigger BUSY logic
After validation of a global trigger request TS gives the GLOBAL_DRIFT signal to all v789 boards
During a GLOBAL_DRIFT, TS doesn’t accept any other trigger request, while, during a GLOBAL_BUSY (DAQ dead time for acquisition data download from all chambers) it accepts only a Local Trigger request
During LOCAL_DRIFT it doesn’t accept any other trigger request in the same crate
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Trigger classification depends on:
Energy deposition/number of PMT fired.
Detector occupancy
2D/3D Pattern of fired pixels
TS gives GLOBAL trigger when a MAJORITY condition is met in PMT logic
Otherwise the wires define trigger locality
TS GLOBAL/LOCAL Logic
Adele DI CICCOAdele DI CICCO Napoli, 27 Novembre 2003Napoli, 27 Novembre 2003
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T600 pixel definition Pixel fired
1 pixel area: ~ 0.6 m2 Total Number of Pixels ~ 80 1 pixel area: ~ 0.14 m2 Total Number of Pixels ~ 405
86.4 cm28.8 cm 9.6 cm
1 pixel area: ~ 0.015 m2 Total Number of Pixels ~ 3780
32 x 3 Induction II
wires
32 x 3 Collection
wires
32 Collection wires
32 Induction II wires
32x9
Collection wires
32x9
Induction II wires
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TCU FEATURES
• ≥1 boards per chamber (depending on segmentation)
• VME standard
• Each TCU module receives as input – Naws signals from the 20 AWS-LTCU boards of a chamber
• Naws=40 if sectors are made of 32x9 wires• Naws=120 if 32x3 wires• Naws=360 if 32 wires
– Npmt signals from PMT-LTCU – Next from external (spectro, beam, ...)
• checks Majority, 2D/3D Pattern logic conditions
• event is labelled according to topology
• TCU performs coincidences between:
The wire planes (in a 3s time windows) PMT signals External requests
Adele DI CICCOAdele DI CICCO Napoli, 27 Novembre 2003Napoli, 27 Novembre 2003
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Pixel detection(using only two coordinates)
3s
IND2
IND2 streched
Collection
Pixel
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PMT
Induction II signal
Collection signal
LTCU T1 signal
LTCU T2 signal
TCU Trigger request
TS Trigger signal
T 3 s
T 1.5 ms Trigger dead time
n-bit
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It is necessary to store the evolution in time of the number of fired pixel
For a long track consecutive pixels will be fired (in different time) according to the track direction. In this case the event is global but we could acquire it as many local events.
In case of Supernova burst several pixels could be fired with a big spacing in position and in time.
Pattern Recognition
It is necessary to make consecutive pictures to store detector’s activity
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Rack 11Rack 13
General Idea on Partial majority
• Window runs on the detector
• Majority condition is checked for each window
Adele DI CICCOAdele DI CICCO Napoli, 27 Novembre 2003Napoli, 27 Novembre 2003
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General scheme TCU
IND
2[12:0]
FPGA1WIRES
Coincidences
FPGA2WIRES
Coincidences
FPGA3WIRES
Coincidences
MAJ
PMTFPGAXilinx
Spartan
PMT signal
CO
LL
[8:0]
IND
2[12:0]
CO
LL
[8:0]
CO
LL
[8:0]
IND
2[12:0]
VMEINTERFACE
XilinxSpartan
Address
Data
16
32
S_OUT
DIAG
LOAD
EM
FORCE
CS[3:0]
SEL[2:0]
CS2CS1CS0
CS3
Adele DI CICCOAdele DI CICCO Napoli, 27 Novembre 2003Napoli, 27 Novembre 2003
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Wire Coincidences FPGA Features
• The detector is subdivided in three (or more) sections
• Each section is monitored by a different WC-FPGA• Each WC-FPGA
Makes coincidences between wires of different directionsChecks the occupancy of the sectionDetects spots, tracks, ...
Adele DI CICCOAdele DI CICCO Napoli, 27 Novembre 2003Napoli, 27 Novembre 2003
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receives an N bit Word which defines PMT status
makes concidences between PMT and wiresmakes global trigger proposals
PMT FPGA Features
VME interface Features
is directly interfaced to VME CPU and it establishes communication between VME and the rest of the board.
Adele DI CICCOAdele DI CICCO Napoli, 27 Novembre 2003Napoli, 27 Novembre 2003
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Wire CoincidencesFPGA
preliminary
SYNCBLK
SYNCBLK
ANDBLK
9
13
INA
INB
MASK
9
13
MASK 9
AA
BB
13
A0_B[4:0]
A1_B[5:1]
A2_B[6:2]A3_B[7:3]
A4_B[8:4]
A5_B[9:5]
A6_B[10:6]
A7_B[11:7]
A8_B[12:8]
FLASH
ADR[4:0]
ENC
REG_A
REG_B
REG_C
SUMBLK
VTH
InternalXilinx
Memory
WholeCarpet
Majority
ENCA
ENCA2
ENCA3
MJLOCAL
MJGLOBAL
ADDRESSGENERATOR
FLASH
CLK PIPELINE
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Blocks description
SYNC BLKSYNC BLK syncronizes the data and makes a picture of the detector when FLASH signal occours
AND_BLKAND_BLK makes coicidences between fired wires
ADDRESS GENERATORADDRESS GENERATOR produces the address for Multiplexer to select the sector
ENCENC sums pixel inside the sector
REG_A, REG_B, REG_CREG_A, REG_B, REG_C store three adjacent sectors
SUMSUM sums pixels from adjacent sectors
Adele DI CICCOAdele DI CICCO Napoli, 27 Novembre 2003Napoli, 27 Novembre 2003
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R
RR
RR
R
R R
R
WW
W
W
Ambiguous pixelsW wrong pixel
R right pixel
Nature of detector introduces ambiguity
Adele DI CICCOAdele DI CICCO Napoli, 27 Novembre 2003Napoli, 27 Novembre 2003
R
RW
W
RW
R
W
W
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Rack 11Rack 13
Possible solutions
Higher segmentation
In this case LTCU will produce a FAST OR from a smaller number of boards
TCU will have more input signals
Possibility to send trigger to single board in the crate
Use of Induction1 plane Adele DI CICCOAdele DI CICCO Napoli, 27 Novembre 2003Napoli, 27 Novembre 2003
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R
R
R
WW
W
R R R
W W
W
W
W
Third plane use
Adele DI CICCOAdele DI CICCO Napoli, 27 Novembre 2003Napoli, 27 Novembre 2003
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2nd level trigger
Possibility to have a two levels trigger: Every time a trigger condition is met the TCU
produces a 1° level trigger and sends the proposal to the Supervisor
The TCU records the plane pictures before and after the event and performs a topological analysis in order to define locality/globality and type of event. It produces a second level trigger.
Adele DI CICCOAdele DI CICCO Napoli, 27 Novembre 2003Napoli, 27 Novembre 2003
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Uniboard (Parascandolo,Masone)
ICCMASTER
ICCSLAVE1
ICCSLAVE2
ICCSLAVE3
Spartan II
FAUXSpartan II
VME(J2)
Spartan II
VME(J1)
Spartan II
3 3 3
Adele DI CICCOAdele DI CICCO Napoli, 27 Novembre 2003Napoli, 27 Novembre 2003
FIFOA
FIFOB
FIFOA
FIFOB
FIFOA
FIFOB
FIFOA
FIFOB
18 18 18 18 18 18 18 18
FF FF FF FF
EF
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UNIBOARD
VME INTERFACE Xilinx Spartan XC2S100
INPUT STAGE Xilinx Spartan XC2S100 SYNCHRONOUS FIFO IDT72V263
80 programmable input / output
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Conclusions
• We are working to define algorithms to perform a topological analisys of event in order to define locality and globality of event
• We are studing the possibility to use the third coordinate
• We are evaluating the possibility to have higher segmentation and two trigger level.