systematic pattern dependent variations: an incomplete...

Puneet Gupta (puneet@

ee.ucla.edu)

Systematic Pattern Dependent

Variations: An Incomplete

Introduction

Puneet Gupta

[email protected]


ee.ucla.edu)

What Makes IC Behavior

Unpredictable ?

•Reasons for unpredictability

–Inadequate models

•Signoff criteria for 90nm BSIM device models: ~10% accuracy

threshold for delay and 75% for leakage power

–Variations in manufacturing or operating conditions

Litho/Process

(Tech. Development)

Library

(Library Team)

Layout & libs

(Corner Case

Timing)

Design

(ASIC Chip)

Mask & W

afer Processing

(Foundry)

Design Rules

Device Models

Tapeout

Layout

(collection of polygons)

Chips!


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Taxonomy of Variations

•Source

–Process: Litho, CMP, overlay

•Typically permanent

–Environment: Vdd, temperature

•Typically transient

•Nature

–Systematic: metal dishing, litho proximity effects

–Random: dopantfluctuations, material variations, LER

•Spatial Scale

–Intra-die: litho proximity, CMP

–Inter-die: material variations

•Includes wafer-to-wafer, lot-to-lot variations

–What is a lot ??


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Progress = Random �

Systematic

•Random variations

–Seemingly or truly random behavior

•E.g., dopantfluctuations

–Predictable but too complex to model

•E.g., crosstalk

•Typically handled by worst-casing or statistics

•Modeling and computational advancements �

more effects can be

modeled

•Systematic variations

–Can be modeled, predicted given layout

•E.g., CMP-dependent topography variation

–Some variations are “trend-systematic”

•E.g., relevant circuit parameter always increases though process

parameter may be random

–E.g., defocus (more later)

Variations: random now, systematic tomorrow


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Major FEOL Source: Litho


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Basics of IC Manufacturing

•Image the design layout onto the silicon wafer (photolithography)

–Similar to photography but with wave optics

–Goal: get accurate critical dimension (CD)

•Process the transferred image to create the needed layers (implant,

deposit or grow material)

•600+ processing steps, 30+ layers

–Every step is an increase in uncertainty and cost

Deposit material and

spin coat resist

Expose resist

Develop

photoresist

Etch material

Strip resist

Dice wafer

Package die

Wafer

Material (polysilicon, copper)

Photoresist(positive resist here)

Repeat for all layers


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Lithography Basics

•The famous Raleigh Equation:

λ λλλ: Wavelength of the exposure system

NA: Numerical Aperture (sine of the capture angle of the

lens, and is a measure of the size of the lens system)

k 1: process dependent adjustment factor

•Exposure = the amount of light or other radiant energy

received per unit area of sensitized material.

•Depth of Focus (DOF) = a deviation from a defined

reference plane wherein the required resolution for

photolithography is still achievable. (affects 3D resist)

•Process Window = Exposure Latitude vs. DOF plot for

given CD tolerance


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•The light interacting with the mask is a wave

•Any wave has certain fundamental properties

–Wavelength (λ)

–Direction

–Amplitude

–Phase

•RET is wavefront engineering

to enhance lithography

by controlling these properties

RET Basics λ

Amplitude

Direction

Phase

Courtesy F. Schellenberg, Mentor Graphics Corp.


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Direction: Illumination

•Regular Illumination

•Many off-axis designs (OAI)

–Annular

–Quadrupole / Quasar

–Dipole

+or


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Acceptable

Unacceptable

130 nm lines, printed

at different pitches

Quasar illumination

NA=0.7

Isolated

Dense

OAI: Impact on PD

•Off axis amplifies certain

pitches at the expense of

the others �“Forbidden”

pitches

–Quasar / Quadrupole

Illumination

•Amplifies dense 0°, 90 °

lines

•Destroys ±45°lines

–Dipole Illumination

•Prints only one orientation

•Must decompose layout

for 2 exposures

Depth of Focus Gra

ph r

efer

ence

: S

och

a et

al.

“F

orb

idd

en P

itch

es f

or

130 n

m

lith

ogra

ph

y a

nd b

elow

”,

in O

pti

cal

Mic

roli

tho

gra

ph

y X

III,

Proc. SPIE Vol. 4000

(2000),

1140-1

155.

0

0.51

1.5

200

400

600

800

1000

1200

1400

Pitch (nm)


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Amplitude: OPC

•Optical Proximity

Correction (OPC)

modifies layout to

compensate for

process distortions

–Add non-electrical

structures to layout

to control

diffraction of light

–Rule-based or

model-based


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Lithographic Defocus

•Defocus = deviation from best focus

–Causes blurring of the image

•Photolithography + defocus

–Causes bad printing, linewidth(e.g., gate length) variation

–Is caused by wafer not being flat enough

–Few 100nm of defocus �10%-20% change in CD

–One of the major causes of gate length variation


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Defocus and Layout:

Systematic Interactions

•An example of “trend-systematic”variation

Defocus

Line Width

Width of dense lines increases

(SMILE)

Width of isolated lines decreases

(FROWN)

Assumed variation if

layout pattern is

assumed to be

random

Actual variation if dense-

ness of lines is taken into

account

Actual variation if iso-

nessof lines is taken into

account


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0.04

0.06

0.08

0.1

0.12

0.14

0.16

0.18

0.2

0.22

0.0

0.1

0.2

0.3

0.4

0.5

0.6

SRAF2

SRAF1

No SRAF

DOF�

CD�

2 SB

1 SB

W/O SB

SB = Scattering Bar ≡ ≡≡≡SRAF

Thanks: Chul-Hong Park, UCSD

SRAFsand Depth of Focus

•Dummy non-printing shapes or sub-resolution assist features (SRAFs)

inserted to make isolated lines look like dense �

remove iso-dense bias

•Forbidden pitch: spacing that does not accommodate assist features


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SRAFsand Bossung Plots

•Bossung plot

–Measurement to evaluate lithographic manufacturability

–Maximize the common process window

–Horizontal axis: Depth of Focus (DOF); Vertical axis: CD

•SRAF OPC

–Improves process margin of isolated pattern

–Larger overlap of process window between dense and isolated lines

-202060100

140

180 -0.8

-0.6

-0.4

-0.2

00.2

0.4

0.6

0.8

DOF (um)

CD (nm)

12 11.5

11 10.5

10 9.5

Bias OPC

SRAF OPC

-20

20

60

100

140

180 -0

.8-0.6

-0.4

-0.2

00.2

0.4

0.6

0.8

DOF (um)

CD (nm)

12

11.5

11

10.5

10

9.5


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Forbidden Pitches

•SRAF insertion

–Leads to more allowed pitches

–Needs discrete spacingsbetween primary features

–More is better

-30105090130

170 10

0300

500

700

900

1100

1300

1500

pitch (nm)

CD (nm)

W/O OPC(Best DOF)

W/O OPC(Defocus)

Bias OPC(Defocus)

SRAF OPC (Defocus)

#SB=1

#SB=2

#SB=3

#SB=4

Allowed Forbidden

x+δx�

x �

Better than


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Similar Problems at Etch Step

40

60

80

100

120

100

600

1100

1600

2100

Space (nm)

CD (nm)

Resist CD

Etch CD

Active

SRAF

Poly

Etch dummy

•Etch CD is the “real”manufactured CD

–Resist CD still needs control because etch CD depends on it!

•Pattern dependence in etch caused by reactant depletion

–Wafer-scale (macroloading) as well as feature-scale (microloading)

–Complex chemical processes �tough and computationally expensive to

model �

no usable “chip-scale”model yet

–Two common methods to deal with etch-resist skew

•Pre-bias drawn CD to change the resist target

•Insert etch dummy features to make local neighborhood uniform


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It is not Only About L

•It is also about W

–Diffusion rounding

•It is also about via/contact

coverage

•It is also about sidewall

angle, line edge

roughness (LER), etc

Courtesy B.P. Wong, Chartered Semiconductors


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Major BEOL Source: CMP


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CMP & Area Fill

•Cause of CMP variability

–pad deforms over metal feature

–greater ILD thickness over dense regions of layout

–“dishing”in sparse regions of layout

–huge part of chip variability budget used up (e.g.,

4000ÅILD variation across-die)

wafer carrier

silicon wafer

polishing pad

polishing table

slurry feeder

slurry

Chemical-Mechanical Planarization (CMP)

Polishing pad wear, slurry composition, pad elasticity make thisa

very difficult process step


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Dishing and Erosion

•Dishing can thin the wire or pad, causing higher

resistance wires or low-reliability bond pads

•Erosion can also result in a sub-planar dip on

the wafer surface, causing short-circuits

between adjacent wires on next layer

Oxide

Copper

Oxide

erosion

Copper dishing


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CMP and CD Variation

(a) Side view showing thickness variation over regions with dense and

sparse layout.

(b) Top view showing CD variation when a line is patterned over a region

with uneven wafer topography, i.e., under conditions of varying

defocus.


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Dummy Fill Synthesis

Area fill feature insertion

Decreases localdensity variation

Decreases the ILD thickness variation after CMP Post-CMP ILD thickness

Features

Area fill

features

•Typical 90nm and below metal fill process constraints

–Density constraints over multiple window sizes on multiple layers

simultaneously

–“Smoothness”constraints

–Via fill for dielectric stability

–Looks like real routes (track fill)

–Driven by actual CMP models


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Fixed-Dissection Regime

•To make filling more tractable, monitor only fixed set of w ×w windows

–offset = w/r (example shown: w = 4, r = 4)

•Partition n x n layout into nr/w×nr/w fixed dissections

•Each w ×w window is partitioned into r2tiles w/r

Overlapping

windows

w

n

tile


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CMP and DFM

Topography

R,C Parasitics

Design Timing

and Power

Depth of Focus

Lithographic

Manufacturability

CMP

•CMP and Fill effects

•Cu erosion and dishing cause resistance change

•Dummy fill to aid CMP in achieving planarity causes

capacitance change

•Topographic variation translates to focus variation for

imaging of subsequent layers � ��

reduced process

window � ��

linewidthvariation � ��

R, C variation

•CMP interacts with design as well as lithography closely


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The Story does not end Here:

New Interactions: Strain

•Channel strain is the new trick in device

engineer’s bag to increase performance

–Compressive stress increases PMOS Idsat

–Tensile stress increases NMOS Idsat

•Strain sources

–STI

–Dual stress liners (DSL), Si-Ge, etc


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NP

Buried oxide

NP

Buried oxide

NP

Buried oxide

Fig. 5.

SE

M c

ross-secti

on o

f a

n S

RA

M c

ell

featu

res

ten

sil

e an

d com

pressiv

e li

ner in

N

MO

S an

d P

MO

S

resp

ecti

vely

.

tensile

Compr

N

P

Ten

sil

e n

it

Co

mp

r n

it

Co

nta

ct

ST

Layout Sensitivities of DSL

Dual Stress Liner

•Poly pitch

•Contact space to Poly

•Contact Pitch

•Affects the channel strain and Mobility

Slide Courtesy B.P. Wong, Chartered Semiconductors


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Remote Versus Nearby

Contacts

Contacts are 60nm

from the gate

Contacts are 90nm

from the gate

Contacts are 180nm

from the gate

High channel stress

Low channel stress

Stress Simulation courtesy of V. Moroz(Synopsys)



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0

0.2

0.4

0.6

0.81

1.2

12

3

Layout

Normalized Average Channel Stress

Effect of Contact & Dummy Poly

on Channel stress

Dummy PC

Dummy PC+CA contacts

Self stress All PC and CA pitch are minimum pitch

min PC pitch

min PC pitch



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Shallow Trench Isolation

STI

STI

STI

Larger the spacing

between trenches, less

overall stress

Amount of stress varies

depending on Active size

and trench size

Source: Nano-CMOS Circuit and Physical Design

1.Need dummy active to keep trench size consistent

2.Use dummy transistors to increase spacing

between trenches



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The Story does not end Here:

New Interactions: WPE

•WPE = Well Proximity

Effect

•Unintentional dopants

�Vtdepends on

proximity to well edge

•Modeled in BSIM4+ by

SCA, SCB parameters

–Connected wells in

digital designs a savior

for modeling


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Let us end with some

randomness: RDF

•RDF = Random dopantfluctuations

–Not only number but also location of dopants


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One Example

Sourc

e: ‘

Ran

dom

Dop

ant

Indu

ced T

hre

shold

Volt

age

Low

erin

g a

nd F

luct

uat

ions

in S

ub-0

.1 u

m M

OS

FE

T’s

: A

3-D

“Ato

mis

tic”

Sim

ula

tion S

tud

y’,

Ase

nA

senov,

IEE

E T

rans

on E

lect

ron D

evic

es, V

ol

45, N

o 1

2, pp 2

505-2

513, D

ec 1

998.

0.78V threshold

0.56V threshold

Both devices have 170

dopantsin the channel

depletion region



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0.00

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

04

812

16

1/squrt(LW) [1/um]

s(DVth)

65nm Vth Mismatch (nMOS)

65nm Vth Mismatch (nMOS)

Measured

L=0.06um

Measured

L=0.6um

•Vthmismatch shows strong L-dependency

•Design using larger devices �random variation that can be

systematically reduced!

•Vthmismatch shows strong L-dependency

•Design using larger devices �random variation that can be

systematically reduced!

SPICE

10X min L



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Summary

•There are a lotof systematic variation sources

–Ongoing research to make random variations

systematic

–Ongoing research to model and compensate

systematic variations in process as well as design

•Many seemingly random variations are “trend-

systematic”(e.g., focus-dependent CD)

•Impact of many random variations can be

pattern-dependent (e.g., Vtvariation

dependence on gate area)

systematic pattern dependent variations: an incomplete...

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