1

Some thoughts on the New Small Wheel Trigger Issues

V. Polychronakos, BNL10 May, 2011

2

The Problem with High pT Triggers

ProposedTriggerProvide vector A at Small Wheel Powerful constraint for real tracksWith pointing resolution of 1 mrad it will also improve pT resolutionCurrently 96% of High pT triggers have no track associated with them

Current Endcap TriggerOnly a vector BC at the Big Wheels is measuredMomentum defined by implicit assumption that track originated at IPRandom background tracks can easily fake this

3

4

Toy Monte CarloGenerate track at a given angle

Track crosses a strip at a random position

Generate primary ionization clusters Poisson distributed

Generate number of electrons for each cluster

Take strip with earliest time and charge over a certain threshold as the track’s coordinate

Strip pitch = 0.5 mm

Reconstruct track and compare slope with the generated oneNo transverse diffusion considered but effect is negligible for the first arriving cluster

5

Sanity CheckDistributions of MC generated Events

10o tracksEarliest arrival10o tracks

6

Average spatial resolution below 0.5 mm for all angles in Small Wheel acceptanceTime of first cluster above threshold mostly below 25 nsecRequiring, e.g, 3 out of 4 detectors to be within a BC should result in ~100% efficiencyAddress of strips can be directly used in a lookup table (e.g. Content addressable memories similar to FTK

40 deg

30 deg

20 deg

10 deg

40 deg

10 deg

30 deg

20 deg

Position and Timing Resolution as a function of incidence angle

7

Slope Resolution

L= 10 cm

L= 20 cm

L= 25 cm

8

Trigger/DAQ Block Diagram

9

Block Diagram of the IC being designed

For TGC there will be fewer (16 or 32) channels with LVDS outputs of individual discriminatorsAll other features remain the same

To SRS

10

Timing Diagram

40 MHz BC clock convenient for LHC but any clock can be used to related hit with trigger accept

Fine Time to next BC

11

Small Wheel Counting Rates in kHz/cm2Radiation flux maps from GCALOR (M.Shupe)

750.0 760.0 90.0 100.0 0.676965 750.0 760.0 100.0 110.0 0.531924 750.0 760.0 110.0 120.0 0.462974 750.0 760.0 120.0 130.0 0.428746 750.0 760.0 130.0 140.0 0.372947 750.0 760.0 140.0 150.0 0.353284 750.0 760.0 150.0 160.0 0.293642 750.0 760.0 160.0 170.0 0.262680 750.0 760.0 170.0 180.0 0.226831 750.0 760.0 180.0 190.0 0.188895 750.0 760.0 190.0 200.0 0.186949 750.0 760.0 200.0 210.0 0.185153 750.0 760.0 210.0 220.0 0.158295 750.0 760.0 220.0 230.0 0.134239 750.0 760.0 230.0 240.0 0.128854 750.0 760.0 240.0 250.0 0.113969 750.0 760.0 250.0 260.0 0.103517 750.0 760.0 260.0 270.0 0.102746 750.0 760.0 270.0 280.0 0.100118 750.0 760.0 280.0 290.0 0.840098E-01 750.0 760.0 290.0 300.0 0.954108E-01

750.0 760.0 300.0 310.0 0.861459E-01 750.0 760.0 310.0 320.0 0.870514E-01 750.0 760.0 320.0 330.0 0.797542E-01 750.0 760.0 330.0 340.0 0.706889E-01 750.0 760.0 340.0 350.0 0.703702E-01 750.0 760.0 350.0 360.0 0.565054E-01 750.0 760.0 360.0 370.0 0.543138E-01 750.0 760.0 370.0 380.0 0.434476E-01 750.0 760.0 380.0 390.0 0.457534E-01 750.0 760.0 390.0 400.0 0.433348E-01 750.0 760.0 400.0 410.0 0.469865E-01 750.0 760.0 410.0 420.0 0.401987E-01 750.0 760.0 420.0 430.0 0.341343E-01 750.0 760.0 430.0 440.0 0.326369E-01 750.0 760.0 440.0 450.0 0.302566E-01 750.0 760.0 450.0 460.0 0.287393E-01 750.0 760.0 460.0 470.0 0.285842E-01 750.0 760.0 470.0 480.0 0.278045E-01 750.0 760.0 480.0 490.0 0.206697E-01 750.0 760.0 490.0 500.0 0.187729E-01 750.0 760.0 500.0 510.0 0.245147E-01

Z1 Z2 R1 R2 Rate Z1 Z2 R1 R2 Rate

EIL0(CSC)

EIL1

EIL2

EIL3

Trigger

12

Taking ONLY the first arriving hit per 64-Channel IC reduces the number of Channels used for Trigger from 2M ~30,000, while maintaining spatial resolution <0.5 mm

But are we paying a price for this? i.e. efficiency loss?

Consider worst case at h= 2.4:Rate r = 10 kHz/cm2, strip length l = 50 cm, strip width w = 0.5 mm

Occupancy/BC = rlwt = 6.25x10-4

Probability per Front End IC [%]

Probability per Chipper Bunch Crossing

Probability per Chip per 3 Bunch Crossings

Probability per Chipper 5 Bunch Crossings

# Hits

0 96.1 88.7 81.9

1 3.8 10.6 16.5

>=2 0.1 0.6 1.6

13

14

•Can transfer 2 addresses in 1 BC•If 2 parallel paths each handling 16 chips then 4 hits can be moved in 1 BC•Is 200 MHz clock too aggressive? (long ~0.5 m connections)•Develop custom digital ASIC?

15

FE ASICsclk

Link controller

Link controller

Data MoverData

Mover

TimingTiming

portport

portport

portport

Controlport

Controlport

Front-Ende-links

GBTManagement

logic

GBTManagement

logic

Slow Control ASICe-link

clk40T<15:0>

e-link

e-port

e-port

ReadoutControl Din

Dout

clk

e-link (6 wires)LVDS: Clk80, Din, Dout

32 ports80Mb/s

Timing

T<15:0>

GBT-SCAGBT-SCA

GBT13

FE ASICsclk

Link controller

Link controller

Data MoverData

Mover

TimingTiming

portport

portport

portport

Controlport

Controlport

Front-Ende-links

GBTManagement

logic

GBTManagement

logic

Slow Control ASICe-link

clk40T<15:0>

e-link

e-port

e-port

ReadoutControl Din

Dout

clk

e-link (6 wires)LVDS: Clk80, Din, Doute-link (6 wires)LVDS: Clk80, Din, Dout

32 ports80Mb/s

Timing

T<15:0>

GBT-SCAGBT-SCA

GBT13

GBTx (Gigabit tranceiver) Chipset, being developed at CERN•Will combine bidirectional data transfer, TTC, and DCS•4.8 Gbps (2.56 Gbps data, 160 Mbps DCS, 640 MBps TTC), + (1.28 Gbps FEC, 160 Mbps Header)•First generation prototypes exist, a clock driver error resulted inreduced bandwidth•Production estimated by the end of 2012

16

17

An Example

18

Existing chip developed by the CDF Pisa group

19

Time Required (BC)Muon TOF 1Detector Response (drift time) 1Front End Response (peaking time) 2 -- 3Front End to GBTx 2To USA15 (80 m fiber) 15GBTx FPGA to CAM (up to 5 addresses per BCID) 1 – 2CAM Read (160 MHz clock) 2 – 3To Sector Logic 1 – 5*

Total 25 – 32

* Assumes that existing sector logic clocked @ 40 MHz

20

Summary/Work needed

• Readout and Trigger concept that seems feasible• MOST of the electronics processing is for the trigger• Concept reduces the 2M channels to ~30,000 – eliminates argument

that Mmegas will be much more expensive because of channel cnt.• One optical fiber per layer (GBTx assumed)

• Need development of one or two digital custom Ics• Probably can piggy-back on front end development• Need extensive electronics engineering effort (U. Az already on

board, Saclay is very much interested • Need extensive simulation work• Need demonstration prototype with existing CDF CAM or FPGAs asap

hopefully by October test beam?

21

Additional Slides

22

status / notes

Analog section completed

Peak/time detection in progress

Common circuitry in progress

Digital sections

Physical layout

Fabrication 1st prototype CMOS 130nm, 1.2V, MPW, by Summer 2011

Qmax = 330 fC

EN

C (

e-)

CIN [pF]

200ns

Charge Resolution

5k

20000

peaktime 25ns

50ns 100ns

1.2

time [ns]0

Am

plitu

de [

V]

0 150

Pulse Response

Qin = 300 fC

Analog section:transistor-level simulationspower ≈ 4 mW

VMM1 IC Schedule and Status

TTC Specs

# specification min typ max unit note

Number of outputs 8

Frequencies 40, 80 and 160 MHz individually programmable per output, set by control word Freq[1:0]

Phase resolution 50 ps Set by Delay[8:0]

DNL 20% LSB (50ps)

INL 30% LSB (50ps)

Jitter RMS 5 ps

Jitter P-P 30 ps

Temperature coefficient

5 ps/deg

Supply coefficient 50 ps/V

Logic levels Programmable: CMOS/LVDS

Synchronized with the 40Mhz main clock