simulation and fabrication of submicron channel length dmos transistors for analog applications

2222 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 40, NO. 12, DECEMBER 1993

Simulation and Fabrication of Submicron Channel Length DMOS Transistors for

Analog Applications Merit Y . Hong, Member, IEEE

Abstract-The purpose of this paper is to explore the use of an asymmetric MOS structure for superior analog circuit performance. Results from the fabrication of 1 pm gate length DMOS transistors show increases of up to 1.9 in transconductance, 10 in output resistance, and 8 in intrinsic gain when compared to NMOS of similar gate length and threshold voltage. Substrate current is also reduced by up to a factor of 10. This represents the first reported results of submicron channel length DMOS transistors.

The standard 7" implantation angle has significant impact on DMOS fabrication, and is shown to produce a usable asymmetric DMOS from an otherwise symmetric DMOS. An optimal implant energy and diffusion time is shown to exist for DMOS enhancement region formation.

Two-dimensional process and device simulators have proven necessary to develop the DMOS process, as well as to qualita- tively explain body effect reduction and threshold voltage determination.

The DMOS process has succesfully yielded experimental cri- cuits. These include a single ended operational amplifier of folded cascode topology, and a 101-state ring oscillator.

1. INTRODUCTION T is desirable in a mixed analog/digitial DMOS tech- I nology to provide transistors designed for optimum an-

alog and digital performance. Since transistors designed for optimum digital performance are not necessarily designed for optimum analog performance, process de- signers have oftentimes added a "third" device to a CMOS digital process for the purpose of obtaining higher analog performance.

As an alternative to using conventional NMOS or bi- polar structures for the "third" device, this paper will investigate the suitability of an asymmetrical MOS structure known as the double diffused MOS (DMOS) transistor [l], [2]. It will be shown that the DMOS transistor structure is capable of obtaining high intrinsic gain and high transconductance simultaneously.

A cross section of the DMOS structure considered here is shown in Fig. l(a). Only a few additional processing steps are required for the incorporation of DMOS transis-

Manuscript received April 29, 1991; revised January 18, 1993. This work was supported by the Semiconductor Research Corporation under Contract

The author was with Massachusetts Institute of Technology, Cambridge, MA 02139. He is now with Advanced Custom Technologies, Motorola, Mesa, AZ 85202.

89-SP-080.

IEEE Log Number 9212631.

L E 1 +LD4- I N metal

oxide xi

pvpe poly "diffused" region

(b) Fig. 1. DMOS cross section and model. (a) (top) Cross section of the DMOS structure utilized. (b) (bottom) E / D transistor model. For the devices considered here, the enhancement mode section has a positive threshold voltage and the depletion mode section has a negative threshold voltage.

tors into a conventional CMOS process. These include the addition of a channel (n-) implant, a source ( p ) implant, and a subsequent drive-in.

Frequent use will be made of DMOS analytical modeling results. It is important that the analytical model ac- curately predict the drain saturation voltage, since a meaningful comparison of NMOS and DMOS transistors from the analog perspective requires that the devices be biased in saturation. Although the details of the analytical model used are described elsewhere [3], the model is based upon the decomposition of the DMOS transistor into a short enhancement mode transistor in series with a longer depletion mode transistor [4]. Such an approach provides the basis for the enhancement/depletion (E/D) model. A schematic diagram of the model is shown in Fig. l(b).

11. DMOS SIMULATION

SUPRA and MINIMOS4 were used for process and device simulations respectively. Doping profiles obtained from SUPRA were used as input to MINIMOS4, a two

0018-9383/93$03.CN 0 1993 IEEE

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HONG: SIMULATION AND FABRICATION OF SUBMICRON CHANNEL LENGTH DMOS TRANSISTORS 2223

dimensional MOS transistor simulator. The mobility model originally used in MINIMOS4 [ 5 ] was modified to combine mobility models based separately on surface transverse electric field and bulk doping [6]. It has similar performance to the mobility model used in MINIMOSS.

A. Process Simulation It will be convenient to compare DMOS simulations of

a “standard,” 1 pm gate length design. The primary process parameters for this design are a channel implant of 10” cm-’ arsenic at 70 keV, a source implant of loL4 cm-* boron at 25 keV, and a source diffusion of 2 h at 950°C.

Contours of simulated net doping concentration in a “standard” DMOS are shown in Fig. 2(a). Approximate lengths of the enhancement and depletion mode sections are based on surface doping type, and are given by LE = 0.08 pm and LD = 0.67 pm.

Since the source and drain implants are self-aligned to the gate electrode, implant shadowing and penetration into the gate are possible whenever the implant beam is not perpendicular to the substrate surface. The shadowing effect has a significant impact on DMOS fabrication because it can significantly alter the doping near the source edge, a region vital to the operation of the DMOS. In the DMOS process, implants are made at an angle 7” off normal to minimize bulk channelling effects. With a gate electrode height of 0.5 pm, this can create an approximate 0.06 pm lateral displacement of the peak concentration away from the gate edge.

Since SUPRA does not support implantation at any angle other than normal, an effective mask for use with normal implants was used instead. This is shown in Fig. 3 . The resultant worst case scenario of implant shadowing at the source for a “standard” DMOS doping profile is represented (in reflected form) as the drain profile of Fig. 2(b), where the surface doping fails to convert from n to p . Similarly, implant shadowing can also be used to widen the enhancement region, as is shown in the source profile of Fig. 2(b).

Although implant shadowing adds process variability to the standard DMOS process, the effect can also be used to facilitate the fabrication of DMOS. Even at a 7” implant angle, the effects are substantial. Fig. 2(b) shows the effect of shadowing on an otherwise symmetric DMOS. Note that the symmetric DMOS is a DMOS whose source and drain regions both receive the enhancement mode implants.

Optimal combinations of implant energy and diffusion times exist for the source implant and subsequent drive- in. For the “standard” DMOS process, SUPRA predicts an optimal implant energy of 25 keV. Lower implant energies result in doping profiles too shallow to take advantage of lateral straggle in the implant profile. Higher- energies result in doping profiles too deep to affect surface concentrations. Utilizing a gaussian approximation for diffusion and implantation, the effect of implant energy and

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Standard DMOS Shadowed Symmetric DMOS Doping Profile Doping Profile

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0.0 0.2 0.4 0.6 0.8 1.0 0.0 0.2 0.4 0.6 0.8 1.0

Distance from Surface (pm) Distance from Surface (pm) (a) (b)

Fig. 2. Various DMOS net doping profiles. Both axes are drawn to pro- portion. The doping concentration contours vary from 10l6 to lo2’ cm-3 in powers of 10 for both p and n. (a) (left) DMOS (b) (right) Shadowing scenario for a symmetric DMOS. The source and drain doping profile each represent the DMOS sensitivity at the source to different implant angles. In the worst implant angle case, an asymmetric DMOS can have a source doping profile given by the drain doping profile of the pictured symmetric DMOS. In the best implant angle case, an asymmetric DMOS can have a source doping profile given by the source profile of the pictured symmetric DMOS.

+re \1 ions

shadow increased penetration

Fig. 3 . Off normal implantation. The solid line denotes the outline of the polysilicon structure that casts a shadow and allows increased lateral penetration. To approximate off normal implantation conditions, an implant mask denoted by the shaded area is used in SUPRA.

subsequent diffusion on the surface doping profile is shown in Fig. 4.

B. Device Simulation Results obtained from device simulation are shown in

Fig. 5(a), where the asymmetrical nature of the DMOS is evident from a comparison of ZD-VD curves for DMOS operating in both forward and backward configurations. Operation in the backward configuration degrades analog performance because of reduced breakdown voltage and output resistance.

Parametric curves of ZD versus V , for the “standard” DMOS transistor are shown in Fig. 5(b). Values for threshold voltage and mobility model parameters associ-

2224 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 40, NO. 12, DECEMBER 1993

Classical Simulation of ImplanVDiffusion Cycle DMOS gm (From Simulation)

C

i j

C z

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20 40 60 80

Implant Energy (keV)

Fig. 4. Effect of implant energy and diffusion on surface doping for a point located 0.2 pm from the source edge of the gate electrode. Diffusion effects are characterized by Dt’s which vary from 0.0 to 0.1 pm2 in steps of 0.01 pm2. Higher Dt’s result in a higher distribution curve. Doping concentration is the product of distribution function value and implant dose. Inter- section of the solid line with a Dt curve yields the implant energy which produces the maximum doping. Implant statistics from [7 ] .

v, 01) (a)

DMOS go (From Simulation) DMOS Gain (From Simulation)

DMOS ID-VD (From Simulation) DMOS ID-VG (From Simulation)

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10” 10.’ 104 in-9 _.” -.-

0.0 1.0 2.0 3.0 4.0 5.0 0.0 1.0 2.0 3.0 4.0 5.0’- v, (VI ’G (’)

(a) (b) Fig. 5 . DMOS characteristics. (a) (left) fD-VD. Operation in both forward and backward configurations are shown. V , stepped from 0 to 5 V in 1 V increments. V, and Vs are 0 V. (b) (right) ID-VG. V, stepped from 0 to -3 V in -1 V increments, V, is 0.1 V, and Vs is 0 V.

ated with the DMOS analytical model used here are obtained from a fitting of the VB = 0 V, V, = 0.1 V curve. The resultant parameter values are VTE = 0.75 V , VTD = -0.9 V , pEo = 380 cm2/V s , pDo = 600 cm2/V s, O E = 0.01 V s/cm2, and OD = 0.07 Vs/cm2.

From a device modeling standpoint, it is desirable that a minimal threshold voltage dependence on substrate bias be obtained for the depletion mode portion of the “standard” DMOS. For a 0 V source-substrate bias, the DMOS analytical model predicts that a “standard” DMOS will operate with no more than 1.5 V reverse bias on the source electrode of the depletion mode device (node Vx). Under these same substrate bias conditions, the measured threshold voltage shift of a depletion mode device whose channel consists of only the DMOS depletion mode doping never exceeded 0.1 V. The small substrate bias effect on the depletion mode threshold voltage can therefore be safely neglected in the modeling analysis of the “standard” DMOS process.

The DMOS output conductance contours are shown in Fig. 6(a). A convenient method for determining the over-

-.- 0.0 1.0 2.0 3.0 4.0 5.0 0.0 1.0 2.0 3.0 4.0 5.0

v, (v) VG (v)

(b) (c) Fig. 6. DMOS small signal characteristics. The solid curves denote the saturation point as calculated from the E / D model. (a) (top) DMOS conductance. The contour values from upper left to lower right in clockwise fashion are 1 x 2 x 5 x 1 x 2 X 5 X

and 1 X 10’ S/cm. (b) (bottom left) DMOS transconductance. The contour values from upper left to upper right are 0.2, 0.4, 0.6, 0.8, 1 .O, 1.2, 1.4, and 1.6 S/cm. (c) (right) DMOS intrinsic gain. Contour values from upper left to lower right are 500, 400, 300, 200, 100, and 1.

1 x io-*, 2 x IO-*, 5 x io-2, 1 x io-’, 2 x io-’, 5 x io-’,

all saturation curve is to find the curve which is closest to an upward turning curve, but does not turn upward itself. This is equivalent to using a critical conductance value to separate the saturation and nonsaturation regions. Also shown in Fig. 6(a) is the predicted drain saturation voltage from modeling. The shielding (or cascoding) effect of the depletion mode is evident from the large upward turn in output conductance along the drain saturation voltage border predicted for the depletion mode. The strong upward turns along the predicted depletion mode drain saturation curve at low gate bias show that depletion mode saturation is an important component contributing to the low DMOS output conductance.

Saturation at low drain biases is not as easily seen from the output conductance contours. However, it can be more easily seen from the transconductance contours shown in Fig. 6(b), where the saturation voltage occurs at the lower left corner of each contour. The predicted drain saturation voltage from modeling is also shown. Both the simulated and predicted saturation voltages closely match. A comparison of the DMOS transconductance for several drain voltages is shown in Fig. 7. The E / D model calculation matches the general form of the simulation transconductance curves fairly well. The smoother simulation curves result because the graded junction between enhancement and depletion sections is taken into account in the simulations, but not in the E /D model.


DMOS gm Comparison DMOSINMOS gm Ratios

0.0

- model - - - - simulation

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v, [v)

Fig. 7. Transconductance comparison between MINIMOS4 and E / D model. Parametric curves are shown for Vo of 1 , 2 , 3 , and 4 V.

Intrinsic gain derived from the transconductance and output conductance data is shown in Fig. 6(c). It shows that the optimal gain for DMOS occurs when both enhancement and depletion mode portions saturate.

Comparison of DMOS and NMOS transistors with similar threshold voltage illustrates the potential superiority of DMOS over NMOS in analog performance. Maximum improvement factors of 1.9 in g, , 2.6 in go , and 4 . 4 in gain are obtained for the “standard” DMOS. The distri- butions of improvement ratios as a function of operating voltages are shown in Fig. 8. The 0.05 V threshold voltage mismatch between DMOS and NMOS has a minimal impact on the positional accuracy of the ratio comparison.

Fig. 8(a) shows that the largest transconductance improvement occurs at low gate biases, where the enhancement mode is saturated. The location of peak improvement occurs at a bias just below the boundary between enhancement and depletion mode saturation. This is in- dicative of velocity saturation because of velocity saturation and series resistance both tend to move the location of peak improvement away from the border between enhancement and depletion mode saturation. This also has the effect of reducing the peak improvement value. Fig. 8(b) shows that the largest conductance reduction occurs at large drain biases, where the depletion mode is saturated. It is therefore not surprising that Fig. 8(c) shows that the largest gain improvement occurs at low gate and large drain bias, where both the enhancement and depletion mode sections are saturated.

Recall that the source and drain profiles of Fig. 2(b) each represent the sensitivity of the “standard” DMOS to different implant angles. Simulation results of the threshold voltage for an asymmetric DMOS with a worst and best case implant angle indicate a threshold voltage of -0.15 V and 2.15 V, respectively. This is to be compared with a “standard” DMOS threshold voltage of 0.75 V.

MINIMOS4 can also be used to examine electric fields throughout the device. Of major concern in short channel devices is the peak electric field near the drain, where

5.0

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(a) DMOSINMOS go Ratios DMOS/NMOS Gain Ratios

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3.0

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1 .o

0.0 ”.” _._ 0.0 1.0 2.0 3.0 4.0 5.0 0.0 1.0 2.0 3.0 4.0 5.0

Fig. 8. DMOS/NMOS comparison. The solid curves denote the saturation point as calculated from the E/D model. (a) (top) Transconductance comparison. (b) (bottom left) Conductance comparison. Note that a smaller R indicates better performance here. (c) (right) Gain comparison.

high lateral electric fields can cause increased substrate current and oxide charging. As shown in Fig. 9, the peak lateral electric field in the DMOS is slightly reduced when compared to an NMOS of comparable threshold voltage. For identical gate and drain bias, the DMOS exhibits a reduced peak lateral electric field as compared to an NMOS with the same threshold voltage. In addition, shifts in threshold voltage at the drain do not affect the overall DMOS threshold voltage provided that the shifts are kept below V,, - VTD. Such characteristics make the DMOS a desirable candidate for digital applications.

However, for a given drain voltage increment above the drain saturation voltage, the DMOS can have a greater peak electric field than an NMOS with comparable threshold voltage. The appropriate drain bias is given by VD - VD, in the DMOS, and VD - V,, in the NMOS. This is a typical bias condition in most analog applications. Shifts in threshold voltage at the drain also affects the bounda- ries of the DMOS analog operating region through VDsD. As a consequence, there may be no benefit in choosing a DMOS over an NMOS for analog applications because of reliability reasons alone.

On the source side of the DMOS, the lateral electric fields are significantly higher than in the NMOS. Since the voltage across the enhancement region saturates, this need not be a problem. It is an issue to be considered in device design, lest any hot electron effects get introduced into this critical area.

Carrier velocity for both DMOS and NMOS is shown in Fig. 10. The velocity shown represents an average over

2226 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 40. NO. 12, DECEMBER 1993

Surface Lateral Electric Field 0.5

- - - - NMOS with same V, and VDYDS,DSD

--- NMOS with Same I, and V,-V,,,,

-- NMOS wlth same VG and VD

1 - 5 0.4 5

0 z U a 0.3 C L .- P s 0.2

f 3 Oal

F w -

0.0 0.0 0.2 0.4 0.6 0.8 1.0

Distance from Source (pm) Fig. 9 . Comparison of DMOS and NMOS lateral electric field. The DMOS is biased at VG = 1.4 V and V, = 3 V for maximum gain. The NMOS is biased at V, = 1.4 V and V, = 1.66 V for constant gate voltage comparison, and VG = 1.77 V and V, = 1.91 V for constant drain current comparison. Where applicable, the excess drain voltage is V, - V,, = 1.0 V for the DMOS and V, - VDs = 1.0 V for the NMOS.

Distance from Source (p) Fig. 10. Comparison of camer velocity. Carrier velocity is averaged over the mobile charge cross section. The DMOS is biased at Vc = 1.4 V and V, = 3 V for maximum gain. The NMOS is biased at VG = 1.4 V and V, = 1.57 V for constant gate voltage comparison, and VG = 1.77 V and V, = 1.91 V for constant drain current comparison. Where applicable, the excess drain voltage is V, - VDsD = 1 .O V for the DMOS, and V, - VDs = 1.0 V for the NMOS.

the mobile charge cross section, and is calculated using the relationship U,,, = J JlUl dy/q J n dy, where Jlu, and n are obtained directly from MINIMOS4 and the y-direc- tion is transverse to the surface. Examination of the velocity curves shows that carriers in the DMOS have higher average velocity than in the NMOS. This is consistent with simple analytical modeling [3].

C. Substrate Effects It is generally accepted that the threshold voltage of the

DMOS is determined by the peak doping located adjacent to the source electrode [8] for transistors not suffering

DMOS Threshold Voltage

- - - - NMOS with channel doping taken 0.195 p from DMOS, source

I " " I " " I " " I " "

0.6 - -DDMOS

- 5 0.4 - 9 3 a

-... - 0.2 -

0.0 ' 0.0 1.0 2.0 3.0 4.0 5.0

Fig. 1 1 . DMOS threshold voltage determination. ID-VG curves are shown for an NMOS whose channel doping is a one dimensional slice taken 0.195 pm from the poly edge at the DMOS source. Also shown are the DMOS ID-VG characteristics. Substrate bias is stepped from 0 to -3 V in increments of 1 V. Drain bias is 0.1 V.

from short channel effects. A more accurate method is to use the doping adjacent to the source depletion edge un- derneath the gate electrode. The modified approach can account for the reduction in body effect evident in Fig. 5(b).

By neglecting the effect of the gate electrode on the source depletion region edge, a rough approximation to the actual source depletion edge can be obtained to illus- trate the body effect reduction. Consider the junction between source and channel of the "standard" DMOS process when V, = V,. It is appropriately modeled by a one- sided, abrupt junction located 0.125 pm from the poly edge. With an average channel doping of 3 X l O I 7 cm-3 on the enhancement side, the depletion region width of the junction is approximately 0.07 pm. Fig. 11 shows the result of a threshold voltage simulation obtained from the "standard" DMOS device and a conventional MOS whose channel doping is identical to that found at this depletion region edge (i.e., located 0.195 pm from the DMOS poly edge).

When a - 1 V substrate bias is applied, the source increases its depletion region and subsequently moves the threshold point further away from the source. Neglecting the gate electrode effectsd the lateral depletion region can expand more than 280 A . For a uniform NMOS whose channel doping is a one dimensional slice taken 0.195, 0.205, and 0.215 pm from the poly edge at the DMOS source, the extrapolated threshold voltage at -1 V substrate bias is 1.2, 1.05, and 0.8 V, respectively. These threshold voltages are to be compared with the 1.05 V obtainefl from the DMOS curves shown in Fig. 11. Only a 100 A shift is necessary to obtain the desired threshold voltage shift for a - 1 V substrate bias. Furthermore, the 100 A spacing is only one Debye length. These results support the notion that the reduction in body effect seen

HONG: SIMULATION AND FABRICATION OF SUBMICRON CHANNEL LENGTH DMOS TRANSISTORS

in the DMOS device is due to a shift in the threshold determining region towards areas with lower doping concentrations.

111. DMOS FABRICATION

The DMOS process was adapted from available 2 pm NMOS and CMOS analog processes. Two additional non- critical masking steps were required in each case. One mask was needed for the DMOS depletion mode implants, and another for the DMOS enhancement mode implants. If the DMOS depletion mode implants are used solely for channel implants, a conventional NMOS depletion mode transistor is obtained. The DMOS technology utilizes a gate oxide thickness of 144 A in order to prop- erly scale down to 1 pm polysilicon gate lengths. To test the DMOS process, experimental circuits were fabricated using a DMOS process.

A . NMOS Version

The NMOS process is based on a simple 4-mask process [9]. The added DMOS process steps consist of a DMOS channel mask and implantation, a DMOS source mask and implantation, and a DMOS source drive. For the “standard” DMOS, the added process parameters consist of a channel implant of 10l2 cmp2 arsenic at 70 keV, a source implant of l O I 4 cmp2 boron at 25 keV, and a 2 h source dopant drive at 950°C.

ZD-VD and ZD-VG characteristics for the standard DMOS device are shown in Fig. 12. Comparison of the forward and backward ZD-VD curves clearly demonstrate the asymmetrical nature of the device. The extrapolated threshold voltage from the ZD-VG characteristic is 1.05 V.

Enhancement and depletion NMOS were also fabricated on the same wafer. The enhancement NMOS was designed to have a similar threshold voltage as the DMOS. The depletion NMOS is a DMOS transistor without the source implant. Both of these devices can be used to determine approximate values for the mobility model parameters. An acceptable fit to the analytic model is obtained when VTE = 0.7 V, VTD = -0.7 V, p m = 480 cm2/V s, pDo = 580 cm2/V s, OE = 0.20 V s/cm2, and OD = 0.24 V s/cm2. The difference between NMOS and DMOS threshold voltage is 0.35 V. This is somewhat larger than the 0.05 V difference predicted by simulation results shown in Section 11.

Contours of DMOS transconductance, conductance and intrinsic gain are shown in Fig. 13, along with the saturation voltage curve predicted by modeling. Fig. 13(a) indicates an enhancement mode saturation voltage mismatch between modeling and measurement. One possible explanation is that L E , as obtained from simulations, differs somewhat from the actual L E . Another possible explanation is that series resistance reduces the transconductance before its maximum is reached. Otherwise, the conductance and intrinsic gain of the DMOS exhibit similar behavior to that obtained from simulation. The on-

2227

DMOS ID-VD (From Measurement) DMOS ID-VG (From Measurement)

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(a) (b) Fig. 12. DMOS characteristics. Drawn transistor dimensions are L = 1.2 pm and W = 50 pm. Actual poly gate length is closer to I p n . (a) (left) DMOS tD-VD for operation in both forward and backward configurations. V, stepped from 0 to 4.5 V in 0.5 V increments. V, and VB are 0 V . (b) (right) DMOS forward ID-Vc;. VB stepped from 0 to - 3 V in -1 V increments. Vo is 0.1 V, and Vs is 0 V.

DMOS go (From Measurement)

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(b) (c) Fig. 13. DMOS small signal characteristics. (a) (top) DMOS transconductance. Contour values from bottom to top are 0.2, 0.4, 0.6, 0.8, 1.0, and 1.2 S/cm. (b) (bottom left) DMOS output conductance. Contour values along lower horizontal axis from left to right are 1 X 2 X IO-‘,

IO-*, I X I O - ’ , 2 X I O - ’ , 5 X I O - ’ , and 1 x 10°S/cm. (c) (right) DMOS intrinsic gain. Contour values from inside to outside are 250, 200. 150, 100, 50, and 1.

5 x 10-4, I x 10-3, 2 x 10-3, 5 x 10 3 , 1 x 1 0 - 2 , 2 x 1 0 - 2 , 5 x

set of soft breakdown, as obtained from measurements, is approximately 2 V above the saturation voltage.

A comparison of DMOS and NMOS transconductance, output conductance, and intrinsic gain is shown in Fig. 14. Unlike the comparisons shown in Section 11, these comparisons are plotted as functions of excess drain voltage (the amount of drain voltage exceeding the drain saturation voltage) and drain current. The choice of excess


DMOSlNMOS gm (From Measurement) DMOS Ig (From Measurement)

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I , /W ( A i c m )

(b) (C) Fig. 14. DMOS/NMOS comparison. Since the comparison is made with data taken in the range 0 5 V, < 5 and 0 < VD 5 5 V, results for certain regions are absent. The regions of absent data are shaded. Drain saturation voltages are obtained from the E / D model. The gate bias where V, = V,, in the DMOS corresponds to ID/W = lo-'.' = 1.6 x IO-' A/cm. (a) (top) Transconductance comparison. (b) (bottom left) Conductance comparison. Note that a smaller contour value indicates better performance here. (c) (right) Gain comparison.

drain voltage is necessary because both devices exhibit signs of breakdown within the 5 V operating range. The choice of drain current is used primarily because it cor- rects for the 0.35 V mismatch in threshold voltage. It is also a more appropriate parameter for analog circuit design. The figures show improvements of up to l .9 in transconductance, 10 in output conductance, and 6 in gain. The maximum improvements do not all occur under the same bias conditions. Although the maximum improvement in transconductance is consistent with simulation, the substantially larger maximum improvements in output conductance, and hence gain, is attributable to the earlier occurence of breakdown in the NMOS. The figures also indicate that the DMOS offers best performance enhancement in the range lop2 < ZD/W < 4 X lo-' A/cm, 1.5 < VD - VDsD. Maximum improvement in gain and transconductance are simulataneously obtained in this range. As will be shown, this regime also offers reduced substrate currents.

Measured substrate current is shown in Fig. 15 for DMOS and NMOS. For a given gate and drain bias, the DMOS has reduced substrate current. for a given excess drain voltage over saturation (V, - VDsD in the DMOS and VD - VDs in the NMOS), the DMOS has a slightly increased substrate current. This is consistent with simulation results which indicate a higher peak electric field in the DMOS given a constant excess drain voltage. How-

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NMOS I, (From Measurement) DMOSlNMOS 1, (From M e a s w " t ) (a)

1 0 . ~ i o 4 io-2 10-1 loo io1

VG o / ) I , /W ( A i c m )

(b) (C) Fig 15 DMOS and NMOS substrate currents (a) (top) DMOS forward Is-VG Contour values increase from low VG to high VG, and are given by - - 10 ', - - 10 ', - 10 A/cm, respectively (b) (bottom left) NMOS Is-VG Contour values increase from low VG to high V,, and are given by - 10 ', - 10 ', - 10 ', - (c) (nght) DMOS/NMOS substrate current companson Contours are shown for ratios of 1 0, 0 5 , 0 2, 0 1, and 0 05 The unlabeled contour7 which lie in the region bounded by I D / W < 5 X 10 ' A/cm and VI, < 1 4 V all have the value 1 0 See Fig 14 for additional details regarding this style of comparison Note that the lower contour value indicates better performance, just as in the output conductance case

- 10 A/cm, respectively

ever, a comparison of substrate currents in Fig. 14(c) using the same method as for the other analog parameters shows that the DMOS is no worse than a comparable NMOS. For higher excess voltages, the DMOS is superior. On the basis of the substrate current comparison, the DMOS is clearly a superior device for digital applications. For analog applications, the DMOS is not any worse than the comparable NMOS. It is a superior analog device at high excess drain voltages.

B. CMOS Version The CMOS process utilizes a twin well technology that

contains 10 masking steps [lo]. The substrate is a lightly doped p/p' epitaxial wafer. As in the NMOS process, two additional masking steps are required, with the DMOS residing in the p-well. The same DMOS parameters that were used in the NMOS process are also used here. DMOS characteristics are similar to that obtained in the NMOS version. PMOS ZD-VD curves are shown in Fig. 16. The extrapolated PMOS threshold voltage is -0.8 V.

An experimental ring oscillator with 101 inverter stages was fabricated. The W / L ratio of the DMOS and PMOS transistors is 3 /2 and 6/2, respectively. The power-delay product curve is shown in Fig. 17, and was calculated by


0.6

0.5

0.4

-1.5

-1.0

E . 9 3 n . -

-0.5

n.n

-

-

-

PMOS lD-VD (From Measurements)

0.0 -1.0 -2.0 -3.0 -4.0 -5.0

v, (VI Fig. 16. PMOS ID-VD. VG stepped from 0 to -5 V in -0.5 V increments.

Drawn transistor dimensions are L = 2 pm, and W = 50 pm.

Power-Delay Curve

Supply Voltage (V)

; - - - - Supply Voltage

Power -

t l ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ i 0.0 2.0 4.0 6.0 8.0

Power (mw)

Fig. 17. Power-delay product curve. The average gate delay is also shown as a function of the supply voltage.

taking the product of total power and propagation delay for one complete period, and then averaging over the total number of state transistions that occur during that period. Both a low-high and high-low transition constitute separate state transitions.

Also fabricated on the same chip was an experimental single-ended operational amplifier. The opamp is of a folded cascode topology that is often implemented with cascoded NMOS transistors to improve gain, but with the improved output resistance of the DMOS, the cascoded NMOS was replaced with a single DMOS to improve output swing. The circuit also utilizes an improved output

I Drawn W/L Ratios (pm) I

Fig. 18. DMOS/PMOS opamp schematic.

swing bias scheme [ l l ] . A schematic of the opamp is shown in Fig. 18.

The differential mode voltage gain of the folded cascode topology is given by

(1) where R, and RI are the current source output resistance (transistors M25 and M26, and M14 and M15 respectively), g,, and r,,, and g , and r,,, are the transconductance and output resistance of the DMOS (transistors M16 and M17) and PMOS (transistors M23 and M24) devices, respectively, and

is the effective resistance looking into the source of the PMOS cascode (transistors M23 and M24) [ 111. Accord- ing to ( I ) , differential gain is maximized when the output resistance of the load current source is much greater than the output resistance of the cascode (R, >> r,,,), and the output resistance of the PMOS current source is much greater than the output resistance of the input device (R,

The maximum gain measured from the opamp was 400. For a power consumption of 24 mW and a load capaci- tance of 12 pF, the slew rate was 60 V/ps and the unity gain frequency was 20 MHz. The bias was ibiasI = -0.21 mA, ibiad = 2.97 mA, and ubiasl = 0 V, and the power supply voltages were V,, = 3.34 V and V,, = - 1.74 V.

>> r,,).


Symmetric DMOS ln-VD with Slight Asymmetry (Measured)

4.0

- 3.0 6 5 2.0 L -! 1.0

.

.

0.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0

‘G (’)

(a)

Symmetric DMOS l,,-Vn with Significant Asymmetry (Measured)

4.0

- 3.0 6 5 2.0 3 -! 1.0

.

.

0.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0

‘G 01) (bi

Fig. 19. Effect of angled implants on symmetric DMOS characteristics. Curves are shown for both forward and backward operation. Vc is stepped from 0 to 5 V in 0.5 V increments. (a) (left) Symmetric DMOS ID-VD exhibiting slight asymmetry. An effort is made to present identical shadowing conditions for the DMOS source and sourceidrain implants. Since the ion implanter used does not have an alignment stage, some slight asymmetry is unavoidable. (b) (right) Symmetric DMOS I,,-VD exhibiting significant asymmetry. An effort is made to exploit shadowing opportunities with the DMOS source and source/drain implants.

Under ideal conditions (Ton >> R,, and R, >> i?,,), the entire g, of input transistors M 16 and M 17 can be applied to the output node. The open circuit gain of the opamp is then g,,RI. Under nonideal conditions, g,,R, is the lower bound on DMOS intrinsic gain. Since transistors M16 and M17 are wider than transistors M14 and M15 by a factor of 2.5, the lower bound on DMOS gain is 160. Since Figs. 16 and 12(a) indicate the likelihood that R, < r,,, further improvement in opamp gain can be achieved with a cascoded PMOS current source.

The ZD-VD characteristic of a symmetric DMOS is shown in Fig. 19(a) for the standard DMOS process conditions. Utilizing 7” implant shadowing to full advantage, significant asymmetry is achieved. Fig. 19(b) shows the resulting symmetric DMOS I,- V , characteristics. The extrapolated threshold voltage for the DMOS without shadowing and the DMOS with shadowing is 1.1 V and 2 . 1 V, respectively. There is good consistency between these values and the corresponding simulation results of 0.75 V and 2.15 V, respectively.

IV. CONCLUSION The DMOS is an asymmetric MOS structure which

achieves the desired objective of higher gain with higher transconductance. The improved performance over conventional MOS structures is achieved without an increase in substrate current, and is readily incorporated into existing MOS processes. Short gate length DMOS transistors have been successfully fabricated within the frame- work of an existing analog NMOS and CMOS process. Only modest adjustments to the process flow were required. Superior analog performance with regard to transconductance, body effect, and intrinsic gain have been demonstrated by the DMOS transistors.

The best performance enhancement occurs in the range bounded by lo-’ < Z,/W < 4 X lo-’ A/cm, 1.5 < V, - ifDsD. Maximum-improvement in gain and transconductance are simultaneously achieved, with improve-

ments of up to a factor of 1.9 in transconductance and a factor of 5 in intrinsic gain obtained. Biasing in this range also yields an improvement in substrate current. Improve- ments in substrate current increase with increasing drain voltage. A drawback of the DMOS is that a higher abso- lute drain voltage is necessary for this performance enhancement.

Experimental circuits were fabricated, yielding func- tional opamps and ring oscillators. Asymmetric DMOS devices have also been fabricated from otherwise symmetric DMOS structures by choosing specific wafer ori- entations for the implantation process. Superior DMOS performance is obtained from this method.

A 2-D device simulator is used to obtain electrical in- formation based on 2-D profiles produced by the process simulator. The results are used to determine body effect, transconductance, and output resistance. A qualitative explanation of threshold voltage determination and body effect reduction is obtained from simulation results. Im- provement factors obtained from simulation agree well with those from measurement.

ACKNOWLEDGMENT The author would like to thank Prof. D. Antoniadis for

his technical advice, J . Jacobs for his assistance with MINIMOS4, G. Carlin for his help with opamp measurements, and Prof. H.-S. Lee for his advice of an opamp design. Suggestions provided by the reviewers were also appreciated. Device measurements were obtained from equipment donated by the Hewlett-Packard Corporation.

REFERENCES

[ I ] Y . Tarui, Y. Hayashi, and T. Sekigawa. “Diffusion self-aligned MOST: A new approach for high speed device,” in Proc. 1st Con$ on Solid State Devices, Tokyo, Japan, 1969; also Supplement to J. Japan Soc. Appl. Phys., vol. 39, pp. 105-110, 1970.

[2] Y . Tarui, Y . Hayashi, T. Sekigawa, and Y. Komiya, “Diffusion self- aligned MOST and lateral transistor,” in Proc. 4 fh Microelecfron. Congr., Munich, W. Germany, 1970, pp. 102-128.

[3] M. Y . Hung, “Double diffused (DMOS) FET’s for analog applications,” Ph.D. dissertation, Mass. Inst. Technol., 1990.

[4] H. Masuda, T. Masuhara, M. Nagata, and N. Hashimoto, “Device design of E / D Gate MOSFET,” in Proc. 4th Con$ on Solid State Devices, Tokyo, Japan, 1972; also Supplement to J . Japan Soc. Appl. Phys., vol. 42, pp. 167-172, 1973.

[5] S . Selberherr, Anulysis and Simulafion of Semiconductor Devices. New York: Springer-Verlag, 1984.

[6] J. B. Jacobs, “Modeling the effects of Si/SiOz interface proximity and transverse field on carrier mobility in MOSFETs,” MIT VLSI Memo No. 87-395, July 1987.

[7] J . E. Gibbons, W. S . Johnson, S . W. Mylroie, Projected Range Sta- tistics, 2nd ed., Stroudsburg, Dowden, Hutchinson, & Ross, 1975.

[8] M. D. Pocha, A. G . Gonzalez, and R. W. Dutton, “Threshold voltage controllability in double-diffused-MOS transistors, ’’ IEEE Trans. Electron Devices, vol. ED-21, pp. 778-784, 1974.

[9] S. L. Garverick, private communication. [lo] P. K. Tedrow, C. G . Sodini, Twin Well CMOS Process, Version 1.2.

Cambridge, MA: Mass. Instit. Technol., 1989. [ l l ] T. C. Choi, R. T. Kaneshiro, R . W. Brodersen, P. R. Gray, W. B.

Jett, and M. Wilcox, “High-frequency CMOS switched-capacitor fil- ters for communications application,” IEEE J . Solid-state Circuits, vol. SC-18, pp. 652-664, 1983.

Merit Y. Hong, photograph and biography not available at the time of publication.

simulation and fabrication of submicron channel length dmos transistors for analog applications

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