session 4 packaging techniques

SESSION 4

PACKAGING TECHNIQUES

Sponsored by: National Science Foundation D4.1

Power Cycling Tests for Passive Integrated Power Electronics Modules

Seung-Yo Lee, Ning Zhu, W.G. Odendaal and J.D. van Wyk20032003

q Power Cycling Tests for Passive Integrated ModulesØTemperature Chamber( Ambient Temperature:-2 °C )

Integrated ModuleIntegrated Module

Vc

Vds

iLC

ØCircuit Diagram for Power Cycling ØWaveforms in Power Cycling Circuit (for 2-Turn Module)

Current of the LC Module (5A/div): iLC

Drain-Source Voltage of the Top Switch (20V/div): VdsApplied Capacitor

Voltage (25V/div): Vc

Ø Power CycleØ Temperature Profile (for 2-Turn Module) Ø Temperature Profile (for 3-Turn Module)

Crack in Ceramic

Ceramic substrate

Copper

Epoxy

Delamination at the Interface between Copper and CeramicLayers Crack in Ceramic

Spring to hold the module

Temp(°C)

About 92°C

Heating Cooling

About 2 °C

Heating

Time(sec)48sec 48sec

q Power Cycling Tests ResultsØ Optical Microscopic Images after Power Cycling

for 2-Turn Module

ØElectrical Characteristics of The Integrated Modules before and after Power Cycling§ 2-Turn Module

q Passive Integrated Modules Used in Power Cycling Testsq ObjectiveØInvestigate Failure Mechanismof the Passive IPEMsØHelp to Estimate Lifetime of the

Passive IPEMs

• 2-Turn Module •3-Turn Module

- Relative Dielectric Constant of Ceramic Substrate: 1720~2690

q ConclusionØ Cracks and Delaminations Were

Found after Power Cycling TestsØ Capacitances Were Changed within

10,000 Cycles with about 90°C~97°CTemp. Variation and 96sec Power Cycle

• Electrical Characteristics of LC Modules

§ 3-Turn Module

cpes virginia tech

80

A Comparison of Lifetime and Thermal Performance of Lead-free Solder Alloys for Bonding Power Devices in Flux

and Flux-less Reflow Processes

Sponsored by: NSF

D. Huff, D. Katsis, J.D. van Wyk, G-Q Lu

D4.2

20032003

Vacuum-reflowedPower Devices

Resulting Scanning Acoustic Micrograph of Solder Junction

Vacuum Reflow Furnace

Graphite Fixture

0 cycles

2000x

0 cycles

6000x

60 cycles

2000x60 cycles

6000x

0 cycles

2000x

0 cycles

6000x

60 cycles

2000x60 cycles

6000x

Progression of void growth, 0 to 500 temperature cycles

Coarsening of solder grain structure

New Device 1000 2000 3000 4000

5000 6000 7000 10000

Void Growth

10

20

30

40

50

0 2000 4000 6000 8000 10000Power Cycles

Void

%

Typical Large AreaSolder Application

Materials

•Substrate

•Solder

•Plating

Processing

•Equipment and Tooling

•Atmosphere

•Process Profile

Accelerated Life Testing

•Temperature Cycling

•Power Cycling

Project Scope: Die Attach of Silicon Power Devices

Flux-less Vacuum Solder ReflowUsing Lead-free Solder

Reliability Analysis

Analysis Tools

•Scanning Acoustic Microscopy (SAM)

•Scanning Electron Microscopy (SEM)

•Thermal Performance Measurement

•Modeling

MOSFETS

Chamber Shelf

MOSFETS

Chamber Shelf

-60

-40

-20

0

20

40

60

80

100

0 2 4 6 8 10time-minutes

tem

pera

ture

-C

Actual Profile Temp

Die Attach Process

Direct Bond Copper (DBC) Substrate with Au/Ni Plating

Temperature/Power Cycling Void Growth

SAM Analysis SEM Analysis

For details on Thermal Performance Measurementand Modeling please see poster #R52 in room 633C !

Reflow Equipment and Tooling Process Profile

Solder

Solder Types

•Sn100

•Sn95.5Ag4Cu0.5

•Sn95Sb5

•Sn96.5Ag3.5

•Sn97Cu2Sb0.8Ag0.2

•Sn63Pb37

•SnBi

Courtesy of Kelly Stinson-Bagby

Coining of America, LLCKester, Inc.

•<50 mtorr Vacuum

•Ar95H25 Forming Gas

•N295H25 Forming Gas

•N2 Gas

Atmosphere

Substrate and Plating

cpes virginia tech

81

Calorimeter for Accurate Measurement of Power Losses in IPEMs

Sponsored by: NSF

Chucheng Xiao, Gang Chen, W.G. Odendaal

D4.3

20032003

Motivation: Power loss measurement in active IPEMs, passive IPEMs and integrated magnetics.

Heat Sink

DUT

RP2

TC

I2Rm/2

I2Rm/2

αΙTC

αΙTH

TH

1/Km

RP1

Rhs

Rfs

To

Rio

Roa

Tin

Ta Ta

RP2

TC

I2Rm/2

I2Rm/2

αΙTC

αΙTH

TH

1/Km

RP1

Rhs

Rfs

To

Rio

Roa

Tin

Ta Ta

TE Modules

Base Plate II

Heat Flux Sensor

Two covers

Leads

Base Plate I

Schematic of proposed calorimeter Heat transfer model

Temperature Controller for two covers(limits heat leakage)

TE modules as cooler to direct heat(controls temperature on DUT)

Heater

+15

Inner cover

Outer cover

AD595

AD595

DifferentialAmplifier

CMP

+15

-15+15

Driver

+15

-15

vPolished double covers

vInsulator: fiberglass

vAir-tight test chamber: feedthroughs, spring-loaded connectors, gasket, adjustable draw latches

Features:Ø Direct measurement of heat flux

Ø Error < 5%

Ø Control an arbitrary temperature on DUT

Ø Easy to setup

TEModules

Base Plate II AD595

AmplifierCMP

+15

-15+15

Driver

+15

-15

Vref

DUT

Outer coverOuter cover

Inner coverInner cover

InsulationInsulation

Base plateBase plate

Heat flux sensor

Heat flux sensor

Thermoelectric Modules

Thermoelectric Modules

Base coverBase cover

TemperatureControlCircuits

Power Supply

Power Supply

HeaterHeater

VDS

VGS

Control signals of TE moduleControl signals of TE moduleOutput of heat flux sensor for 4.26 W power

loss measurementOutput of heat flux sensor for 4.26 W power

loss measurement

cpes virginia tech

82

20

30

40

50

60

70

80

90

100

0 10 20 30 40 50time-ms

tem

p-C

0 15% 40%55% 15% Avg 40% Avg55% Avg

A Finite Element Modeling of Dynamic Hot Spot Effects in MOSFET Dies

Sponsored by: National Science Foundation

D. C. Katsis and J.D. vanWyk

D4.4

20032003

=CapacitanceJ/ ºC=Resistanceθ, ºC/W=AmpsW=VoltsºC

RC Circuit Thermal Models

58ºC

55ºC

51ºC

48ºC

55% Voided Area

40% Voided Area

15% Voided Area

0% Voided Area

C, 10k cycles

A, 0 cycles

B, 7k cycles

15% Die-Attach Area Voided



SimulatedActual

FEA Simulation Development FEA Results vs. Experimental Observation

5ms 10ms 15ms 20ms

30ms 35ms 40ms

45ms 50ms

25ms

FEA Heating Simulation

21ms

30ms

22ms20ms

25ms23ms

FEA Cooling Simulation

RC Circuit Response With Encapsulation

Voids

CrossSection

cpes virginia tech

83

Investigation of Gate-driver Selection based on Operating Conditions

Sponsored by: National Science Foundation / Raytheon

J.T. Strydom, J.D. van Wyk

D4.5

20032003

Bus

vol

tage

(V)

Gate capacitance

RV

VS

Nor

mal

ized

vol

tage

RN=1

RN=2RN=4

RN=10

1

0

0.2

0.4

0.6

0.8

RN=8RN=6

200 2 4 6 8 10 12 14 16 18

RN=1

RN=2

RN=4RN=6

200 2 4 6 8 10 12 14 16 18

1

0

0.2

0.4

0.6

0.8

Nor

mal

ized

cur

rent

Nor

mal

ized

cur

rent

IN=1

IN=1/2

IN=1/4IN=1/6

100 1 2 3 4 5 6 7 8 9

1

0

0.2

0.4

0.6

0.8

IN=1/8IN=0.1

Nor

mal

ized

vol

tage IN=1

IN=1/2IN=1/4

IN=0.1

100 1 2 3 4 5 6 7 8 9

1

0

0.2

0.4

0.6

0.8

IN=1/8IN=1/6

Gate capacitance

RC

RFIS

Gate capacitance

RRLR

RP Clamped resonance

0.6

0.4

0.2

00 2ππ 3π

0.8

Nor

mal

ized

Indu

ctor

Cur

rent

Q=5

Q=2.5

Q=0.5

Q=0.625

Q=1

Clamped resonance- Vs =Vg

1.5

1

0.5

00 2ππN

orm

aliz

ed C

apac

itor

Vol

tage Full resonance

Clamped resonance- Vs =Vg

Q=5Q=2.5

Q=0.5

Q=0.625

Q=1

0.8

RV (3), RR (15)

IS (6)

RF (9)

RR, Q=5

0.01

0.1

1

100

Z0 (14)

50 0.5 1 1.5 2 2.5 3 3.5 4 4.5

10

RRHQ (18)

Rgate=1Ω

Res

ista

nce

(Ω),

Cur

rent

(A

) Maximum clamped resonance frequencyMaximum full resonance frequency ~ Q = 5

Maximum frequency: Voltage source driver

Increasing Q

Maximum freewheeling resistance: Pc-

baseline=PV

Decreasing max. freq.Full resonance Q=5

Current driven: RF = 0

0.01

0.1

1

Full resonance Q=1/2

50 0.5 1 1.5 2 2.5 3 3.5 4 4.5

10Current driven: RF = 0.1RV

Increasing Q

Voltage driven

Increasing freewheeling losses current driven

Pow

er d

issip

ation

(W)

Max. crossover point for losses between voltage and current driven topologies

20mm

Semiconductor area

Passives area

Semiconductor area

Passives area

Semiconductor area

Passives area

Gate-driver Investigation Most neglected part of converter

design Influences converter performance Most pronounced at:

High frequency High voltage Low power

Different topologies possible Comparative study to evaluate

gate-driver topologies

3π

Opto-isolation

Galvanically isolated supply

Opto-isolation

SiC BootstrapSupply

LV level shift and Si Bootstrap supply

HV level shiftBootstrap supply

0.5 1 2 3 4 5Switching frequency (MHz)

200

0

400

600

800

1000

1200

1400

Representative voltage and frequency ranges of different commercial gate-driver systems

Representative gate voltage for base-line requirement of all gate-driver topologies

Simplified charge-interval circuit for the Voltage Source gate-driver topology

Simplified charge-interval circuit for the Current Source gate-driver topology

Normalized time

Normalized time

Normalized time

Normalized time Normalized time

Normalized time

Simplified charge-interval circuit for the Resonant gate-driver topology

Charge time ≤ 5% of period

Switching periodDuty cycle variation

Shape dependent on gate-driver ∆t

0.8VS

VS

Current and Voltage waveforms for different Q-values for the resonant topology

Current and Voltage waveforms for different current source values

Current and Voltage waveforms for different series resistance values

Frequency (MHz)Frequency (MHz)

Gate-driver comparison resultsUnder the presented assumptions: Below cross over point: Current

source has lowest losses Above cross-over: Current

source - highest losses, but only solution for required rise time

Resonant lowest losses, but most frequency limited

Maximum allowable resistances for the three gate-driver topologies as function of frequency

Maximum allowable resistances for the three gate-driver topologies as function of frequency

Same topology Same technology

Voltage driven - 200kHz, hybrid Voltage driven – 1MHz, SMT Current driven – 1MHz, SMT

cpes virginia tech

84

Processing and Reliability Study of Pressure-assisted Low-Temperature

Sintered Die-attach


Zach Zhang and Dr. Guo-Quan Lu

D4.6

20032003

Conclusion:

Increasing the temperature and pressure improved the electrical and thermal conductivity, and the shear strength.

Increasing the time beyond two minutes did not change the properties significantly.

I Processing parameters investigation

Thermal cycling

0 . 0 0 E + 0 0

5 . 0 0 E + 0 4

1 . 0 0 E + 0 5

1 . 5 0 E + 0 5

2 . 0 0 E + 0 5

2 . 5 0 E + 0 5

3 . 0 0 E + 0 5

3 . 5 0 E + 0 5

4 . 0 0 E + 0 5

4 . 5 0 E + 0 5

5 . 0 0 E + 0 5

1 7 0 O C 2 4 0 O C 3 0 0 O C 1 0 M P a 2 0 M P a 4 0 M P a 2 M in 5 M in 1 0 M in

s int e re d a t 4 0 M P a, 5 M ins int e re d a t 2 4 0 o C , 5 mins int e re d a t 4 0 M P a, 2 4 0 o C

0

2 0

4 0

6 0

8 0

1 0 0

1 2 0

1 4 0

170OC 240OC 300OC 10MP a 20MP a 40MPa 2Min 5Min 10Min

s int e re d a t 4 0 M P a, 5 M ins int e re d a t 2 4 0 o C , 5M ins int e re d a t 2 4 0 o C , 4 0 M P a

c

0

1 0

2 0

3 0

4 0

5 0

6 0

7 0

1 7 0 O C 2 4 0 O C 3 0 0 O C 1 0 M P a 2 0 M P a 4 0 M P a 2 M i n 5 M i n 1 0 M i n

s i n t e re d a t 4 0 MP a , 5 Mi ns i n t e re d a t 2 4 0 o C , 5 Mi ns i n t e re d a t 4 0 MP a , 2 4 0 o C

II Reliability investigation

Before cycling

Solder (Sn63Pb37) Reflow Die-attach layer

SAM

300 cycles

Silver sintering(240oC, 40MPa, 5Min)

Die-attach layerSAM

Appearance of New Voids

Growth of Void Area

Edge Cracking

Destructive adhesion test accomplished by chiseling the chip from the substrate

Conclusion:

The sintered silver die-attach layer is highly resistant to void-induced failure.

Inhomogeneous pores distribution, binder residue may cause local concentrations of stress during the cycling load because of CTE mismatch. These stress concentrations usually initiate and propagate cracks these sintered silver die-attach layer.

Initial voids

Silver sintering(240oC, 40MPa, 5Min)

Die-attach layerSEM

Largepores

Small pores

Largermagnification

Shea

r Stre

ngth

(MPa

)

Effect of Processing Parameters on Shear Strength

Processing Parameters

Effect of Processing Parameters on Thermal conductivity

Ther

mal

con

duct

ivity

(W/m

-K)


Effect of Processing Parameters on Electrical Conductivity

Elec

trica

l Con

duct

ivity

((Ohm

*cm

)-1)


cpes virginia tech

85

Planar Litz - A method to reduce high frequency conduction losses in integrated

components

Sponsored by: CPES

M.A. de Rooij, J.T. Strydom, J.D. van Wyk

D4.7

20032003

Position

Wide planar conductor with flux lines (for a current into or out of the page)

Current density along the center line in the conductor I[A]

Substrate Lower l ayer of planar litz conductor

Upper layer of planar litz conductor

Layer inter -connects

Planar litz conductor direction

Planar litz lines

Inner layer strands

Outer layer strands

Strand angle

Vias wPLC

Inner layer Outer layer

1 1

1

2

1

3

3

4 4

5

5

litz blocks

27 strands 20mils x 20mils



Inner layer and core Outer layer and core Assembled planar litz conductor and core

12345 A

B

CR LR

LM

4 : 2

A

B

D

100V 24V

L-L-C-T module

IP

Outer layer

Via layer

Inner layer

Top layer Bottom layer

Outer layer

Via layer

Inner layer

Terminal blocks used to accommodate narrowing of the planar litz conductor

44 mm

91mm

12mm

Primary Winding

Secondary Winding

Alignment holes Vias

Copper sputtered onto substrate, and electroplated

Step 1: Cutting substrate Step 2: Application of copper to substrate

Step 3: Etching of inner layer Step 4: Masking of inner layer

Step 5: Applicat ion of copper for outer layer

Step 6: Etching of outer layer

Step 7: Masking of outer layer Step 8: Final cutting

Current density distribution and magnetic flux lines in an isolated wide planar conductor

( )maxmax20 torofWcond δ⋅>Definition of a wide planar conductor

where Wcond = Width of the planar conductor [m]d = Skin depth of the conductor [m]tmax = Maximum thickness of the conductor [m]

Definition for a planar litz conductor

Strand/s: Narrow conductor/s used to make up a planarlitz conductor.

Planar litz Conductor: A planar conductor comprised of many isolated strands that are weaved together to form a single high frequency, higher current carrying capacity conductor.

Planar litz conductor guidelines1. Any improvement over a single planar conductor is an improvement.

2. An extra layer is required. The additional thickness is small . Multi-layer structures are also possible by zigzagging additional layers as shown in the figure.

3. Minimum number of litz strands is 3.

4. The higher the number of strands the more efficient the effect.

5. All the litz strands must be of equal length and width so that the impedances of each strand will be the same.

6. The litz strand may zig-zag within the winding window as many times as is possible.

7. An optimal strand angle is 45º.

8. The width of the planar litz conductor will be greater than or equal to half the width of a single conductor.

9. Inter-connects are used to connect the layers of the planarlitz conductor together on the outer edges of the planar litz conductor only.

Simplified top views of the planar litz conductor building blocks

Converter Parameter Value Units Maximum Input voltage (Vi n) 200 V Maximum Output voltage (V o) 48 V Maximum Output power (Po) 500 W Resonant frequency (fo) 1.1 MHz Resonant capacitance (CR) 50 nF Resonant inductance (L R) 400 nH Magnetizing inductance (L M) 20 µH Primary winding (NP) 4 turns Secondary winding (N S1) = (NS2) 1 turn

Steps followed to construct a planar litzconductor for experimental

1. A corner block.

2. A square block. The following equation describes the line position change of a strand where a strands starts in line x and ends in line y and where:

3. A rectangle block.

4. A termination block.

5. A termination compensation block.

x nlines≤y n xlines= + −( )1

Different #2 blocks sizes for the same and different strand and spacing widths

Top views of the assembled planar litzconductor with a planar E-core

EXPERIMENTAL VERIFICATION OF THE PLANAR LITZ CONDUCTOR

Power circuit used to test the planar litzconcept

Experimental converter specifications

Primary side litz conductor patterns

Secondary side litz conductor pattern

Photo of an experimental winding made using planar litz for an integrated passive component

EXPERIMENTAL

Using a half grid to eliminate the gap in the corner blockWide planar conductors utilize the

conductor area poorly and a new method is sought to capitalize on the benefits of

litz wire for planar conductors

THE PLANAR LITZ CONDUCTOR

Wide planar conductors are widely used in many integrated power electronic

passive components and are usually made to be skin depth thick at the

designed operating frequency

cpes virginia tech

86

An Overview of Electromagnetic Modeling of Resonant Integrated Spiral Planar Power

Passives (ISP3)


J.T. Strydom, J.D. van Wyk

D4.8

20032003

LM

LR1CR

NP NS

LR2

CMSCMP

Ciw

Complete L-L-C-TStructure

Ferrite Core

Leakage Layer

Secondary Winding

Primary Winding

Main core

LR

NS

NP

LM

LMCR

Acore

ka⋅lcore

lcore

wwAC

ka⋅lcore /2

lT

l

wT

Bottom conductor Mth layer

Top conductor Mth layer

Bottom conductor mth layer

Top conductor mth layer

w

Bottom conductor 1st layer

Top conductor 1st layer

HNI/w mNI/w MNI/w

I/Mw

(m-1)NI/w

x = 0

x = l

Structure length

N conductors

Bottom conductor Mth layer

Top conductor Mth layer

Bottom conductor mth layer

Top conductor mth layer

w

Bottom conductor 1st layer

Top conductor 1st layer

HNI/w mNI/w MNI/w

I/Mw

(m-1)NI/w

x = 0

x = l

Structure length

N conductors

Prototype 2

Primary side

Secondary side

Heat sink

Gate drives

Prototype 3 - connected

Prototype 1

Thermo-couples

Input voltage measurement

Output voltage measurement

Input current measurement

DC-input

DC-output

0.001

1

0.01

0.1

0.2

0.5

0.02

0.05

0.002

0.005

Cor

e as

pect

rat

io k

a

Inherent leakage inductance constraint

Local-minimum507W.cm3

Volume-loss product constraint

600

1k

2k

12501.5k

1500 10050 200Flux density BT (mT) (a)

0.001

1

0.01

0.1

0.2

0.5

0.02

0.05

0.002

0.005

Cor

e as

pect

rat

io k

a



Volume-loss product constraint

1k500

1.5k

350

400

1500 10050 200Flux density BT (mT) (b)

0.001

1

0.01

0.1

0.2

0.5

0.02

0.05

0.002

0.005

Cor

e as

pect

rat

io k

a



Profile restriction

250

1k500

375

1.5k

1500 10050 200Flux density BT (mT) (c)

0.001

1

0.01

0.1

0.2

0.5

0.02

0.05

0.002

0.005

Cor

e as

pect

rat

io k

a


Profile restriction


250

1k500 375

1500 10050 200Flux density BT (mT) (d)

Initial construction technology

Improved electromagnetic modeling and optimization

Initial electromagnetic modeling

1kW, 1MHz prototype (1999) – 130W/in3

Improved construction technology CPES

½kW, 1MHz prototype 1 (2001) – 240W/in3

½kW, 1MHz prototypes 2 and 3(2002) – 480W/in3

Process development

Core aspect ratio

Jmax

0

1

0

Bmax0,001

Current density Flux density

Design Parameter Prototype 1 Prototype 2 Prototype 3

Input Voltage (V) 200.0 ±0.7 200.0 ±0.7 200.1 ±0.7

Input Current (A) 2.89 ±0.02 2.87 ±0.02 2.83 ±0.02

Output Voltage (V) 49.9 ±0.06 50.3 ±0.07 50.3 ±0.07

Output Current (A) 10.15 ±0.02 10.17 ±0.02 10.00 ±0.02

Input Power (W) 577.7±6.5 574.7±6.4 564.9 ±6.4

Output Power (W) 506.3 ±1.9 511.7 ±1.9 503.3 ±1.9

Total Converter Losses (W) 71.4 ±8.4 63.0 ±8.4 61.6 ±8.3

Converter Efficiency (%) 87.7 ±1.3 89.0 ±1.3 89.1 ±1.3

Module power density [W/cm3 / W/in3] 14.1 / 230.5 29.8 / 487.6 28.6 / 468.6

Top core temperature 47.4 45.9 42.2

Middle inside temperature 57 51 48

Bottom inside temperature 51 44 43

Heatsink temperature 26.2 26.3 26.2


Input Voltage (V) 200.0 ±0.7 200.0 ±0.7 200.1 ±0.7

Input Current (A) 2.89 ±0.02 2.87 ±0.02 2.83 ±0.02

Output Voltage (V) 49.9 ±0.06 50.3 ±0.07 50.3 ±0.07

Output Current (A) 10.15 ±0.02 10.17 ±0.02 10.00 ±0.02

Input Power (W) 577.7±6.5 574.7±6.4 564.9 ±6.4

Output Power (W) 506.3 ±1.9 511.7 ±1.9 503.3 ±1.9









Input Voltage (V) 200.0 ±0.7 200.0 ±0.7 200.1 ±0.7

Input Current (A) 2.89 ±0.02 2.87 ±0.02 2.83 ±0.02

Output Voltage (V) 49.9 ±0.06 50.3 ±0.07 50.3 ±0.07

Output Current (A) 10.15 ±0.02 10.17 ±0.02 10.00 ±0.02

Input Power (W) 577.7±6.5 574.7±6.4 564.9 ±6.4

Output Power (W) 506.3 ±1.9 511.7 ±1.9 503.3 ±1.9








Design ParameterDesign Parameter Prototype 1Prototype 1 Prototype 2Prototype 2 Prototype 3Prototype 3

Input Voltage (V)Input Voltage (V) 200.0 ±0.7200.0 ±0.7 200.0 ±0.7200.0 ±0.7 200.1 ±0.7200.1 ±0.7

Input Current (A)Input Current (A) 2.89 ±0.022.89 ±0.02 2.87 ±0.022.87 ±0.02 2.83 ±0.022.83 ±0.02

Output Voltage (V)Output Voltage (V) 49.9 ±0.0649.9 ±0.06 50.3 ±0.0750.3 ±0.07 50.3 ±0.0750.3 ±0.07

Output Current (A)Output Current (A) 10.15 ±0.0210.15 ±0.02 10.17 ±0.0210.17 ±0.02 10.00 ±0.0210.00 ±0.02

Input Power (W)Input Power (W) 577.7±6.5577.7±6.5 574.7±6.4574.7±6.4 564.9 ±6.4564.9 ±6.4

Output Power (W)Output Power (W) 506.3 ±1.9506.3 ±1.9 511.7 ±1.9511.7 ±1.9 503.3 ±1.9503.3 ±1.9

Total Converter Losses (W)Total Converter Losses (W) 71.4 ±8.471.4 ±8.4 63.0 ±8.463.0 ±8.4 61.6 ±8.361.6 ±8.3

Converter Efficiency (%)Converter Efficiency (%) 87.7 ±1.387.7 ±1.3 89.0 ±1.389.0 ±1.3 89.1 ±1.389.1 ±1.3

Module power density [W/cm3 / W/in3]Module power density [W/cm3 / W/in3] 14.1 / 230.514.1 / 230.5 29.8 / 487.629.8 / 487.6 28.6 / 468.628.6 / 468.6

Top core temperatureTop core temperature 47.447.4 45.945.9 42.242.2

Middle inside temperatureMiddle inside temperature 5757 5151 4848

Bottom inside temperatureBottom inside temperature 5151 4444 4343

Heatsink temperatureHeatsink temperature 26.226.2 26.326.3 26.226.2

L-L-C-T Loss Component (W) Prototype 1 Prototype 2 Prototype 3

Ferrite Core Losses 4.8 4.3 3.7Dielectric Losses 5.5 5.6 5.0Primary Conductor Losses 14.1 11.6 14.8Secondary Conductor Losses 2.9 4.6 5.3Total Estimated L-L-C-T Losses 27.3 26.1 28.8Semiconductor Losses 31.0 31.1 30.8Estimated Converter Losses 58.3 57.2 59.6Experimental Losses 71.4 ±8.4 63.0 ±8.4 61.6 ±8.3Unaccounted Losses 13.1 ±8.4 5.8 ±8.4 2.0 ±8.3Calculated module efficiency [%] 94.6 ±1.3 94.9 ±1.3 94.3 ±1.3

L-L-C-T Loss Component (W) Prototype 1 Prototype 2 Prototype 3

Ferrite Core Losses 4.8 4.3 3.7Dielectric Losses 5.5 5.6 5.0Primary Conductor Losses 14.1 11.6 14.8Secondary Conductor Losses 2.9 4.6 5.3Total Estimated L-L-C-T Losses 27.3 26.1 28.8Semiconductor Losses 31.0 31.1 30.8Estimated Converter Losses 58.3 57.2 59.6Experimental Losses 71.4 ±8.4 63.0 ±8.4 61.6 ±8.3Unaccounted Losses 13.1 ±8.4 5.8 ±8.4 2.0 ±8.3Calculated module efficiency [%] 94.6 ±1.3 94.9 ±1.3 94.3 ±1.3

L-L-C-T Loss Component (W)L-L-C-T Loss Component (W) Prototype 1Prototype 1 Prototype 2Prototype 2 Prototype 3Prototype 3

Ferrite Core Losses Ferrite Core Losses 4.84.8 4.34.3 3.73.7Dielectric LossesDielectric Losses 5.55.5 5.65.6 5.05.0Primary Conductor LossesPrimary Conductor Losses 14.114.1 11.611.6 14.814.8Secondary Conductor LossesSecondary Conductor Losses 2.92.9 4.64.6 5.35.3Total Estimated L-L-C-T LossesTotal Estimated L-L-C-T Losses 27.327.3 26.126.1 28.828.8Semiconductor LossesSemiconductor Losses 31.031.0 31.131.1 30.830.8Estimated Converter LossesEstimated Converter Losses 58.358.3 57.257.2 59.659.6Experimental LossesExperimental Losses 71.4 ±8.471.4 ±8.4 63.0 ±8.463.0 ±8.4 61.6 ±8.361.6 ±8.3Unaccounted LossesUnaccounted Losses 13.1 ±8.413.1 ±8.4 5.8 ±8.45.8 ±8.4 2.0 ±8.32.0 ±8.3Calculated module efficiency [%]Calculated module efficiency [%] 94.6 ±1.394.6 ±1.3 94.9 ±1.394.9 ±1.3 94.3 ±1.394.3 ±1.3

Prototype 1

Prototype 2

Prototype 3

A

B

C

DE

A

B

C

DE

A

B

C

DE

Series resonant ISP3 L-L-C-T structure: (a) equivalent circuit and (b) exploded view

(a)

(b)

Structural dimensions for the L-L-C-T structure (cross-sectional view from top)Two-dimensional magnetic field intensity for the primary-

side winding window showing the spatial distribution

3D design space showing some idealized design constraints

Remaining designs meeting

design constraints

Efficiency constraint

Inherent inductance constraint

Volumetric constraint

0

1

Bmax0,001

Current density

Core aspect ratio

Flux density

Jmax

Partial design spaces showing volume-loss product for current densities of (a) 8A/mm2, (b) 12A/mm2, (c) 16A/mm2, (d) 20A/mm2 for the 500W, 1MHz prototype converter

Experimental setup showing integrated L-L-C-T prototypes

Future prototypes –1000W/in3 possible

Design space showing location of selected sections

Modeling results compared to experimental measurementsExperimental measurement results Prototypes

cpes virginia tech

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(a) Temperature recording and curve fitting

(b) Thermal equivalent circuit of four time constants

An Experiment for Accurate Characterization ofTransient and Steady-state Die Thermal Parameters

Sponsored by: Philips Research

Jian Yin, J. D. van Wyk and W. G. Odendaal

D4.9

20032003

(b) Gate-source voltage of the MOSF (c) Experimental waveform of Vgs

time

Achieve transient thermal parameters to improve thermal management compared to the existing approachesObjective

Setup

Experiment

Recording of cool-down curve and achievement of RC equivalent circuit

On-state resistance Measurement

• Accurate determination of thermal parameters of power device packaging

• Identification of the physical meaning

• A valuable method to investigate and evaluate die connecting approaches

• Further careful analysis provides a key to an improved or new double-sided cooling structure

0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.520

22

24

26

28

30

32

34

Time (S)

Tem

pera

ture

(oC

)D. U. T

DBCSolder

Heat Sink

Insulating Materials

Thermo-electric CoolerHeat Spreader

Heat Spreader

Adjustable Fixture

Wire bond sample

0.1156 0.2184

0.0217 0.1224 1.6697

0.0655

To

0.3815

0.2250

Die HeatSpreader

(a) Temperature transient curve

Vgs

T

time

d

D

D.U.T

Heat Sink

Heating andMeasurement

TemperatureControl

Voltage

T

TE Module

(d) Control Process

• Self heating by measurement:0.00134°C (one pulse)

• MOSFET die is controlled tolinear region to heat and saturation region to measure

• Bottom temperature of the heatspreader is controlled

• Encapsulation and natural air flow

• Blue uneven line is temperature recording curve and red line iscurve fitting curve

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88

Measurement and Calculation of Residual Stress between Substrate and Copper Deposition in

Integrated Passive Modules


Ning Zhu, S.Y.Lee, J.D.van Wyk, W.G.Odendaal, J.N.Calata

Problem:Possible reasons for failures of passive modules: Intrinsic residual stress & thermal stress in

metallization layer. Objective:

Compare the contributions of thermal-mechanical stress and intrinsic residual stress to the mechanical failures of the moduleMethodology:• use smooth,flat substrate to show up the metallization stresses• use same metallization procedures as processing passive modules• measure the sample bending using Dektak surface profile measuring system • calculate the residual stress based on Stoney Equation• simulate the thermal-mechanical stress of the same films using IDEAS software

D4.10

20032003

16mmGlass

16 mm18mm

18mm

Copper

• Sample Construction: • Sample bending after electroplating:

-5000

0

5000

10000

15000

20000

25000

30000

35000

40000

• Measurement results: example• Measurement equipment:

0

5000

10000

15000

20000

25000

30000

35000

⋅

−+⋅

−⋅+⋅= 33

11)(61

ss

sf

f

f

fsff d

Ed

E

dddR υυσ

• Residual stress Calculations:

• Thermal stress simulation results: example

0

5000

10000

15000

20000

25000

30000

35000

40000

Measurement Length 5mm

Strain δ 3.4µm

Bottom side of the copper Top view of the sample

100MPa

Sputtered copper (400-500nm)

Glass substrate(150µm)

Electroplatedcopper (100µm)

• Cross-section of the sample:

Electroplated copper

Glass substrate

Sample processing steps: 1. Sandblast substrate(Grit #400) for adhesion; 2. Sputter Cu; 3. Electroplate Cu for 100 µm.

Electroplating conditions: 1. Room temperature: around 20°C; 2.Current density 300 A/m2 ; 3.Plating time: 4 hours

• Electroplating tank:

Conclusions: 1. Residual stresses in metallized films are measurable by substrate distortion. 2. By careful experimental investigation, consistent results can be obtained.3. A methodology to compare residual and thermal-mechanical stresses in metal film on

substrate has been developed.Future work: What’s the relations between metallization process parameters and the residual stresses?

3851.38Thermal Cond’ty(W/m-K)

11064Young’s Modulus(Gpa)

0.3430.19Poisson’s Ratio

16.44CTE(µm/m-°C)100150Thickness(µm)Cuglassmaterials

Material properties: Comparison between residual stress and thermal -mechanical

stress: example

1.5

100

1

10

100

residual thermal-mech’al

MPa

1.528 MPa1.894 m3.3µmMeasurement (c)

1.505 MPa1.923 m3.25µmMeasurement (b)

1.574 MPa1.838 m3.4µmMeasurement (a)Residual stressCurvature RStrain δ

cpes virginia tech

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A Planar Process Module for Active IPEM Manufacturing

Sponsored by: NSF

Z. Liang and J. D. van Wyk20032003

Base Substrate

CSP

Base Substrate

CSP CSP

Surface Mount

Double sided Cooling Capability

Single Chip Packaging

Dual Chip Packaging

IPEM Packaging

To Integrated Power Chips Stage

3-D Assembly

Gat

e D

river

High-density Assembly

Double MOSFET Module for Half-bridge Switching Configuration

Embedded Power

From Power MOSFET, IGBT, Diode Bare Dice

2 CoolMOSFETs+2 SiC Diodes for PFC Power Switching

DPS System Active IPEM: 2 CoollMOS+2 SiC Diodes +2 Si MOSFETs

Discrete MOSFET Device

S1 S2S1 S2

G1 G2

S1 S2S1 S2

G1 G2

D1 D2D1 D2

D1 D2D1 D2

G1 S1

D1

G2

S2

D2

Gat

e D

river

Gat

e D

river

Drain (Cr/V-Ni/Au)

Source (Al)Gate (Al)

Ceramic Chip Carrier Preparation

Multichip Mount

SiSi

Interlayer Dielectric Coat

Si Si

Metallization Pattern Deposition

Si Si

D4.11

cpes virginia tech

90

Preliminary Electromagnetic Modeling of an Integrated RF-EMI Filter

Sponsored by: NSF

Lingyin Zhao and J. D. van Wyk

S8.1

20032003

The prototype

Preliminary calculation results.

1 MHz10 kHz 100 MHz~22 MHz

0 dB

0 °

-180 °

-50 dB


0 dB

0 °

-180 °

-50 dB


0 dB

0 °

-180 °

-50 dB

Slope: 40 dB/decade

103 104 105 106 107 108-60

-40

-20

0

20

Frequency (Hz)

Gai

n (d

B)

Rg=1m Ohms

103

104

105

106

107

108

-200

-100

0

100

200

Frequency (Hz)

Pha

se (

degr

ee)

Rg=1m Ohms

Measurement results of transfer gain at ZL=50Ω.

Cu

Al2O3Ni

NiBaTiO3

Al2O3

Cu

HF: High AttenuationLF: Conducting

+

_Integrated Power Electronic Module LOAD_

+SOURCE RF-EMI

Filter

+

_Integrated Power Electronic Module LOAD_

+_+

SOURCE RF-EMI Filter

• Proximity effect does influence the resonances and current distributions.• The filter behaves like a R-C network at very high frequency due to the dominance of resistances over inductances.• The measurement setup used can not measure the real transfer gain. • Accurate loss modeling – future work

• Proximity effect does influence the resonances and current distributions.• The filter behaves like a R-C network at very high frequency due to the dominance of resistances over inductances.• The measurement setup used can not measure the real transfer gain. • Accurate loss modeling – future work

C12∆x

L1∆x

L2∆x

G12∆x

R1∆x

R2∆x

I1(x,t)

I2(x,t)

I1(x +∆x,t)

I2(x +∆x,t)

C34∆x

L3∆x

L4∆x

G34∆x

R3∆x

R4∆x

I3(x,t)

I4(x,t)

I3(x +∆x,t)

I4(x +∆x,t)

C23∆x G23∆x

C12∆x

L1∆x

L2∆x

G12∆x

R1∆x

R2∆x

I1(x,t)

I2(x,t)

I1(x +∆x,t)

I2(x +∆x,t)

C34∆x

L3∆x

L4∆x

G34∆x

R3∆x

R4∆x

I3(x,t)

I4(x,t)

I3(x +∆x,t)

I4(x +∆x,t)

C23∆x G23∆x

C12∆x

L1∆x

L2∆xG12∆x

R1∆x

R2∆x

C34∆x

L3∆x

L4∆xG34∆x

R3∆x

R4∆x

C23∆x G23∆x

M3,12∆x

M3,12∆x

M4,12∆x

M4,12∆x

M2,34∆x

M2,34∆x

M1,34∆x

M1,34∆x

C12∆x

L1∆x

L2∆xG12∆x

R1∆x

R2∆x

C34∆x

L3∆x

L4∆xG34∆x

R3∆x

R4∆x

C23∆x G23∆x

M3,12∆x

M3,12∆x

M4,12∆x

M4,12∆x

M2,34∆x

M2,34∆x

M1,34∆x

M1,34∆x

(a) Model without considering proximity effect

(b) Model with proximity effect considerations

Proximity Effect Modeling

I

I

A

B

C

D

IZL

ZL VoutVin

1

23

4

0 l x

I

I

A

B

C

D

IZL

ZL VoutVin

1

23

4

0 l x

Multi-conductor Transmission Structure Model

Measurement setup.

Equivalent connections

Measurement Issues

Parameter Extraction

Zg IZg

I

I

A

B

C

D

IZL

ZL VoutVin

1

23

4

0 l x

Zg IZg

I

I

A

B

C

D

IZL

ZL VoutVin

1

23

4

0 l x

Difference made by common-ground measurement setup.

103 104 105 106 107 108-60

-40

-20

0

20

Frequency (Hz)

Gai

n (d

B)

Rg=1M OhmsRg=1m Ohms

103 104 105 106 107 108-200

-100

0

100

200

Frequency (Hz)

Pha

se (

degr

ee)

Rg=1M OhmsRg=1m Ohms

Objectives: To model the high frequency characteristics of an integrated RF-EMI filterTo facilitate the filter design

Objectives: To model the high frequency characteristics of an integrated RF-EMI filterTo facilitate the filter design

cpes virginia tech

91

High Density Integrated Power Passive with Single Layer Symmetric Structure

Sponsored by: NSF

Wenduo Liu, J. D. van Wyk, W.G. Odendaal

S8.2

20032003

)(0 Hll

l

AL

r

geg

corecell

µ

µ−

+=

)(0 Fh

AC

d

cellrcell

εε=

Cr Lr1 Lr2

Cp LM

n:1

)1(

)1)(1(2

21

2

−

−−≈

pMr

rMpropen CLC

CLCLjZ

ωω

ωω)1'(

)1](1)'([

22

12

212

−

−−+≈

prr

prrrrshort CLC

CLCLLjZ

ωω

ωω

Open Circuit

7.67E+06

8.71E+05

5.19E+05

0.1

1

10

100

1000

1.00E+05 1.00E+06 1.00E+07 1.00E+08

f (Hz)

Impe

danc

e (o

hms)

-90

-70

-50

-30

-10

10

30

50

70

90

Phas

e

Impedance Phase

Short Circuit

7.76E+06

3.56E+06

2.40E+06

0.1

1

10

100

1000

1.00E+05 1.00E+06 1.00E+07 1.00E+08

f (Hz)

Impe

danc

e (o

hms)

-90

-70

-50

-30

-10

10

30

50

70

90

Phas

e

Impedance Phase

Internal Cell

Magnetic fluxCurrent flow

1st Order Approximation of a Single Cell

Single Layer Symmetric Structure

A

B

1234

5678

Interconnections are achieved on the vertical surface.

A

B

1 2 3 4

8 7 6 5

Schematic Diagram

Various interconnections provide flexibility to achieve various energy transfer functions. 1st Order Approximation of a Module

with Specific Interconnection

Schematic of One-dimensional Thermal Model

X

T (ºC)

Z

X

0 1 2 3 4 5 6 7 8 9 10 …13 14

A section in the ferrite layer

Ferrite

Insulation layer Copper Dielectric

Current Distribution and Conductor Loss Simulation Design Optimization Map

Thermal Constraint

Constructional Constraint

L-L-C-T Module

2nd Order Approximation

524kHz

871kHz

7.56MHz 2.39kHz

4.57kHz

7.94kHz

Calculation Results

Experimental Results

Z

T (ºC)

X

cpes virginia tech

92

Modeling of Skin- and Proximity Effect Losses in Foils and in Planar Litz Windings


Shen Wang, M.A. de Rooij, W.G. Odendaal, J.D. Van Wyk, D. Boroyevich

S8.4

20032003

MotivationsThe new trend in power converters is to design planar magnetic components, aiming at low profile. However, the increasing ac resistance at high operating frequency is an important constraint.

Assumption: End-effect can be ignored. The magnetic fields are always perpendicular to current flow and parallel to the flat surface of the conductor.

z

yx

hw

Infinite length

( w >> h )I

H

To account for the losses due to skin- and proximityeffect respectively, we define two factors andFΛ GΛ

dceGdcrmsF RHwRIP 222)1( Λ++Λ=

1coscoshsinsinh

2−

−+⋅=Λ

ααααα

F ααααα

coscoshsinsinh

+−⋅=Λ G

Single Foil Conductor

Planar Litz Conductor

3D FEM Modeling

A 3-dimensional finite element analysis method was used to calculate the effective ac resistance.

Litz winding can result in lower ac resistance than planar winding in a specific freq. range

Strand/s: Narrow conductor/s used to make up a planar litzconductorPlanar Litz Conductor: A planar conductor comprised of many isolated strands that are weaved together to form a single high frequency, higher current carrying capacity conductor.Strand angle: The angle the strand makes with the direction of the planar litz conductor.

Top Bottom

Copper layers

AB

AB

JJPlanar Winding and E Core

High eddy current due to proximity effect

Uniform current

each strand subjected to the magnetic field everywhere in the winding window

Litz Winding and E Core

I I

Top layer strand

Bottom layer strand

Vias

Planar conductor

Strand angle

Planar Litz conductor

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High Density Integrated Power Passives with Vertical Interconnect and Stacked Structure

Sponsored by: (NSF)

Wenduo Liu, J. D. van Wyk, W.G. Odendaal

NP4.1

20032003

Magnetic flux

Current flow

The Stacked Structure

3D Interconnection

Planar Symmetric Structure Small Profile and Volume

Complete Usage of Space

Interconnections determine the energy transfer functions in the module.The challenge is to achieve interconnections for modules with many internal cells.

Interleaving Leads Stacked Structure Encapsulated ModuleCreating Interconnection

by Metal Deposition

Height

Generation 4

57.6MHz

1.93MHz

66.8MHz1.00

10.00

100.00

1000.00

10000.00

100000.00

1.00E+05 1.00E+06 1.00E+07 1.00E+08

Frequency (Hz)

Mag

nitu

de (o

hms)

-100.00

-80.00

-60.00

-40.00

-20.00

0.00

20.00

40.00

60.00

80.00

100.00

Phas

e (°

)

Magnitude Phase

Module: 2MHz Resonator

Current Distribution and Conductor Losses Simulation

One-Dimensional Thermal Calculation

Design Optimization Map

Height

Thermal Constraint

1st Order Approximation

Measurement Result

cpes virginia tech

94

session 4 packaging techniques

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