sakura-g specification ver.1.0 englishsatoh.cs.uec.ac.jp/sakura/.../sakura-g...english.pdf · the...

SAKURA-G Side-channel AttacK User Reference Architecture

Specifications

Version 1.0

August 1, 2013

SAKURA Hardware Security Project

MORITA TECH CO., LTD.

2

Revision History

The following table shows the revision history.

Date Version Revision

2013-08-01 1.0 Initial release.

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Table of Contents

1. Overview ........................................................................................................................................... 5

2. Operational Instructions .................................................................................................................. 7

2.1. Power Circuit ........................................................................................................................... 10

2.1.1. Block Diagram .................................................................................................................. 10

2.1.2. Power-On Sequence ........................................................................................................... 11

2.1.3. Voltage Calibration ............................................................................................................ 11

2.2. Configuration ........................................................................................................................... 12

2.2.1. JTAG Chain ...................................................................................................................... 12

2.2.2. Configuration Mode .......................................................................................................... 13

2.2.3. Remote Configuration ...................................................................................................... 13

2.3. Clock System ........................................................................................................................... 14

2.4. Measurement Points ............................................................................................................... 15

2.5. USB Interface .......................................................................................................................... 16

2.6. I/O ............................................................................................................................................. 17

2.6.1. Connectors ........................................................................................................................ 17

2.6.2. Switches ............................................................................................................................ 22

2.6.3. Jumpers ............................................................................................................................ 24

3. FPGA I/O Assignments ................................................................................................................... 25

3.1. Main FPGA .............................................................................................................................. 25

3.1.1. Clock and Reset ................................................................................................................ 29

3.1.2. User LED .......................................................................................................................... 29

3.1.3. User Push switch .............................................................................................................. 29

3.1.4. User DIP switch ................................................................................................................ 29

3.1.5. User Header ...................................................................................................................... 30

3.1.6. USB Interface ................................................................................................................... 31

3.1.7. FPGA Interconnect ........................................................................................................... 31

3.1.8. Main FPGA Configuration ............................................................................................... 33

3.1.9. Reserved I/O ..................................................................................................................... 34

3.2. Controller FPGA ...................................................................................................................... 35

3.2.1. Clock and Reset ................................................................................................................ 39

3.2.2. User LED .......................................................................................................................... 39

3.2.3. User Push switch .............................................................................................................. 39

3.2.4. User DIP switch ................................................................................................................ 40

3.2.5. User Header ...................................................................................................................... 40

3.2.6. USB Interface ................................................................................................................... 41

3.2.7. FPGA Interconnect ........................................................................................................... 41

4

3.2.8. Main FPGA Configuration ............................................................................................... 41

3.2.9. Controller FPGA Configuration ....................................................................................... 42

4. Board Design ................................................................................................................................... 43

4.1. Board Revision ......................................................................................................................... 43

4.2. Schematic ................................................................................................................................. 44

4.3. Parts List ................................................................................................................................. 63

4.4. Board Layout ........................................................................................................................... 67

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1. Overview The SAKURA-G FPGA board is designed for research and development on hardware security, such as

Side-Channel Attacks (SCA), Fault Injection Attacks (FIA), Physical Unclonable Functions (PUF), and dynamic

reconfiguration. Two Spartan-6 FPGAs are integrated on the board and serve as the controller and main security

circuits, respectively. SAKURA-G is highly compatible with SASEBO-GII. A Spartan-6 LX75 provides a logic

circuit 2.5 times larger than the Virtex-5 LX30 on SASEBO-GII. Ultra-low-noise board design and an on-board

amplifier make power analysis easier. Users can easily configure and operate SAKURA-G using Verilog-HDL code

designed for SASEBO-GII and the free Xilinx ISE WebPACK design software.

Figure 1 : SAKURA-G Board Overview (Top View)

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Table 1 : Key Specifications

FP

GA

#1 (Main

)

FPGA ・Xilinx Spartan-6 (XC6SLX75-2CSG484C)

Configuration ROM ・32Mbit SPI-ROM (Atmel/Adesto AT45DB321D)

Configuration Mode ・JTAG

・from SPI-ROM : Master SPI (x1)

・from Controller FPGA : Master Serial / Master SPI (x1, x2, x4) /

Master SelectMAP (x8) / Slave SelectMAP (x8) / Slave Serial

Clock ・48.000MHz Clock Oscillator

Reset ・210ms(typ.)-delayed reset signal from DONE

・Manual Reset (Push switch)

User LED ・10 bit

User switch ・2 bit Push switches

・8 bit DIP switch

User GPIO ・26 bit Header

・2 ports SMA (2 single ended or 1 differential pair, clock capable)

USB I/F ・FTDI FT2232H Channel B

Measurement point ・High side of VCCINT (Core)

Amplifier ・360MHz Bandwidth, +20dB Gain (+14dB for 50ohm termination)

FP

GA

#2 (Con

troller)

FPGA ・Xilinx Spartan-6 (XC6SLX9-2CSG225C)

Configuration ROM ・32Mbit SPI-ROM Atmel/Adesto AT45DB321D

Clock ・48.000MHz Clock Oscillator

Reset ・210ms(typ.)-delayed reset signal from DONE

・Manual Reset (Push switch)

User LED ・10 bit

User switch ・2 bit Push switch

・8 bit DIP switch

User GPIO ・26 bit Header

・2 ports SMA (2 single ended or 1 differential pair, clock capable)

USB I/F ・FTDI FT2232H Channel A

FPGA Interconnect ・51 bit

Rated voltage ・5V ±5%

Rated current ・500mA via USB (Protected by resettable fuse)

・3A via External Power Supply (Rated by LDO)

Circuit board ・6 Layers, FR-4, 1.6t

Dimensions ・140mm × 120mm

7

2. Operational Instructions Figure 2 and Figure 3 show the functions of the each part on the SAKURA-G board. Figure 4 shows the functions

as block diagram.

Main FPGA

Controller FPGA

Amplifier

JTAG

JTAG

PowerSwitch

USB-B

MeasurementPoint

User I/O

User I/O

System Settings

User I/O

User I/O

EXT.VIN

LDO

Reset

Reset

SPI-ROM

Figure 2 : SAKURA-G Board Functions (Top View)

8

Figure 3 : SAKURA-G Board Functions (Bottom View)

9

MainFPGA

Spartan-6XC6SLX75

ControllerFPGA

Spartan-6XC6SLX9

USB Interface

Push Switch

DIP Switch

Header

LED

Push Switch

DIP Switch

Header

LED

LDO 1.2V

LDO 2.5V

Amplifier

MeasurementPoint

LDO 1.2V

LDO 2.8V

LDO 3.3V

Oscillator

Reset

SPI-ROM

JTAG

SMA

Oscillator

Reset

SPI-ROM

JTAG

SMA

USB B

External VIN

Figure 4 : SAKURA-G Functional Block Diagram

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2.1. Power Circuit The recommended source voltage (EXT 5.0V) range is between 4.75V and 5.25V. The absolute maximum rating of

input voltage is 12.6V, limited by amplifier AD8000.

2.1.1. Block Diagram

The power supply can be selected to come from the USB B connector (CN6) or the External 5.0V connector (CN1)

by toggling Power Switch (SW1).

Figure 5 : Power System

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2.1.2. Power-On Sequence

As shown in Figure 6, FPGA configuration starts when voltages VCC2V5 and VCC1V2 rise according to the

power-on reset sequence. When the configuration is completed, a supervisor IC holds the software reset signal low

for 210ms.

Figure 6 : Power-On Sequence of Main FPGA

Figure 7 : Power-On Sequence of Controller FPGA

2.1.3. Voltage Calibration

The voltage of VCC1V2M (core voltage for the nain FPGA) can be adjusted from 0.5 – 1.5V by using trimmer

VR1. Shorting JP2 with a jumper can prevent voltage drop at VCCINT when large power consumption is required.

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2.2. Configuration The controller FPGA should be configured before the main FPGA by setting DIP switch SW2 to an appropriate

position, excepting in cases where the main FPGA is configured using a JTAG chain.

2.2.1. JTAG Chain

Each FPGA has its own JTAG chain. The JTAG connectors, CN2 and CN4, are connected to the main FPGA U1

and the controller FPGA U2, respectively. SPI-ROMs are not connected to these JTAG chain.

Figure 8 : JTAG Chain for Main FPGA

Figure 9 : JTAG Chain for Controller FPGA

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2.2.2. Configuration Mode

The configuration mode pins M0 and M1 of the main FPGA can be set using DIP switch SW2 or the controller

FPGA. Only DIP switch SW2-1 should be set to high when configuring the main FPGA from the SPI-ROM.

Figure 10 : Configuration Mode Settings

2.2.3. Remote Configuration

The configuration pins of the main FPGA are connected to the controller FPGA. When remote configuration is not

used, all configuration signals should be set to pull-up or float to avoid failing the configuration process.

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Figure 11 : Configuration Signals of Main FPGA

2.3. Clock System Each FPGA has each own on-board 48MHz clock oscillator. The oscillators can be disabled when the FPGAs use

external clocks through two pairs of SMA connectors. The USB Interface chip FTDI FT2232H supplies 60MHz

clock when the chip is operated in a synchronous FIFO mode.

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Spartan-6XC6SLX75

(U1)

Spartan-6XC6SLX9

(U2)

J4 J5

P(+) N(-)

J6 J7

P(+) N(-)

SMA SMA

48.000MHzOscillator

(U11)

48.000MHzOscillator

(U14)

48MHz Inhibit 48MHz Inhibit

SW2-4 SYSTEM

CLKINH

(*1) 1 differential pair or 2 single ended

(*1) (*1)

3

3

560MHz

FT2232H(U17)

(*2)

(*2) This clock signal is only available when using “FT245 Synchronous FIFO Interface Mode”.

Clock CapableInterconnects

Figure 12 : Clock System

2.4. Measurement Points Two measurement points, SMA connectors J1 and J2 are available to monitor power waveforms on the core voltage

VCCINT of the main FPGA as shown in Figure 13. The current-sense resistor R12 can be bypassed by inserting a

jumper into JP2. SMA connector J3 outputs the amplified waveform.

Figure 13 : Measurement Points

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2.5. USB Interface Channel A of the FT2232H is connected to the controller FPGA and channel B is connected to the main FPGA. The

reset pin of the FT2232H is simply pulled up.

Spartan-6XC6SLX75

(U1)

Spartan-6XC6SLX9

(U2)

FT2232H(U17)

8

8

8

8

BCBUS

BDBUS

ACBUS

ADBUS

PWREN#SUSPEND#

RESET#R119

JP5

R120

JP6

(*)

(*)

(*)

(*)

R1162.2k ohm

R117(*)

(*) Do Not Populate

Channel B

Channel A

Figure 14 : USB Interface

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2.6. I/O 2.6.1. Connectors

Table 2 : SAKURA-G Connectors

Designator Function

CN1 External Power Supply (5.0V)

CN2 JTAG for Main FPGA

CN3 Header for Main FPGA

CN4 JTAG for Controller FPGA

CN5 Header for Controller FPGA

CN6 USB

J1 High-side current-sense resistor for Main FPGA (Regulator IC side)

J2 High-side current-sense resistor for Main FPGA (FPGA side)

J3 Amplified J2

J4 Differential-clock capable SMA user I/O for Main FPGA (Positive)

J5 Differential-clock capable SMA user I/O for Main FPGA (Negative)

J6 Differential-clock capable SMA user I/O for Controller FPGA (Positive)

J7 Differential-clock capable SMA user I/O for Controller FPGA (Negative)

Table 3 : CN1 – External Power Supply

Pin Function

1 (▲) External 5.0V (EXT_VCC5V)

2 GND

Table 4 : CN2 – JTAG for Main FPGA

Pin Function

1 GND

2 2.5V (VCC2V5)

3 GND

4 TMS

5 GND

6 TCK

7 GND

8 TDO

9 GND

18

10 TDI

11 GND

12 N.C.

13 GND

14 N.C.

Table 5 : CN3 – Header for Main FPGA

Pin Function Net FPGA Pin I/O Voltage

1 User GPIO M_HEADER_0 A4 2.5V


3 User GPIO M_HEADER_2 B6 2.5V






9 GND GND

10 GND GND

11 User GPIO M_HEADER_8 C5 2.5V




15 User GPIO (Clock Capable) M_HEADER_12 A11 2.5V

16 User GPIO (Clock Capable) M_HEADER_13 A12 2.5V

17 User GPIO (Clock Capable) M_HEADER_14 B12 2.5V


19 GND GND

20 GND GND









19

29 GND GND

30 GND GND

31 User GPIO (Clock Capable) M_HEADER_CLK_P B10 2.5V

32 User GPIO (Clock Capable) M_HEADER_CLK_N A10 2.5V

33 2.5V power supply VCC2V5


35 GND GND

36 GND GND



39 VIN power supply VIN


Table 6 : CN4 – JTAG for Controller FPGA

Pin Function

1 GND

2 2.5V (VCC2V5)

3 GND

4 TMS

5 GND

6 TCK

7 GND

8 TDO

9 GND

10 TDI

11 GND

12 N.C.

13 GND

14 N.C.

Table 7 : CN5 – Header for Controller FPGA


1 User GPIO C_HEADER_0 N4 2.5V

2 User GPIO C_HEADER_1 M5 2.5V



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6 User GPIO C_HEADER_5 R4 2.5V

7 User GPIO C_HEADER_6 P5 2.5V


9 GND GND

10 GND GND


12 User GPIO (Clock Capable) C_HEADER_9 P7 2.5V

13 User GPIO (Clock Capable) C_HEADER_10 R7 2.5V

14 User GPIO (Clock Capable) C_HEADER_11 R8 2.5V

15 User GPIO (Clock Capable) C_HEADER_12 N8 2.5V


17 User GPIO C_HEADER_14 P9 2.5V


19 GND GND

20 GND GND

21 User GPIO C_HEADER_16 L5 2.5V

22 User GPIO C_HEADER_17 L6 2.5V

23 User GPIO (Clock Capable) C_HEADER_18 L8 2.5V






29 GND GND

30 GND GND

31 User GPIO (Clock Capable) C_HEADER_CLK_N N7 2.5V

32 User GPIO (Clock Capable) C_HEADER_CLK_P M8 2.5V



35 GND GND

36 GND GND





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Table 8 : CN6 – USB

Pin Function

1 VBUS

2 D-

3 D+

4 GND

Table 9 : J1 – High-side current-sense resistor for Main FPGA (Regulator IC side)

Pin Function

Center Signal

Shield GND

Table 10 : J2 – High-side current-sense resistor for Main FPGA (FPGA side)

Pin Function

Center Signal

Shield GND

Table 11 : J3 – Amplified J2

Pin Function

Center Signal

Shield GND

Table 12 : J4 – Differential-clock capable SMA user I/O for Main FPGA (Positive)

Pin Function

Center Signal

Shield GND

Table 13 : J5 – Differential-clock capable SMA user I/O for Main FPGA (Negative)

Pin Function

Center Signal

Shield GND

Table 14 : J6 – Differential-clock capable SMA user I/O for Controller FPGA (Positive)

Pin Function

Center Signal

Shield GND

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Table 15 : J7 – Differential-clock capable SMA user I/O for Controller FPGA (Negative)

Pin Function

Center Signal

Shield GND

2.6.2. Switches

Table 16 : SAKURA-G Switches

Designator Switch Type Function

SW1 Slide (SPDT) Power

SW2 DIP (4bit) System settings

SW3 Push User push switch #0 for Main FPGA

SW4 Push User push switch #1 for Main FPGA

SW5 DIP (8bit) User DIP switch for Main FPGA

SW6 Push Reconfiguration for Main FPGA

SW7 Push Reset for Main FPGA

SW8 Push User push switch #0 for Controller FPGA

SW9 Push User push switch #1 for Controller FPGA

SW10 DIP (8bit) User DIP switch for Controller FPGA

SW11 Push Reconfiguration for Main FPGA

SW12 Push Reset for Main FPGA

Table 17 : SW1 – Power

Side Function

USB Power supply from USB (USB_VBUS)

OFF Power off

EXT Power supply from CN1 (EXT_VCC5V)

Table 18 : SW2 – System settings

Pin Function On Off

1 Mode M0 for Main FPGA M0 = 1 (*) M0 = 0

2 Mode M1 for Main FPGA M1 = 1 M1 = 0 (*)

3 Mode controller for Main FPGA Controller FPGA SW2-1, SW2-2 (*)

4 Disable clock oscillator for Main FPGA Disable Enable (*)

(*): Default settings

23

Table 19 : SW3 – User push switch #0 for Main FPGA


1 Push to High M_PUSHSW_0 D3 2.5V

Table 20 : SW4 – User push switch #1 for Main FPGA


1 Push to High M_PUSHSW_1 E3 2.5V

Table 21 : SW5 – User DIP switch for Main FPGA


1 ON to High M_DIPSW_0 B2 2.5V

2 ON to High M_DIPSW_1 B1 2.5V

3 ON to High M_DIPSW_2 C1 2.5V

4 ON to High M_DIPSW_3 D2 2.5V

5 ON to High M_DIPSW_4 D1 2.5V

6 ON to High M_DIPSW_5 E1 2.5V

7 ON to High M_DIPSW_6 F2 2.5V

8 ON to High M_DIPSW_7 F1 2.5V

Table 22 : SW6 – Reconfiguration for Main FPGA


1 Push to reconfigure M_PROG_B AA1 (*) 2.5V

(*): not for user I/O

Table 23 : SW7 – Reset for Main FPGA


1 Push to reset U12./MR D3 (U12./RST) 2.5V

Table 24 : SW8 – User push switch #0 for Controller FPGA


1 Push to High C_PUSHSW_0 L3 2.5V

Table 25 : SW9 – User push switch #1 for Controller FPGA


1 Push to High C_PUSHSW_1 M4 2.5V

24

Table 26 : SW10 – User DIP switch for Controller FPGA


1 ON to High C_DIPSW_0 K1 2.5V

2 ON to High C_DIPSW_1 L1 2.5V

3 ON to High C_DIPSW_2 L2 2.5V

4 ON to High C_DIPSW_3 M1 2.5V

5 ON to High C_DIPSW_4 N1 2.5V

6 ON to High C_DIPSW_5 N2 2.5V

7 ON to High C_DIPSW_6 P1 2.5V

8 ON to High C_DIPSW_7 M3 2.5V

Table 27 : SW11 – Reconfiguration for Controller FPGA


1 Push to reconfigure C_PROG_B R2 (*) 2.5V

(*): not for user I/O

Table 28 : SW12 – Reset for Controller FPGA


1 Push to reset U15./MR P2 (U15./RST) 2.5V

2.6.3. Jumpers

Table 29 : SAKURA-G Jumpers

Designator Function

JP1 (*) Current monitor of whole board

JP2 Short when bypassing the current-sense resistor (R12)

JP3 (*) Short when disable oscillator U11 for Main FPGA

JP4 (*) Short when disable oscillator U14 for Controller FPGA

JP5 (*) Short when control FTDI_RESET_B from Main FPGA

JP6 (*) Short when control FTDI_RESET_B from Controller FPGA

(*) : Optional (Jumper post is not populated)

25

3. FPGA I/O Assignments

3.1. Main FPGA Table 30 : Main FPGA (U1) I/O Assignments

Pin Function Net Bank Voltage

N20 IO_L47P_FWE_B_M1DQ0_1 FTDI_BCBUS0_RXF_B 1 2.5V

P20 IO_L64N_1 FTDI_BCBUS1_TXE_B 1 2.5V

R20 IO_L49P_M1DQ10_1 FTDI_BCBUS2_RD_B 1 2.5V

U20 IO_L51P_M1DQ12_1 FTDI_BCBUS3_WR_B 1 2.5V

V18 IO_L73N_1 FTDI_BCBUS4_SIWUB 1 2.5V

V20 IO_L71N_1 FTDI_BCBUS5 1 2.5V

V19 IO_L71P_1 FTDI_BCBUS6 1 2.5V

W20 IO_L53P_1 FTDI_BCBUS7_PWRSAV_B 1 2.5V

V21 IO_L52P_M1DQ14_1 FTDI_BDBUS0 1 2.5V

V22 IO_L52N_M1DQ15_1 FTDI_BDBUS1 1 2.5V

U22 IO_L51N_M1DQ13_1 FTDI_BDBUS2 1 2.5V

T22 IO_L50N_M1UDQSN_1 FTDI_BDBUS3 1 2.5V

R22 IO_L49N_M1DQ11_1 FTDI_BDBUS4 1 2.5V

P21 IO_L48P_HDC_M1DQ8_1 FTDI_BDBUS5 1 2.5V

P22 IO_L48N_M1DQ9_1 FTDI_BDBUS6 1 2.5V

N22 IO_L47N_LDC_M1DQ1_1 FTDI_BDBUS7 1 2.5V

Y20 IO_L67N_1 FTDI_PWREN_B 1 2.5V

W22 IO_L53N_VREF_1 FTDI_SUSPEND_B 1 2.5V

W1 IO_L9N_3 MC_IC_D0 3 2.5V

Y1 IO_L2N_3 MC_IC_D1 3 2.5V

Y2 IO_L2P_3 MC_IC_D2 3 2.5V

AA2 IO_L1P_3 MC_IC_D3 3 2.5V

AB2 IO_L1N_VREF_3 MC_IC_D4 3 2.5V

AB3 IO_L8N_3 MC_IC_D5 3 2.5V



AA6 IO_L64P_D8_2 MC_IC_D8 2 2.5V

AB6 IO_L64N_D9_2 MC_IC_D9 2 2.5V

AB11 IO_L31N_GCLK30_D15_2 MC_IC_D10 2 2.5V

AB12 IO_L30N_GCLK0_USERCCLK_2 MC_IC_D11 2 2.5V

AA12 IO_L30P_GCLK1_D13_2 MC_IC_D12 2 2.5V

26


AB14 IO_L15N_2 MC_IC_D14 2 2.5V

AA14 IO_L15P_2 MC_IC_D15 2 2.5V




AB18 IO_L2N_CMPMOSI_2 MC_IC_D19 2 2.5V

AA18 IO_L2P_CMPCLK_2 MC_IC_D20 2 2.5V

AB19 IO_L65P_1 MC_IC_D21 1 2.5V

AB20 IO_L65N_1 MC_IC_D22 1 2.5V

AA20 IO_L61P_1 MC_IC_D23 1 2.5V

AB21 IO_L61N_1 MC_IC_D24 1 2.5V

AA21 IO_L63P_1 MC_IC_D25 1 2.5V

AA22 IO_L63N_1 MC_IC_D26 1 2.5V

Y21 IO_L59P_1 MC_IC_D27 1 2.5V

Y22 IO_L59N_1 MC_IC_D28 1 2.5V

V3 IO_L18N_3 MC_IC_D29 3 2.5V

W3 IO_L9P_3 MC_IC_D30 3 2.5V

Y3 IO_L8P_3 MC_IC_D31 3 2.5V

W4 IO_L7P_3 MC_IC_D32 3 2.5V

Y4 IO_L7N_3 MC_IC_D33 3 2.5V

Y7 IO_L63P_2 MC_IC_D34 2 2.5V

Y8 IO_L47N_2 MC_IC_D35 2 2.5V

W9 IO_L47P_2 MC_IC_D36 2 2.5V

AA10 IO_L32P_GCLK29_2 MC_IC_D37 2 2.5V


AB10 IO_L32N_GCLK28_2 MC_IC_D39 2 2.5V

Y10 IO_L29N_GCLK2_2 MC_IC_D40 2 2.5V

Y11 IO_L31P_GCLK31_D14_2 MC_IC_D41 2 2.5V

W11 IO_L29P_GCLK3_2 MC_IC_D42 2 2.5V

W12 IO_L42P_2 MC_IC_D43 2 2.5V

Y12 IO_L42N_2 MC_IC_D44 2 2.5V

Y13 IO_L41P_2 MC_IC_D45 2 2.5V

Y14 IO_L16N_VREF_2 MC_IC_D46 2 2.5V

W14 IO_L16P_2 MC_IC_D47 2 2.5V

Y15 IO_L5P_2 MC_IC_D48 2 2.5V

27

W15 IO_L14P_D11_2 MC_IC_D49 2 2.5V

Y16 IO_L14N_D12_2 MC_IC_D50 2 2.5V

W17 IO_L1P_CCLK_2 M_CCLK_R0 2 2.5V

P3 IO_L43N_GCLK22_IRDY2_M3CASN_3 M_CLK_EXT0_N 3 2.5V

N4 IO_L43P_GCLK23_M3RASN_3 M_CLK_EXT0_P 3 2.5V

M1 IO_L38N_M3DQ3_3 M_CLK_INH_B 3 2.5V

J1 IO_L41N_GCLK26_M3DQ5_3 M_CLK_OSC 3 2.5V

AB5 IO_L65N_CSO_B_2 M_CSO_B 2 2.5V

Y17 IO_L3P_D0_DIN_MISO_MISO1_2 M_D0_DIN_MISO 2 2.5V

V13 IO_L12P_D1_MISO2_2 M_D1 2 2.5V

W13 IO_L12N_D2_MISO3_2 M_D2 2 2.5V

AA8 IO_L49P_D3_2 M_D3 2 2.5V

AB8 IO_L49N_D4_2 M_D4 2 2.5V

W6 IO_L62P_D5_2 M_D5 2 2.5V

Y6 IO_L62N_D6_2 M_D6 2 2.5V

Y9 IO_L48P_D7_2 M_D7 2 2.5V

B2 IO_L54P_M3RESET_3 M_DIPSW_0 3 2.5V

B1 IO_L54N_M3A11_3 M_DIPSW_1 3 2.5V

C1 IO_L52N_M3A9_3 M_DIPSW_2 3 2.5V

D2 IO_L50P_M3WE_3 M_DIPSW_3 3 2.5V

D1 IO_L50N_M3BA2_3 M_DIPSW_4 3 2.5V

E1 IO_L48N_M3BA1_3 M_DIPSW_5 3 2.5V

F2 IO_L46P_M3CLK_3 M_DIPSW_6 3 2.5V

F1 IO_L46N_M3CLKN_3 M_DIPSW_7 3 2.5V

T20 IO_L74N_DOUT_BUSY_1 M_DOUT_BUSY 1 2.5V

Y19 IO_L67P_1 M_FTDI_RESET_B 1 2.5V

A4 IO_L1N_VREF_0 M_HEADER_0 0 2.5V

A5 IO_L2N_0 M_HEADER_1 0 2.5V

B6 IO_L4P_0 M_HEADER_2 0 2.5V






C5 IO_L2P_0 M_HEADER_8 0 2.5V

C6 IO_L3N_0 M_HEADER_9 0 2.5V

28

C7 IO_L5P_0 M_HEADER_10 0 2.5V

C17 IO_L64P_SCP5_0 M_HEADER_11 0 2.5V

A11 IO_L35N_GCLK16_0 M_HEADER_12 0 2.5V

A12 IO_L36N_GCLK14_0 M_HEADER_13 0 2.5V

B12 IO_L36P_GCLK15_0 M_HEADER_14 0 2.5V





A16 IO_L63N_SCP6_0 M_HEADER_19 0 2.5V

B16 IO_L63P_SCP7_0 M_HEADER_20 0 2.5V



B18 IO_L66P_SCP1_0 M_HEADER_23 0 2.5V

A10 IO_L34N_GCLK18_0 M_HEADER_CLK_N 0 2.5V

B10 IO_L34P_GCLK19_0 M_HEADER_CLK_P 0 2.5V

B3 IO_L1P_HSWAPEN_0 M_HSWAPEN 0 2.5V

Y5 IO_L65P_INIT_B_2 M_INIT_B 2 2.5V

M2 IO_L38P_M3DQ2_3 M_LED_0 3 2.5V

N1 IO_L37N_M3DQ1_3 M_LED_1 3 2.5V

P1 IO_L36N_M3DQ9_3 M_LED_2 3 2.5V

P2 IO_L36P_M3DQ8_3 M_LED_3 3 2.5V

R1 IO_L35N_M3DQ11_3 M_LED_4 3 2.5V

T1 IO_L34N_M3UDQSN_3 M_LED_5 3 2.5V

T2 IO_L34P_M3UDQS_3 M_LED_6 3 2.5V

U1 IO_L33N_M3DQ13_3 M_LED_7 3 2.5V

V1 IO_L32N_M3DQ15_3 M_LED_8 3 2.5V

V2 IO_L32P_M3DQ14_3 M_LED_9 3 2.5V

Y18 IO_L1N_M0_CMPMISO_2 M_M0 2 2.5V

U15 IO_L13P_M1_2 M_M1 2 2.5V

AB17 IO_L3N_MOSI_CSI_B_MISO0_2 M_MOSI_CSI_B 2 2.5V

D3 IO_L81N_3 M_PUSHSW_0 3 2.5V

E3 IO_L48P_M3BA0_3 M_PUSHSW_1 3 2.5V

AB9 IO_L48N_RDWR_B_VREF_2 M_RDWR_B 2 2.5V

A2 IO_L83N_VREF_3 M_RESET_B 3 2.5V

H1 IO_L42N_GCLK24_M3LDM_3 M_RSVIO_0_N 3 2.5V

29

H2 IO_L42P_GCLK25_TRDY2_M3UDM_3 M_RSVIO_0_P 3 2.5V

3.1.1. Clock and Reset

Table 31 : Main FPGA (U1) Clock and Reset

Net Pin (U1) Destination Voltage

M_CLK_OSC J1 U11.OUT 2.5V

M_CLK_INH_B M1 U11./INH 2.5V

M_CLK_EXT0_P N4 J4 2.5V

M_CLK_EXT0_N P3 J5 2.5V

M_RESET_B A2 U12./RST 2.5V

3.1.2. User LED

Table 32 : Main FPGA (U1) User LED


M_LED_0 M2 LED1 2.5V

M_LED_1 N1 LED2 2.5V

M_LED_2 P1 LED3 2.5V

M_LED_3 P2 LED4 2.5V

M_LED_4 R1 LED5 2.5V

M_LED_5 T1 LED6 2.5V

M_LED_6 T2 LED7 2.5V

M_LED_7 U1 LED8 2.5V

M_LED_8 V1 LED9 2.5V

M_LED_9 V2 LED10 2.5V

3.1.3. User Push switch

Table 33 : Main FPGA (U1) User Push switch


M_PUSHSW_0 D3 SW3 2.5V

M_PUSHSW_1 E3 SW4 2.5V

3.1.4. User DIP switch

Table 34 : Main FPGA (U1) User DIP switch


M_DIPSW_0 B2 SW5.1 2.5V

M_DIPSW_1 B1 SW5.2 2.5V

30

M_DIPSW_2 C1 SW5.3 2.5V

M_DIPSW_3 D2 SW5.4 2.5V

M_DIPSW_4 D1 SW5.5 2.5V

M_DIPSW_5 E1 SW5.6 2.5V

M_DIPSW_6 F2 SW5.7 2.5V

M_DIPSW_7 F1 SW5.8 2.5V

3.1.5. User Header

Table 35 : Main FPGA (U1) User Header


M_HEADER_0 A4 CN3.1 2.5V


M_HEADER_2 B6 CN3.3 2.5V






M_HEADER_8 C5 CN3.11 2.5V
















M_HEADER_CLK_P B10 CN3.31 2.5V

M_HEADER_CLK_N A10 CN3.32 2.5V

31

3.1.6. USB Interface

Table 36 : Main FPGA (U1) USB Interface


FTDI_BCBUS0_RXF_B N20 U17.BCBUS0 2.5V

FTDI_BCBUS1_TXE_B P20 U17.BCBUS1 2.5V

FTDI_BCBUS2_RD_B R20 U17.BCBUS2 2.5V

FTDI_BCBUS3_WR_B U20 U17.BCBUS3 2.5V

FTDI_BCBUS4_SIWUB V18 U17.BCBUS4 2.5V

FTDI_BCBUS5 V20 U17.BCBUS5 2.5V

FTDI_BCBUS6 V19 U17.BCBUS6 2.5V

FTDI_BCBUS7_PWRSAV_B W20 U17.BCBUS7 2.5V

FTDI_BDBUS0 V21 U17.BDBUS0 2.5V

FTDI_BDBUS1 V22 U17.BDBUS1 2.5V

FTDI_BDBUS2 U22 U17.BDBUS2 2.5V

FTDI_BDBUS3 T22 U17.BDBUS3 2.5V

FTDI_BDBUS4 R22 U17.BDBUS4 2.5V

FTDI_BDBUS5 P21 U17.BDBUS5 2.5V

FTDI_BDBUS6 P22 U17.BDBUS6 2.5V

FTDI_BDBUS7 N22 U17.BDBUS7 2.5V

FTDI_PWREN_B Y20 U17.PWREN# 2.5V

FTDI_SUSPEND_B W22 U17.SUSPEND# 2.5V

M_FTDI_RESET_B Y19 R119, JP5 2.5V

3.1.7. FPGA Interconnect

Table 37 : FPGA Interconnect between Main FPGA (U1) and Controller FPGA (U2)

Net Pin (U1) Pin (U2) Voltage

MC_IC_D0 W1 D1 2.5V

MC_IC_D1 Y1 C1 2.5V

MC_IC_D2 Y2 C2 2.5V

MC_IC_D3 AA2 B3 2.5V

MC_IC_D4 AB2 A3 2.5V





32





MC_IC_D13 AB13 A10 2.5V

MC_IC_D14 AB14 A11 2.5V

MC_IC_D15 AA14 B11 2.5V

MC_IC_D16 AB15 A12 2.5V

MC_IC_D17 AB16 A13 2.5V

MC_IC_D18 AA16 B13 2.5V

MC_IC_D19 AB18 B15 2.5V

MC_IC_D20 AA18 C14 2.5V

MC_IC_D21 AB19 C15 2.5V

MC_IC_D22 AB20 D15 2.5V

MC_IC_D23 AA20 E14 2.5V

MC_IC_D24 AB21 E15 2.5V

MC_IC_D25 AA21 F15 2.5V

MC_IC_D26 AA22 G14 2.5V

MC_IC_D27 Y21 G15 2.5V

MC_IC_D28 Y22 H15 2.5V

MC_IC_D29 V3 G3 2.5V

MC_IC_D30 W3 F4 2.5V

MC_IC_D31 Y3 F3 2.5V

MC_IC_D32 W4 F5 2.5V

MC_IC_D33 Y4 E3 2.5V

MC_IC_D34 Y7 D5 2.5V

MC_IC_D35 Y8 C5 2.5V

MC_IC_D36 W9 E6 2.5V

MC_IC_D37 AA10 D7 2.5V

MC_IC_D38 AB7 C8 2.5V

MC_IC_D39 AB10 D8 2.5V

MC_IC_D40 Y10 E7 2.5V

MC_IC_D41 Y11 E8 2.5V

MC_IC_D42 W11 E9 2.5V

MC_IC_D43 W12 D10 2.5V

MC_IC_D44 Y12 C10 2.5V

33

MC_IC_D45 Y13 C11 2.5V

MC_IC_D46 Y14 D11 2.5V

MC_IC_D47 W14 C12 2.5V

MC_IC_D48 Y15 G12 2.5V

MC_IC_D49 W15 D13 2.5V

MC_IC_D50 Y16 F12 2.5V

3.1.8. Main FPGA Configuration

Table 38 : Main FPGA (U1) Configuration

Net (U1) Pin (U1) Net (U2) Pin (U2) Other Voltage

M_CCLK_R0 W17 M_CCLK_R H13 U10.SCK 2.5V

M_CSO_B AB5 M_CSO_B_R A6 U10./CS 2.5V

M_D0_DIN_MISO Y17 M_D0_DIN_MISO_R G13 U10.SO 2.5V

M_D1 V13 M_D1_R C9 2.5V

M_D2 W13 M_D2_R F11 2.5V

M_D3 AA8 M_D3_R C4 2.5V

M_D4 AB8 M_D4_R C6 2.5V

M_D5 W6 M_D5_R D3 2.5V

M_D6 Y6 M_D6_R D4 2.5V

M_D7 Y9 M_D7_R D6 2.5V

M_DONE U16 M_DONE_R F13 U12.RSTIN 2.5V

M_DOUT_BUSY T20 M_DOUT_BUSY_R G11 2.5V

M_HSWAPEN B3 R43 (Pull-down) 2.5V

M_INIT_B Y5 M_INIT_B_R E4 2.5V

M_M0 Y18 U9.1Y 2.5V

M_M0_REMOTE E2 U9.1B 2.5V

M_M1 U15 U9.2Y 2.5V

M_M1_REMOTE E1 U9.2B 2.5V

M_MOSI_CSI_B AB17 M_MOSI_CSI_B_R B14 U10.SI 2.5V

M_PROG_B AA1 M_PROG_B_R A2 SW6 2.5V

M_RDWR_B AB9 M_RDWR_B_R C7 2.5V

34

3.1.9. Reserved I/O

Table 39 : Main FPGA (U1) Reserved I/O


M_RSVIO_0_P H2 TP17 2.5V

M_RSVIO_0_N H1 TP18 2.5V

35

3.2. Controller FPGA Table 40 : Controller FPGA (U2) I/O Assignments

Pin Function Net Bank Voltage

N12 IO_L1P_CCLK_2 C_CCLK 2 2.5V

J1 IO_L41N_GCLK26_M3DQ5_3 C_CLK_EXT0_N 3 2.5V

J2 IO_L41P_GCLK27_M3DQ4_3 C_CLK_EXT0_P 3 2.5V

H1 IO_L42N_GCLK24_M3LDM_3 C_CLK_INH_B 3 2.5V

J3 IO_L43N_GCLK22_IRDY2_M3CASN_3 C_CLK_OSC 3 2.5V

R3 IO_L65N_CSO_B_2 C_CSO_B 2 2.5V

K1 IO_L40N_M3DQ7_3 C_DIPSW_0 3 2.5V

L1 IO_L39N_M3LDQSN_3 C_DIPSW_1 3 2.5V

L2 IO_L39P_M3LDQS_3 C_DIPSW_2 3 2.5V

M1 IO_L38N_M3DQ3_3 C_DIPSW_3 3 2.5V

N1 IO_L37N_M3DQ1_3 C_DIPSW_4 3 2.5V

N2 IO_L37P_M3DQ0_3 C_DIPSW_5 3 2.5V

P1 IO_L2N_3 C_DIPSW_6 3 2.5V

M3 IO_L38P_M3DQ2_3 C_DIPSW_7 3 2.5V

P15 IO_L74N_DOUT_BUSY_1 C_FTDI_RESET_B 1 2.5V

N4 IO_L63P_2 C_HEADER_0 2 2.5V

M5 IO_L64P_D8_2 C_HEADER_1 2 2.5V

N5 IO_L64N_D9_2 C_HEADER_2 2 2.5V

M6 IO_L47N_2 C_HEADER_3 2 2.5V

N6 IO_L48P_D7_2 C_HEADER_4 2 2.5V

R4 IO_L63N_2 C_HEADER_5 2 2.5V

P5 IO_L49P_D3_2 C_HEADER_6 2 2.5V

R5 IO_L49N_D4_2 C_HEADER_7 2 2.5V

R6 IO_L48N_RDWR_B_VREF_2 C_HEADER_8 2 2.5V

P7 IO_L32P_GCLK29_2 C_HEADER_9 2 2.5V

R7 IO_L32N_GCLK28_2 C_HEADER_10 2 2.5V

R8 IO_L29N_GCLK2_2 C_HEADER_11 2 2.5V

N8 IO_L29P_GCLK3_2 C_HEADER_12 2 2.5V

R9 IO_L16N_VREF_2 C_HEADER_13 2 2.5V

P9 IO_L16P_2 C_HEADER_14 2 2.5V

R10 IO_L13N_D10_2 C_HEADER_15 2 2.5V

L5 IO_L62N_D6_2 C_HEADER_16 2 2.5V

36

L6 IO_L62P_D5_2 C_HEADER_17 2 2.5V

L8 IO_L31N_GCLK30_D15_2 C_HEADER_18 2 2.5V

M9 IO_L15P_2 C_HEADER_19 2 2.5V

N9 IO_L15N_2 C_HEADER_20 2 2.5V

M10 IO_L14N_D12_2 C_HEADER_21 2 2.5V

N11 IO_L12N_D2_MISO3_2 C_HEADER_22 2 2.5V

M11 IO_L12P_D1_MISO2_2 C_HEADER_23 2 2.5V

N7 IO_L30N_GCLK0_USERCCLK_2 C_HEADER_CLK_N 2 2.5V

M8 IO_L30P_GCLK1_D13_2 C_HEADER_CLK_P 2 2.5V

B2 IO_L1P_HSWAPEN_0 C_HSWAPEN 0 2.5V

P3 IO_L65P_INIT_B_2 C_INIT_B 2 2.5V

F1 IO_L46N_M3CLKN_3 C_LED_0 3 2.5V

G2 IO_L44P_GCLK21_M3A5_3 C_LED_1 3 2.5V

G1 IO_L44N_GCLK20_M3A6_3 C_LED_2 3 2.5V

H3 IO_L42P_GCLK25_TRDY2_M3UDM_3 C_LED_3 3 2.5V

H4 IO_L47N_M3A1_3 C_LED_4 3 2.5V

H5 IO_L49N_M3A2_3 C_LED_5 3 2.5V

J5 IO_L47P_M3A0_3 C_LED_6 3 2.5V

J4 IO_L45N_M3ODT_3 C_LED_7 3 2.5V

K5 IO_L45P_M3A3_3 C_LED_8 3 2.5V

K4 IO_L43P_GCLK23_M3RASN_3 C_LED_9 3 2.5V

R12 IO_L1N_M0_CMPMISO_2 C_M0 2 2.5V

N10 IO_L13P_M1_2 C_M1 2 2.5V

P11 IO_L3P_D0_DIN_MISO_MISO1_2 C_MISO 2 2.5V

R11 IO_L3N_MOSI_CSI_B_MISO0_2 C_MOSI 2 2.5V

L3 IO_L1N_VREF_3 C_PUSHSW_0 3 2.5V

M4 IO_L1P_3 C_PUSHSW_1 3 2.5V

P2 IO_L2P_3 C_RESET_B 3 2.5V

N15 IO_L47N_LDC_M1DQ1_1 FTDI_ACBUS0_RXF_B 1 2.5V

M15 IO_L46N_FOE_B_M1DQ3_1 FTDI_ACBUS1_TXE_B 1 2.5V

¥L14 IO_L45P_A1_M1LDQS_1 FTDI_ACBUS2_RD_B 1 2.5V

L15 IO_L45N_A0_M1LDQSN_1 FTDI_ACBUS3_WR_B 1 2.5V

K15 IO_L44N_A2_M1DQ7_1 FTDI_ACBUS4_SIWUA 1 2.5V

J14 IO_L43P_GCLK5_M1DQ4_1 FTDI_ACBUS5_CLKOUT 1 2.5V

J13 IO_L36N_A8_M1BA1_1 FTDI_ACBUS6_OE_B 1 2.5V

J15 IO_L43N_GCLK4_M1DQ5_1 FTDI_ACBUS7 1 2.5V

37

M13 IO_L46P_FCS_B_M1DQ2_1 FTDI_ADBUS0 1 2.5V

L12 IO_L40N_GCLK10_M1A6_1 FTDI_ADBUS1 1 2.5V

K12 IO_L40P_GCLK11_M1A5_1 FTDI_ADBUS2 1 2.5V

K13 IO_L44P_A3_M1DQ6_1 FTDI_ADBUS3 1 2.5V

K11 IO_L38N_A4_M1CLKN_1 FTDI_ADBUS4 1 2.5V

J11 IO_L36P_A9_M1BA0_1 FTDI_ADBUS5 1 2.5V

H11 IO_L32N_A16_M1A9_1 FTDI_ADBUS6 1 2.5V

H12 IO_L34P_A13_M1WE_1 FTDI_ADBUS7 1 2.5V

P14 IO_L74P_AWAKE_1 FTDI_PWREN_B 1 2.5V

N14 IO_L47P_FWE_B_M1DQ0_1 FTDI_SUSPEND_B 1 2.5V

D1 IO_L54N_M3A11_3 MC_IC_D0 3 2.5V

C1 IO_L83N_VREF_3 MC_IC_D1 3 2.5V

C2 IO_L83P_3 MC_IC_D2 3 2.5V

B3 IO_L2P_0 MC_IC_D3 0 2.5V

A3 IO_L2N_0 MC_IC_D4 0 2.5V


B5 IO_L6P_0 MC_IC_D6 0 2.5V


B7 IO_L35P_GCLK17_0 MC_IC_D8 0 2.5V

A7 IO_L35N_GCLK16_0 MC_IC_D9 0 2.5V



B9 IO_L37P_GCLK13_0 MC_IC_D12 0 2.5V

A10 IO_L62N_VREF_0 MC_IC_D13 0 2.5V

A11 IO_L63N_SCP6_0 MC_IC_D14 0 2.5V

B11 IO_L63P_SCP7_0 MC_IC_D15 0 2.5V



B13 IO_L65P_SCP3_0 MC_IC_D18 0 2.5V

B15 IO_L1N_A24_VREF_1 MC_IC_D19 1 2.5V

C14 IO_L33P_A15_M1A10_1 MC_IC_D20 1 2.5V

C15 IO_L33N_A14_M1A4_1 MC_IC_D21 1 2.5V

D15 IO_L35N_A10_M1A2_1 MC_IC_D22 1 2.5V

E14 IO_L37P_A7_M1A0_1 MC_IC_D23 1 2.5V

E15 IO_L37N_A6_M1A1_1 MC_IC_D24 1 2.5V

F15 IO_L39N_M1ODT_1 MC_IC_D25 1 2.5V

38

G14 IO_L41P_GCLK9_IRDY1_M1RASN_1 MC_IC_D26 1 2.5V

G15 IO_L41N_GCLK8_M1CASN_1 MC_IC_D27 1 2.5V

H15 IO_L42N_GCLK6_TRDY1_M1LDM_1 MC_IC_D28 1 2.5V

G3 IO_L48N_M3BA1_3 MC_IC_D29 3 2.5V

F4 IO_L50N_M3BA2_3 MC_IC_D30 3 2.5V

F3 IO_L46P_M3CLK_3 MC_IC_D31 3 2.5V

F5 IO_L50P_M3WE_3 MC_IC_D32 3 2.5V

E3 IO_L53N_M3A12_3 MC_IC_D33 3 2.5V

D5 IO_L3P_0 MC_IC_D34 0 2.5V

C5 IO_L3N_0 MC_IC_D35 0 2.5V

E6 IO_L5P_0 MC_IC_D36 0 2.5V

D7 IO_L7P_0 MC_IC_D37 0 2.5V

C8 IO_L36P_GCLK15_0 MC_IC_D38 0 2.5V

D8 IO_L34N_GCLK18_0 MC_IC_D39 0 2.5V

E7 IO_L34P_GCLK19_0 MC_IC_D40 0 2.5V

E8 IO_L38N_VREF_0 MC_IC_D41 0 2.5V

E9 IO_L40N_0 MC_IC_D42 0 2.5V

D10 IO_L39P_0 MC_IC_D43 0 2.5V

C10 IO_L62P_0 MC_IC_D44 0 2.5V

C11 IO_L64N_SCP4_0 MC_IC_D45 0 2.5V

D11 IO_L64P_SCP5_0 MC_IC_D46 0 2.5V

C12 IO_L66P_SCP1_0 MC_IC_D47 0 2.5V

G12 IO_L30N_A20_M1A11_1 MC_IC_D48 1 2.5V

D13 IO_L35P_A11_M1A7_1 MC_IC_D49 1 2.5V

F12 IO_L31N_A18_M1A12_1 MC_IC_D50 1 2.5V

H13 IO_L42P_GCLK7_M1UDM_1 M_CCLK_R 1 2.5V

A6 IO_L33N_0 M_CSO_B_R 0 2.5V

G13 IO_L34N_A12_M1BA2_1 M_D0_DIN_MISO_R 1 2.5V

C9 IO_L39N_0 M_D1_R 0 2.5V

F11 IO_L31P_A19_M1CKE_1 M_D2_R 1 2.5V

C4 IO_L4P_0 M_D3_R 0 2.5V

C6 IO_L33P_0 M_D4_R 0 2.5V

D3 IO_L54P_M3RESET_3 M_D5_R 3 2.5V

D4 IO_L53P_M3CKE_3 M_D6_R 3 2.5V

D6 IO_L5N_0 M_D7_R 0 2.5V

F13 IO_L39P_M1A3_1 M_DONE_R 1 2.5V

39

G11 IO_L30P_A21_M1RESET_1 M_DOUT_BUSY_R 1 2.5V

E4 IO_L51N_M3A4_3 M_INIT_B_R 3 2.5V

E2 IO_L52P_M3A8_3 M_M0_REMOTE 3 2.5V

E1 IO_L52N_M3A9_3 M_M1_REMOTE 3 2.5V

B14 IO_L1P_A25_1 M_MOSI_CSI_B_R 1 2.5V

A2 IO_L1N_VREF_0 M_PROG_B_R 0 2.5V

C7 IO_L7N_0 M_RDWR_B_R 0 2.5V

3.2.1. Clock and Reset

Table 41 : Controller FPGA (U2) Clock and Reset


C_CLK_OSC J3 U14.OUT 2.5V

C_CLK_INH_B H1 U14./INH 2.5V

C_CLK_EXT0_P J2 J6 2.5V

C_CLK_EXT0_N J1 J7 2.5V

C_RESET_B P2 U15./RST 2.5V

3.2.2. User LED

Table 42 : Controller FPGA (U2) User LED


C_LED_0 F1 LED11 2.5V

C_LED_1 G2 LED12 2.5V

C_LED_2 G1 LED13 2.5V

C_LED_3 H3 LED14 2.5V



C_LED_6 J5 LED17 2.5V

C_LED_7 J4 LED18 2.5V

C_LED_8 K5 LED19 2.5V

C_LED_9 K4 LED20 2.5V

3.2.3. User Push switch

Table 43 : Controller FPGA (U2) User Push switch


C_PUSHSW_0 L3 SW8 2.5V

C_PUSHSW_1 M4 SW9 2.5V

40

3.2.4. User DIP switch

Table 44 : Controller FPGA (U2) User DIP switch


C_DIPSW_0 K1 SW10.1 2.5V

C_DIPSW_1 L1 SW10.2 2.5V

C_DIPSW_2 L2 SW10.3 2.5V

C_DIPSW_3 M1 SW10.4 2.5V

C_DIPSW_4 N1 SW10.5 2.5V

C_DIPSW_5 N2 SW10.6 2.5V

C_DIPSW_6 P1 SW10.7 2.5V

C_DIPSW_7 M3 SW10.8 2.5V

3.2.5. User Header

Table 45 : Controller FPGA (U2) User Header


C_HEADER_0 N4 CN5.1 2.5V

C_HEADER_1 M5 CN5.2 2.5V




C_HEADER_5 R4 CN5.6 2.5V

C_HEADER_6 P5 CN5.7 2.5V










C_HEADER_16 L5 CN5.21 2.5V




41





C_HEADER_CLK_P M8 CN5.31 2.5V

C_HEADER_CLK_N N7 CN5.32 2.5V

3.2.6. USB Interface

Table 46 : Controller FPGA (U2) USB Interface


FTDI_ACBUS0_RXF_B N15 U17.ACBUS0 2.5V

FTDI_ACBUS1_TXE_B M15 U17.ACBUS1 2.5V

FTDI_ACBUS2_RD_B ¥L14 U17.ACBUS2 2.5V

FTDI_ACBUS3_WR_B L15 U17.ACBUS3 2.5V

FTDI_ACBUS4_SIWUA K15 U17.ACBUS4 2.5V

FTDI_ACBUS5_CLKOUT J14 U17.ACBUS5 2.5V

FTDI_ACBUS6_OE_B J13 U17.ACBUS6 2.5V

FTDI_ACBUS7 J15 U17.ACBUS7 2.5V

FTDI_ADBUS0 M13 U17.ADBUS0 2.5V

FTDI_ADBUS1 L12 U17.ADBUS1 2.5V

FTDI_ADBUS2 K12 U17.ADBUS2 2.5V



FTDI_ADBUS5 J11 U17.ADBUS5 2.5V

FTDI_ADBUS6 H11 U17.ADBUS6 2.5V

FTDI_ADBUS7 H12 U17.ADBUS7 2.5V

FTDI_PWREN_B P14 U17.PWREN# 2.5V

FTDI_SUSPEND_B N14 U17.SUSPEND# 2.5V

C_FTDI_RESET_B P15 R120, JP6 2.5V

3.2.7. FPGA Interconnect

See Table 37.

3.2.8. Main FPGA Configuration

See Table 38.

42

3.2.9. Controller FPGA Configuration

Table 47 : Controller FPGA (U2) Configuration


C_CCLK N12 U13.SCK 2.5V

C_CSO_B R3 U13./CS 2.5V

C_DONE R14 U15.RSTIN 2.5V

C_HSWAPEN B2 R77 (Pull-down) 2.5V

C_INIT_B P3 LED26 2.5V

C_M0 R12 R93 (Pull-up) 2.5V

C_M1 N10 R94 (Pull-down) 2.5V

C_MISO P11 U13.SO 2.5V

C_MOSI R11 U13.SI 2.5V

C_PROG_B R2 SW11 2.5V

43

4. Board Design

4.1. Board Revision The board revision is printed as “SAKURA-G-R1”, which means revision “R1” of SAKURA-G.

Board Revision

Figure 15 : Revision Mark

44

4.2. Schematic

Figure 16 : Schematic – Power 1 (VCC3V3)

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

D D

C C

B B

A A

Title

Number RevisionSize

A3

Date: 2013/07/05 Sheet ofFile: C:\Users\..\Sheet_Power_1.SchDoc Drawn By:

GND

VIN

GND

0.1uC2

GND

POWER

10m

R1

DNP

JP1

220uC1

12

CN1

B2P-VH(LF)(SN)ON-OFF-ON

EXT_VCC5V

i Net Class

ClassName: POWER

GND

VINII

GND

0.1uC2

GND

POWER

10m

R1

DNP

JP1

220uC1

12

CN1

B2P-VH(LF)(SN)ON-OFF-ON

EXT_VCC5VPOWER_VIN

TP1

VBUS

1

32

SW1

MS-13AAP1 TP2

GND

LED21LED

560R3

VCC3V3

66.5k1%

R2

TP4

GND

TP3

10uC3

GND GND

D1MMBD1501A

GND

Soft StartPD 5.1W (Max.) @VIN=5.0V

Guard Ring

SET

2

NC

1

VCONTROL4

OUT 3IN5

OUT 6

U3 LT3083

GND GND

390uC6

10uC5

VCC3V3

0.1uC4

Power 1 (VCC3V3)

DNP : Do Not Populate

EXT MAIN5V (4.75~12V)

45

Figure 17 : Schematic – Power 2 (VCC1V2C, VCC2V5, VCC2V8)

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

D D

C C

B B

A A

Title

Number RevisionSize

A3


Power 2 (VCC1V2C, VCC2V5, VCC2V8)

GND4

VIN1

SHDN3

VOUT 8

VIN2

PWRGD 5CDELAY 6ADJ 7

EP9

U4

MCP1726-ADJ

VCC3V3

4.7uC7

GND

VCC3V3

GND

1000pDNP

C8

GND

39k1%

R5

75k1%

R4

GND

4.7uC9

GND

VCC1V2C

GND4

VIN1

SHDN3

VOUT 8

VIN2


EP9

U5

MCP1726-ADJ

VCC3V3

4.7uC10

GND

VCC3V3

GND GND

10k1%

R7

51k1%

R6

GND

4.7uC12

GND

VCC2V5

GND4

VIN1

SHDN3

VOUT 8

VIN2


EP9

U6

MCP1726-ADJ

VCC3V3

4.7uC13

GND

VCC3V3

GND GND

27k1%

R9

160k1%

R8

GND

4.7uC15

GND

VCC2V8

1000pDNP

C11

1000pDNP

C14

TP6

TP5

TP8

TP7

TP10

TP9

GND

GND

GND

46

Figure 18 : Schematic – Power 3 (VCC1V2M)

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

D D

C C

B B

A A

Title

Number RevisionSize

A3


Power 3 (VCC1V2M)

VCC3V3

100uC20

GND GNDGND GND GND

VCC1V2M

1kR11

20kVR1

10k1%

R10

GNDGND

Soft Start

Load(Min.) = 1mA

JP2

5

1

234

J1SMA

5

1

234

J2SMA

1

R12

GNDGND

0R13

0R14

TP13

TP14

GND

POWER_VCC1V2M_VOUT

PD 0.6W (Max.)

Guard Ring

10uC19

SET

2

NC

1

VCONTROL4

OUT 3IN5

OUT 6

U7 LT3083

10uC16

0.1uC17

390uC21

TP11

GND

TP12

GND

10uC18

0.5~1.5V

47

Figure 19 : Schematic – Amplifier

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

D D

C C

B B

A A

Title

Number RevisionSize

A3

Date: 2013/06/15 Sheet ofFile: C:\Users\..\Sheet_Amp.SchDoc Drawn By:

Amplifier

61.91%

R17

1000p

C28

0.1u

C29

8061%

R20

4021%

R19

4021%

R18

10uC31

VIN

10uC22

BLM18PG221SN1L1

1uC23

BLM18PG221SN1L2

0.1uC25

1R15

100uC24

AVCC

VCC1V2M

GND GND

GND

AVCC

3571%

R22

40.21%

R21

49.91%

R23

1000pC32

0.1uC33

1000p

C35

0.1u

C36 5

1

2 3 4

J3 SMA

GND

GND GND GND

GND

AVCC

AVCC

0.1uC27

10uC26

GND GND GND

GAIN = +10V/V (20dB)

0

R16

Close to shunt resistor

BW (-3dB) = 360MHz

2

36

8

1

U8A

AD8000

+VS7 -VS 4

NC5 EPAD 9

U8B

AD8000

iNet ClassClassName: S50


10u

C30

10uC34

10u

C37

48

Figure 20 : Schematic – Main FPGA Configuration

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

D D

C C

B B

A A

Title

Number RevisionSize

A3

Date: 2013/06/15 Sheet ofFile: C:\Users\..\Sheet_Main_FPGA_Config.SchDocDrawn By:

Main FPGA Configuration

M_DONE

M_PROG_BM_INIT_B GND

JTAG CONFIG

M_JTAG_TMSM_JTAG_TCKM_JTAG_TDOM_JTAG_TDI

10kR33

10kR34

10kR36

1 23 45 67 89 1011 1213 14

CN2

Xilinx JTAG

10kDNP

R35

0.1uC39

GND

M_MOSI_CSI_BM_CSO_B

M_CCLK

M_M0

M_M1

5678

43211

23

4

SW2

DIPSW-4

M_M1_REMOTE

M_M0_REMOTE

10kR30

10kR29

10kR28

GNDGNDGND

VCC2V5

330R27

GND

M_CLK_INH_B

GND

LED22LED

LED23LED

LED24LED

INIT/ERRORCONF DONE RESET

330R25

330R26

27R24

VCC2V5 VCC2V5

M_M0_DIPSWM_M1_DIPSW

0.1uC40

GND

100

R42

1uDNP

C41

1kR41

VCC2V8 VCC2V8 VCC2V8

M_DONE

M_JTAG_TMS

M_JTAG_TCK

M_JTAG_TDOM_JTAG_TDI

M_PROG_B

330R38

1kR39

GND

VCC2V5VCC2V5

0R40

GND

0R37

VCC2V5

330R32

330R31

0.1uC38

VCC2V5VCC2V5

VCC2V5

M_MODE_REMOTE

M_MODE_REMOTE

GNDGND GND

M_M0_DIPSW

M_M1_DIPSW

GND

XC6SLX75 19,719,712 bitXC6SLX45 11,939,296 bit

XC6SLX100 26,691,232 bit

TCKD14

TDIE18

TMSE16 TDOE14

VFSU19

RFUSET16

SUSPENDW18

CMPCS_B_2T15

DONE_2U16

PROGRAM_B_2AA1

NC(LX45)NC(LX45)

U1G

XC6SLX75-2CSG484C

A/B1

1A2

1B3 1Y 4

2A5

2B6 2Y 7

GND8

3Y 9

3B10 3A11

4Y 12

4B13 4A14

OE15 VCC 16U9

74LVC157APW,118

VCC2V5

M_D0_DIN_MISO


M[1:0]=01 (Master SPI)

SI1 SCK2

RESET3 CS4

WP5

VCC 6

GND 7

SO 8

U10

AT45DB321D

49

Figure 21 : Schematic – Main FPGA I/O (Bank 0, 1)

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

D D

C C

B B

A A

Title

Number RevisionSize

A3

Date: 2013/06/15 Sheet ofFile: C:\Users\..\Sheet_Main_FPGA_IO_1.SchDocDrawn By:

Main FPGA IO 1 (BANK0, 1)

1kR43

GND

M_HSWAPEN

M_HEADER_3M_HEADER_2

M_HEADER_1

M_HEADER_0

M_HEADER_4M_HEADER_5M_HEADER_6

M_HEADER_7

M_HEADER_8

M_HEADER_9

M_HEADER_10

M_HEADER_11

M_HEADER_12


M_HEADER_15


M_HEADER_18


M_HEADER_21


M_HSWAPEN

M_DOUT_BUSY

M_HEADER_CLK_PM_HEADER_CLK_N

BANK 0

NC(LX45)NC(LX45)NC(LX45)

NC(LX45)NC(LX45)

NC(LX45)NC(LX45)

NC(LX45)NC(LX45)

NC(LX45)

IO_L1P_HSWAPEN_0B3

IO_L1N_VREF_0A4

IO_L2P_0C5

IO_L2N_0A5

IO_L3P_0D6

IO_L3N_0C6

IO_L4P_0B6

IO_L4N_0A6

IO_L5P_0C7

IO_L5N_0A7

IO_L6P_0B8

IO_L6N_0A8

IO_L7P_0D7

IO_L7N_0C8

IO_L8P_0C9

IO_L8N_VREF_0A9

IO_L15P_0F9

IO_L15N_0E8

IO_L16P_0H10

IO_L16N_0G9

IO_L32P_0D9

IO_L32N_0D8

IO_L33P_0D10

IO_L33N_0C10

IO_L34P_GCLK19_0B10

IO_L34N_GCLK18_0A10

IO_L35P_GCLK17_0C11

IO_L35N_GCLK16_0A11

IO_L36P_GCLK15_0B12

IO_L36N_GCLK14_0A12

IO_L37P_GCLK13_0D11

IO_L37N_GCLK12_0C12

IO_L38P_0F10

IO_L38N_VREF_0E10

IO_L46P_0D15

IO_L46N_0C14

IO_L47P_0D13

IO_L47N_0D12

IO_L48P_0C13

IO_L48N_0A13

IO_L49P_0F12

IO_L49N_0E12

IO_L50P_0B14

IO_L50N_0A14

IO_L51P_0H11

IO_L51N_0G11

IO_L62P_0C15

IO_L62N_VREF_0A15

IO_L63P_SCP7_0B16

IO_L63N_SCP6_0A16

IO_L64P_SCP5_0C17

IO_L64N_SCP4_0A17

IO_L65P_SCP3_0D17

IO_L65N_SCP2_0C16

IO_L66P_SCP1_0B18

IO_L66N_SCP0_0A18

U1A

XC6SLX75-2CSG484C

BANK 1IO_L1P_A25_1F15

IO_L1N_A24_VREF_1F16

IO_L9P_1F13

IO_L9N_1F14

IO_L10P_1G15

IO_L10N_1G16

IO_L11P_1D19

IO_L11N_1D20

IO_L12P_1C18

IO_L12N_1C19

IO_L13P_1G17

IO_L13N_1G19

IO_L14P_1B20

IO_L14N_1A21

IO_L15P_1F17

IO_L15N_1F18

IO_L16P_1A19

IO_L16N_1A20

IO_L17P_1H17

IO_L17N_1H18

IO_L18P_1F19

IO_L18N_1F20

IO_L19P_1H12

IO_L19N_1G13

IO_L20P_1J16

IO_L20N_1H16

IO_L21P_1H13

IO_L21N_1H14

IO_L28P_1L15

IO_L28N_VREF_1K16

IO_L29P_A23_M1A13_1F21

IO_L29N_A22_M1A14_1F22

IO_L30P_A21_M1RESET_1H19

IO_L30N_A20_M1A11_1H20

IO_L31P_A19_M1CKE_1E20

IO_L31N_A18_M1A12_1E22

IO_L32P_A17_M1A8_1G20

IO_L32N_A16_M1A9_1G22

IO_L33P_A15_M1A10_1D21

IO_L33N_A14_M1A4_1D22

IO_L34P_A13_M1WE_1H21

IO_L34N_A12_M1BA2_1H22

IO_L35P_A11_M1A7_1C20

IO_L35N_A10_M1A2_1C22

IO_L36P_A9_M1BA0_1K18

IO_L36N_A8_M1BA1_1K19

IO_L37P_A7_M1A0_1B21

IO_L37N_A6_M1A1_1B22

IO_L38P_A5_M1CLK_1J17

IO_L38N_A4_M1CLKN_1J19

IO_L39P_M1A3_1J21

IO_L39N_M1ODT_1J22

IO_L40P_GCLK11_M1A5_1L17

IO_L40N_GCLK10_M1A6_1K17

IO_L41P_GCLK9_IRDY1_M1RASN_1M18

IO_L41N_GCLK8_M1CASN_1M19

U1B

XC6SLX75-2CSG484C

BANK 1IO_L42P_GCLK7_M1UDM_1L19

IO_L42N_GCLK6_TRDY1_M1LDM_1K20

IO_L43P_GCLK5_M1DQ4_1L20

IO_L43N_GCLK4_M1DQ5_1L22

IO_L44P_A3_M1DQ6_1K21

IO_L44N_A2_M1DQ7_1K22

IO_L45P_A1_M1LDQS_1M21

IO_L45N_A0_M1LDQSN_1M22

IO_L46P_FCS_B_M1DQ2_1N19

IO_L46N_FOE_B_M1DQ3_1M20

IO_L47P_FWE_B_M1DQ0_1N20

IO_L47N_LDC_M1DQ1_1N22

IO_L48P_HDC_M1DQ8_1P21

IO_L48N_M1DQ9_1P22

IO_L49P_M1DQ10_1R20

IO_L49N_M1DQ11_1R22

IO_L50P_M1UDQS_1T21

IO_L50N_M1UDQSN_1T22

IO_L51P_M1DQ12_1U20

IO_L51N_M1DQ13_1U22

IO_L52P_M1DQ14_1V21

IO_L52N_M1DQ15_1V22

IO_L53P_1W20

IO_L53N_VREF_1W22

IO_L58P_1M16

IO_L58N_1M17

IO_L59P_1Y21

IO_L59N_1Y22

IO_L60P_1N15

IO_L60N_1N16

IO_L61P_1AA20

IO_L61N_1AB21

IO_L62P_1P15

IO_L62N_1P16

IO_L63P_1AA21

IO_L63N_1AA22

IO_L64P_1P19

IO_L64N_1P20

IO_L65P_1AB19

IO_L65N_1AB20

IO_L66P_1P17

IO_L66N_1P18

IO_L67P_1Y19

IO_L67N_1Y20

IO_L68P_1R15

IO_L68N_1R16

IO_L70P_1R17

IO_L70N_1R19

IO_L71P_1V19

IO_L71N_1V20

IO_L72P_1T17

IO_L72N_1T18

IO_L73P_1V17

IO_L73N_1V18

IO_L74P_AWAKE_1T19

IO_L74N_DOUT_BUSY_1T20

U1C

XC6SLX75-2CSG484C

FTDI_BDBUS0_D0FTDI_BDBUS1_D1

FTDI_BDBUS2_D2

FTDI_BDBUS3_D3

FTDI_BDBUS4_D4

FTDI_BDBUS5_D5FTDI_BDBUS6_D6

FTDI_BDBUS7_D7FTDI_BCBUS0_RXF_B

FTDI_BCBUS1_TXE_B

FTDI_BCBUS2_RD_B

FTDI_BCBUS3_WR_B

FTDI_BCBUS4_SIWUB

FTDI_BCBUS5FTDI_BCBUS6

FTDI_BCBUS7_PWRSAV_B

M_FTDI_RESET_BFTDI_PWREN_B

FTDI_SUSPEND_B

MC_IC_D25MC_IC_D26

MC_IC_D27MC_IC_D28

MC_IC_D21MC_IC_D22

MC_IC_D23MC_IC_D24

50

Figure 22 : Schematic – Main FPGA I/O (Bank 2, 3)

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

D D

C C

B B

A A

Title

Number RevisionSize

A3

Date: 2013/06/15 Sheet ofFile: C:\Users\..\Sheet_Main_FPGA_IO_2.SchDocDrawn By:

Main FPGA IO (BANK2, 3)

M_CCLK

M_D0_DIN_MISO

M_INIT_B

M_MOSI_CSI_B

M_CSO_B

M_M0

M_M1

M_RDWR_B

M_D1M_D2

M_D3M_D4M_D5M_D6

M_D7

0R46 M_CCLK_R0

100 1%DNP

R44

GND

Close to FPGA

100 1%DNP

R45

VCC2V5

1kR47

VCC2V5

BANK 2IO_L1P_CCLK_2W17

IO_L1N_M0_CMPMISO_2Y18

IO_L2P_CMPCLK_2AA18

IO_L2N_CMPMOSI_2AB18

IO_L3P_D0_DIN_MISO_MISO1_2Y17

IO_L3N_MOSI_CSI_B_MISO0_2AB17

IO_L4P_2AA16

IO_L4N_VREF_2AB16

IO_L5P_2Y15

IO_L5N_2AB15

IO_L12P_D1_MISO2_2V13

IO_L12N_D2_MISO3_2W13

IO_L13P_M1_2U15

IO_L13N_D10_2V15

IO_L14P_D11_2W15

IO_L14N_D12_2Y16

IO_L15P_2AA14

IO_L15N_2AB14

IO_L16P_2W14

IO_L16N_VREF_2Y14

IO_L20P_2T14

IO_L20N_2U14

IO_L29P_GCLK3_2W11

IO_L29N_GCLK2_2Y10

IO_L30P_GCLK1_D13_2AA12

IO_L30N_GCLK0_USERCCLK_2AB12

IO_L31P_GCLK31_D14_2Y11

IO_L31N_GCLK30_D15_2AB11

IO_L32P_GCLK29_2AA10

IO_L32N_GCLK28_2AB10

IO_L33P_2R13

IO_L33N_2U13

IO_L34P_2T12

IO_L34N_2U12

IO_L41P_2Y13

IO_L41N_VREF_2AB13

IO_L42P_2W12

IO_L42N_2Y12

IO_L47P_2W9

IO_L47N_2Y8

IO_L48P_D7_2Y9

IO_L48N_RDWR_B_VREF_2AB9

IO_L49P_D3_2AA8

IO_L49N_D4_2AB8

IO_L62P_D5_2W6

IO_L62N_D6_2Y6

IO_L63P_2Y7

IO_L63N_2AB7

IO_L64P_D8_2AA6

IO_L64N_D9_2AB6

IO_L65P_INIT_B_2Y5

IO_L65N_CSO_B_2AB5

NC(LX45)NC(LX45)NC(LX45)NC(LX45)

U1D

XC6SLX75-2CSG484C

BANK 3IO_L1P_3AA2

IO_L1N_VREF_3AB2

IO_L2P_3Y2

IO_L2N_3Y1

IO_L7P_3W4

IO_L7N_3Y4

IO_L8P_3Y3

IO_L8N_3AB3

IO_L9P_3W3

IO_L9N_3W1

IO_L10P_3U8

IO_L10N_3T7

IO_L11P_3T8

IO_L11N_3R7

IO_L12P_3AA4

IO_L12N_3AB4

IO_L13P_3U6

IO_L13N_3V5

IO_L18P_3U4

IO_L18N_3V3

IO_L19P_3R9

IO_L19N_3R8

IO_L20P_3T6

IO_L20N_3T5

IO_L21P_3P4

IO_L21N_3R4

IO_L22P_3P6

IO_L22N_3P5

IO_L23P_3P8

IO_L23N_3P7

IO_L24P_3N7

IO_L24N_3N6

IO_L25P_3M8

IO_L25N_3M7

IO_L26P_3T4

IO_L26N_3T3

IO_L31P_3M6

IO_L31N_VREF_3L6

IO_L32P_M3DQ14_3V2

IO_L32N_M3DQ15_3V1

IO_L33P_M3DQ12_3U3

IO_L33N_M3DQ13_3U1

IO_L34P_M3UDQS_3T2

IO_L34N_M3UDQSN_3T1

IO_L35P_M3DQ10_3R3

IO_L35N_M3DQ11_3R1

IO_L36P_M3DQ8_3P2

IO_L36N_M3DQ9_3P1

IO_L37P_M3DQ0_3N3

IO_L37N_M3DQ1_3N1

IO_L38P_M3DQ2_3M2

IO_L38N_M3DQ3_3M1

IO_L39P_M3LDQS_3L3

IO_L39N_M3LDQSN_3L1

NC(LX45)NC(LX45)NC(LX45)NC(LX45)

U1E

XC6SLX75-2CSG484C

BANK 3IO_L40P_M3DQ6_3K2

IO_L40N_M3DQ7_3K1

IO_L41P_GCLK27_M3DQ4_3J3

IO_L41N_GCLK26_M3DQ5_3J1

IO_L42P_GCLK25_TRDY2_M3UDM_3H2

IO_L42N_GCLK24_M3LDM_3H1

IO_L43P_GCLK23_M3RASN_3N4

IO_L43N_GCLK22_IRDY2_M3CASN_3P3

IO_L44P_GCLK21_M3A5_3G3

IO_L44N_GCLK20_M3A6_3G1

IO_L45P_M3A3_3M4

IO_L45N_M3ODT_3M3

IO_L46P_M3CLK_3F2

IO_L46N_M3CLKN_3F1

IO_L47P_M3A0_3M5

IO_L47N_M3A1_3L4

IO_L48P_M3BA0_3E3

IO_L48N_M3BA1_3E1

IO_L49P_M3A7_3K4

IO_L49N_M3A2_3K3

IO_L50P_M3WE_3D2

IO_L50N_M3BA2_3D1

IO_L51P_M3A10_3K6

IO_L51N_M3A4_3K5

IO_L52P_M3A8_3C3

IO_L52N_M3A9_3C1

IO_L53P_M3CKE_3J6

IO_L53N_M3A12_3J4

IO_L54P_M3RESET_3B2

IO_L54N_M3A11_3B1

IO_L55P_M3A13_3H4

IO_L55N_M3A14_3H3

IO_L57P_3H6

IO_L57N_VREF_3H5

IO_L58P_3H8

IO_L58N_3J7

IO_L59P_3K8

IO_L59N_3K7

IO_L60P_3E4

IO_L60N_3F3

IO_L73P_3G8

IO_L73N_3G7

IO_L74P_3G6

IO_L74N_3G4

IO_L75P_3F5

IO_L75N_3E5

IO_L80P_3F8

IO_L80N_3F7

IO_L81P_3C4

IO_L81N_3D3

IO_L82P_3E6

IO_L82N_3D5

IO_L83P_3A3

IO_L83N_VREF_3A2

U1F

XC6SLX75-2CSG484C

NC R11

NC T11

NC V11

NC W10

NC T10

NCU10

NCU9

NCV9

NCV7

NCW8

U1J

XC6SLX75-2CSG484C

M_DIPSW_1

M_LED_0M_LED_1

M_LED_2M_LED_3M_LED_4

M_PUSHSW_1

M_LED_5M_LED_6M_LED_7

M_LED_8M_LED_9

M_DIPSW_2

M_DIPSW_3M_DIPSW_4

M_DIPSW_5

M_DIPSW_6M_DIPSW_7

M_DIPSW_0

M_PUSHSW_0

M_CLK_OSC

M_CLK_INH_B

M_RESET_B

M_CLK_EXT0_NM_CLK_EXT0_P

M_RSVIO_0_PM_RSVIO_0_N

MC_IC_D1

MC_IC_D0

MC_IC_D2

MC_IC_D3MC_IC_D4

MC_IC_D5

MC_IC_D6MC_IC_D7

MC_IC_D8MC_IC_D9

MC_IC_D10

MC_IC_D11MC_IC_D12

MC_IC_D13

MC_IC_D14MC_IC_D15

MC_IC_D16

MC_IC_D17MC_IC_D18

MC_IC_D19MC_IC_D20

MC_IC_D29

MC_IC_D30

MC_IC_D31

MC_IC_D32MC_IC_D33

MC_IC_D34

MC_IC_D35MC_IC_D36

MC_IC_D37

MC_IC_D40

MC_IC_D41

MC_IC_D42

MC_IC_D43MC_IC_D44

MC_IC_D45

MC_IC_D46MC_IC_D47

MC_IC_D48

MC_IC_D49MC_IC_D50

MC_IC_D38

MC_IC_D39



51

Figure 23 : Schematic – Main FPGA Power

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

D D

C C

B B

A A

Title

Number RevisionSize

A3

Date: 2013/06/15 Sheet ofFile: C:\Users\..\Sheet_Main_FPGA_Power.SchDocDrawn By:

Main FPGA PowerGND GND

VCC2V5VCC2V5

VCC1V2M

4.7uC56

GNDGND

100uC55

0.47uC57

GND

0.47uC58

GND

4.7uC60

GNDGND

100uC59

0.47uC61

GND

0.47uC62

GND

0.47uC63

GND

4.7uC66

GNDGND

100uC65

0.47uC67

GND

0.47uC68

GND

0.47uC74

GND

0.47uC64

GND

4.7uC70

GNDGND

100uC69

0.47uC71

GND

0.47uC72

GND

0.47uC73

GND

VCC2V5

VCC2V5

4.7uDNP

C51

GND GND

100uDNP

C490.47uDNP

C54

GND

0.47uDNP

C53

GND

0.47uDNP

C52

GND

4.7uDNP

C50

GND

4.7uC44

GND GND

100uC42

0.47uC48

GND

0.47uC47

GND

0.47uC46

GND

0.47uC45

GND

4.7uC43

GNDVCC2V5

VBATTU17

VCCAUXD16

VCCAUXF11

VCCAUXG12

VCCAUXH9

VCCAUXH15

VCCAUXK15

VCCAUXL8

VCCAUXM15

VCCAUXN8

VCCAUXR6

VCCAUXR10

VCCAUXR12

VCCAUXU11

VCCAUXV6

VCCINTJ8

VCCINTJ10

VCCINTJ12

VCCINTJ14

VCCINTK9

VCCINTK11

VCCINTK13

VCCINTL10

VCCINTL12

VCCINTL14

VCCINTM9

VCCINTM11

VCCINTM13

VCCINTN10

VCCINTN12

VCCINTN14

VCCINTP9

VCCINTP11

VCCINTP13

VCCINTR14

VCCO_0 B4

VCCO_0 B7

VCCO_0 B11

VCCO_0 B15

VCCO_0 E9

VCCO_0 E13

VCCO_0 E17

VCCO_0 G10

VCCO_1 B19

VCCO_1 C21

VCCO_1 E19

VCCO_1 G14

VCCO_1 G21

VCCO_1 J18

VCCO_1 L16

VCCO_1 L21

VCCO_1 N18

VCCO_1 R21

VCCO_1 U18

VCCO_1 W21

VCCO_1 AA19

VCCO_2 T9

VCCO_2 T13

VCCO_2 V8

VCCO_2 V12

VCCO_2 V16

VCCO_2 AA7

VCCO_2 AA11

VCCO_2 AA15

VCCO_3 C2

VCCO_3 F4

VCCO_3 F6

VCCO_3 G2

VCCO_3 J5

VCCO_3 L2

VCCO_3 L7

VCCO_3 N5

VCCO_3 R2

VCCO_3 U5

VCCO_3 W2

VCCO_3 W5

VCCO_3 AA3

NC(LX45)U1H

XC6SLX75-2CSG484C

GND A1

GND A22

GND B5

GND B9

GND B13

GND B17

GND D4

GND D18

GND E2

GND E7

GND E11

GND E15

GND E21

GND G5

GND G18

GND H7

GND J2

GND J9

GND J11

GND J13

GND J15

GND J20

GND K10

GND K12

GND K14

GND L5

GND L9

GND L11

GND L13

GND L18

GNDM10

GNDM12

GNDM14

GNDN2

GNDN9

GNDN11

GNDN13

GNDN17

GNDN21

GNDP10

GNDP12

GNDP14

GNDR5

GNDR18

GNDU2

GNDU7

GNDU21

GNDV4

GNDV10

GNDV14

GNDW7

GNDW16

GNDW19

GNDAA5

GNDAA9

GNDAA13

GNDAA17

GNDAB1

GNDAB22

U1I

XC6SLX75-2CSG484C

DNP for SCA

52

Figure 24 : Schematic – Main FPGA Header

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

D D

C C

B B

A A

Title

Number RevisionSize

A3

Date: 2013/06/15 Sheet ofFile: C:\Users\..\Sheet_Main_Header.SchDoc Drawn By:

Main FPGA Header

VCC2V5

1uC75

GND

TP15

GND

TP16

GND

M_HEADER_3M_HEADER_2M_HEADER_1M_HEADER_0

M_HEADER_4M_HEADER_5M_HEADER_6M_HEADER_7

M_HEADER_8M_HEADER_9M_HEADER_10M_HEADER_11M_HEADER_12M_HEADER_13M_HEADER_14M_HEADER_15

VCC2V5

M_HEADER_16M_HEADER_17M_HEADER_18M_HEADER_19M_HEADER_20M_HEADER_21M_HEADER_22M_HEADER_23

M_HEADER_CLK_PM_HEADER_CLK_N

GND

iDifferentialPairClassClassName: D100


12345678910111213141516171819202122232425262728293031323334353637383940

CN3

Header 40

VIN VCC3V3

Compatible to SASEBO-GII

1uC76

GND

1uC77

GND

VCC3V3 VIN

53

Figure 25 : Schematic – Main FPGA Peripheral

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

D D

C C

B B

A A

Title

Number RevisionSize

A3

Date: 2013/06/15 Sheet ofFile: C:\Users\..\Sheet_Main_Peripheral.SchDocDrawn By:

Main FPGA Peripheral

M_DIPSW_0M_DIPSW_1M_DIPSW_2M_DIPSW_3M_DIPSW_4M_DIPSW_5M_DIPSW_6M_DIPSW_7

SW3

GND

M_PUSHSW_0

M_RSVIO_0_PM_RSVIO_0_N TP18

TP17

10kR58

GND

LED10LED

LED9LED

LED8LED

LED7LED

LED6LED

LED5LED

LED4LED

LED3LED

LED2LED

LED1LED

150R48

GND GND

M_LED_0M_LED_1M_LED_2M_LED_3M_LED_4M_LED_5M_LED_6M_LED_7M_LED_8M_LED_9

GND GND GND GND GND GND GND GND

10k

81

72

63

54

RA110k

81

72

63

54

RA2

M_PUSHSW_1

SW4

10kR59

GND

56789

10111213141516

43211

23

45

67

8

SW5

DIPSW-8

VCC2V5

150R49

150R50

150R51

150R52

150R53

150R54

150R55

150R56

150R57

iNet ClassClassName: D100

iNet ClassClassName: D100

54

Figure 26 : Schematic – Main FPGA Supervisor

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

D D

C C

B B

A A

Title

Number RevisionSize

A3

Date: 2013/06/15 Sheet ofFile: C:\Users\..\Sheet_Main_Supervisor.SchDocDrawn By:

Main FPGA Supervisor

5

1

234

J5 SMA

5

1

234

J4 SMA

GND

GND

0.01uC80

GND

10uC78

GND

BLM18PG221SN1L3

M_CLK_INH_BM_CLK_OSC

2.2kR61

GND

330R60

DNPJP3

1u

C79

GND

VCC2V5

0

R62

SW6

GND

RECONF

GND

M_RESET_B

SW7

GND GNDGND

0.1uC82

RESET

GND

M_DONE

M_PROG_B

M_CLK_EXT0_NM_CLK_EXT0_P

GND2 VCC 4

OUT 3INH1

U11

48.000000MHz

DNP

C84

VCC2V5

VCC2V5

10kR63

VCC2V5

0.1uDNP

C81

0.1uDNP

C83

MRC4

RSTIN5

MR3

RST 1

VSS

2

VCC16U12 STM6779YWB6F

GND

140~280ms




55

Figure 27 : Schematic – Main FPGA Configuration

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

D D

C C

B B

A A

Title

Number RevisionSize

A3

Date: 2013/06/15 Sheet ofFile: C:\Users\..\Sheet_Control_FPGA_Config.SchDocDrawn By:

Controller FPGA Configuration

C_DONE

C_JTAG_TMS

C_JTAG_TCK

C_JTAG_TDOC_JTAG_TDI

C_PROG_B

JTAG CONFIG

C_JTAG_TMSC_JTAG_TCKC_JTAG_TDOC_JTAG_TDI

1 23 45 67 89 1011 1213 14

CN4

Xilinx JTAG

C_CCLKC_MISOC_MOSI

C_CSO_B

C_DONE

LED25LED

LED26LED

LED27LED

C_PROG_B

330R65

330R66

C_INIT_B

27R64

PROGRAM_B_2R2

SUSPENDL13

CMPCS_B_2L10

DONE_2R14

TCKA14

TDIE10

TMSE13 TDOD12

U2E

STD_XC6SLX9-2CSG225C

GND

INIT/ERRORCONF DONE RESET

VCC2V5

XC6SLX16 3,731,264bitXC6SLX9 2,742,528bit

GND

10kR67

10kR68

10kR70

10kDNP

R69

0.1uC85

GND

VCC2V5

0.1uC86

GND

100

R74

1uDNP

C87

1kR73

VCC2V8 VCC2V8 VCC2V8

330R71

1kR72

GND

VCC2V5VCC2V5

VCC2V5VCC2V5

VCC2V5

1001%

R75

GND

1001%

R76

VCC2V5

Close to SPI-ROM


SI1 SCK2

RESET3 CS4

WP5

VCC 6

GND 7

SO 8

U13

AT45DB321D

56

Figure 28 : Schematic – Controller FPGA I/O (Bank 0, 1)

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

D D

C C

B B

A A

Title

Number RevisionSize

A3

Date: 2013/06/15 Sheet ofFile: C:\Users\..\Sheet_Control_FPGA_IO_1.SchDocDrawn By:

Controller FPGA IO 1 (BANK0, 1)

M_DONE

M_PROG_B

M_CCLK

M_MOSI_CSI_B

M_CSO_B

M_RDWR_B

M_D1

M_D3

M_D7

1kR77

GND

C_HSWAPEN

100R80

100R84

100R79

0R90

100R78

100R83

100R88

100R89

100R86

100R81

100R85

M_DONE_R

M_PROG_B_R

M_CCLK_R

M_MOSI_CSI_B_R

M_CSO_B_R

M_RDWR_B_R

M_D1_R

M_D3_R

M_D7_R

C_HSWAPEN

M_DOUT_BUSY

M_D0_DIN_MISO M_D0_DIN_MISO_R

M_DOUT_BUSY_R

BANK 0IO_L1P_HSWAPEN_0B2

IO_L1N_VREF_0A2

IO_L2P_0B3

IO_L2N_0A3

IO_L3P_0D5

IO_L3N_0C5

IO_L4P_0C4

IO_L4N_0A4

IO_L5P_0E6

IO_L5N_0D6

IO_L6P_0B5

IO_L6N_0A5

IO_L7P_0D7

IO_L7N_0C7

IO_L33P_0C6

IO_L33N_0A6

IO_L34P_GCLK19_0E7

IO_L34N_GCLK18_0D8

IO_L35P_GCLK17_0B7

IO_L35N_GCLK16_0A7

IO_L36P_GCLK15_0C8

IO_L36N_GCLK14_0A8

IO_L37P_GCLK13_0B9

IO_L37N_GCLK12_0A9

IO_L38P_0F8

IO_L38N_VREF_0E8

IO_L39P_0D10

IO_L39N_0C9

IO_L40P_0F10

IO_L40N_0E9

IO_L62P_0C10

IO_L62N_VREF_0A10

IO_L63P_SCP7_0B11

IO_L63N_SCP6_0A11

IO_L64P_SCP5_0D11

IO_L64N_SCP4_0C11

IO_L65P_SCP3_0B13

IO_L65N_SCP2_0A13

IO_L66P_SCP1_0C12

IO_L66N_SCP0_0A12

U2A


BANK 1IO_L1P_A25_1B14

IO_L1N_A24_VREF_1B15

IO_L30P_A21_M1RESET_1G11

IO_L30N_A20_M1A11_1G12

IO_L31P_A19_M1CKE_1F11

IO_L31N_A18_M1A12_1F12

IO_L32P_A17_M1A8_1H10

IO_L32N_A16_M1A9_1H11

IO_L33P_A15_M1A10_1C14

IO_L33N_A14_M1A4_1C15

IO_L34P_A13_M1WE_1H12

IO_L34N_A12_M1BA2_1G13

IO_L35P_A11_M1A7_1D13

IO_L35N_A10_M1A2_1D15

IO_L36P_A9_M1BA0_1J11

IO_L36N_A8_M1BA1_1J13

IO_L37P_A7_M1A0_1E14

IO_L37N_A6_M1A1_1E15

IO_L38P_A5_M1CLK_1K10

IO_L38N_A4_M1CLKN_1K11

IO_L39P_M1A3_1F13

IO_L39N_M1ODT_1F15

IO_L40P_GCLK11_M1A5_1K12

IO_L40N_GCLK10_M1A6_1L12

IO_L41P_GCLK9_IRDY1_M1RASN_1G14

IO_L41N_GCLK8_M1CASN_1G15

IO_L42P_GCLK7_M1UDM_1H13

IO_L42N_GCLK6_TRDY1_M1LDM_1H15



IO_L44P_A3_M1DQ6_1K13

IO_L44N_A2_M1DQ7_1K15

IO_L45P_A1_M1LDQS_1L14

IO_L45N_A0_M1LDQSN_1L15

IO_L46P_FCS_B_M1DQ2_1M13

IO_L46N_FOE_B_M1DQ3_1M15

IO_L47P_FWE_B_M1DQ0_1N14

IO_L47N_LDC_M1DQ1_1N15

IO_L74P_AWAKE_1P14

IO_L74N_DOUT_BUSY_1P15

U2B

STD_XC6SLX9-2CSG225CLX9/LX16 CSG225

MC_IC_D9

MC_IC_D10

MC_IC_D11MC_IC_D12

MC_IC_D13

MC_IC_D14MC_IC_D15

MC_IC_D16

MC_IC_D17MC_IC_D18

MC_IC_D19

MC_IC_D20MC_IC_D21

MC_IC_D22

MC_IC_D23

MC_IC_D28

MC_IC_D25

C_FTDI_RESET_BFTDI_PWREN_B

FTDI_SUSPEND_B

FTDI_ACBUS5_CLKOUT

FTDI_ACBUS6_OE_B

FTDI_ACBUS7

FTDI_ADBUS0_D0

FTDI_ADBUS1_D1FTDI_ADBUS2_D2

FTDI_ADBUS3_D3

FTDI_ADBUS4_D4

FTDI_ADBUS5_D5

FTDI_ADBUS6_D6

FTDI_ADBUS7_D7

FTDI_ACBUS0_RXF_B

FTDI_ACBUS1_TXE_B

FTDI_ACBUS2_RD_BFTDI_ACBUS3_WR_B

FTDI_ACBUS4_SIWUA

MC_IC_D39MC_IC_D40

MC_IC_D41

MC_IC_D42

MC_IC_D43

MC_IC_D44

MC_IC_D45MC_IC_D46

MC_IC_D47

MC_IC_D48

MC_IC_D49

MC_IC_D50

MC_IC_D36

MC_IC_D37

MC_IC_D38

MC_IC_D3MC_IC_D4

MC_IC_D5

MC_IC_D6MC_IC_D7

MC_IC_D8MC_IC_D24

MC_IC_D26MC_IC_D27

M_D4 100R82 M_D4_R

MC_IC_D34MC_IC_D35

M_D2 100R87 M_D2_R

1001%

R91

GND

1001%

R92

VCC2V5

Close to SPI-ROM


57

Figure 29 : Schematic – Controller FPGA I/O (Bank 2, 3)

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

D D

C C

B B

A A

Title

Number RevisionSize

A3

Date: 2013/06/15 Sheet ofFile: C:\Users\..\Sheet_Control_FPGA_IO_2.SchDocDrawn By:

Controller FPGA IO 2 (BANK2, 3)

C_CCLK

C_MISO

C_INIT_B

C_MOSI

C_CSO_B

C_M0

C_M1

C_M0

C_M1

1kR93

1kR94

VCC2V5

GND

1kR95

VCC2V5MC_IC_D29

MC_IC_D30

MC_IC_D33

BANK 2IO_L1P_CCLK_2N12

IO_L1N_M0_CMPMISO_2R12

IO_L2P_CMPCLK_2P13

IO_L2N_CMPMOSI_2R13

IO_L3P_D0_DIN_MISO_MISO1_2P11

IO_L3N_MOSI_CSI_B_MISO0_2R11

IO_L12P_D1_MISO2_2M11

IO_L12N_D2_MISO3_2N11

IO_L13P_M1_2N10

IO_L13N_D10_2R10

IO_L14P_D11_2L9

IO_L14N_D12_2M10

IO_L15P_2M9

IO_L15N_2N9

IO_L16P_2P9

IO_L16N_VREF_2R9

IO_L29P_GCLK3_2N8

IO_L29N_GCLK2_2R8

IO_L30P_GCLK1_D13_2M8

IO_L30N_GCLK0_USERCCLK_2N7

IO_L31P_GCLK31_D14_2K8

IO_L31N_GCLK30_D15_2L8

IO_L32P_GCLK29_2P7

IO_L32N_GCLK28_2R7

IO_L47P_2L7

IO_L47N_2M6

IO_L48P_D7_2N6

IO_L48N_RDWR_B_VREF_2R6

IO_L49P_D3_2P5

IO_L49N_D4_2R5

IO_L62P_D5_2L6

IO_L62N_D6_2L5

IO_L63P_2N4

IO_L63N_2R4

IO_L64P_D8_2M5

IO_L64N_D9_2N5

IO_L65P_INIT_B_2P3

IO_L65N_CSO_B_2R3

U2C


BANK 3IO_L1P_3M4

IO_L1N_VREF_3L3

IO_L2P_3P2

IO_L2N_3P1

IO_L37P_M3DQ0_3N2

IO_L37N_M3DQ1_3N1

IO_L38P_M3DQ2_3M3

IO_L38N_M3DQ3_3M1

IO_L39P_M3LDQS_3L2

IO_L39N_M3LDQSN_3L1

IO_L40P_M3DQ6_3K3

IO_L40N_M3DQ7_3K1



IO_L42P_GCLK25_TRDY2_M3UDM_3H3

IO_L42N_GCLK24_M3LDM_3H1

IO_L43P_GCLK23_M3RASN_3K4

IO_L43N_GCLK22_IRDY2_M3CASN_3J3

IO_L44P_GCLK21_M3A5_3G2

IO_L44N_GCLK20_M3A6_3G1

IO_L45P_M3A3_3K5

IO_L45N_M3ODT_3J4

IO_L46P_M3CLK_3F3

IO_L46N_M3CLKN_3F1

IO_L47P_M3A0_3J5

IO_L47N_M3A1_3H4

IO_L48P_M3BA0_3G5

IO_L48N_M3BA1_3G3

IO_L49P_M3A7_3H6

IO_L49N_M3A2_3H5

IO_L50P_M3WE_3F5

IO_L50N_M3BA2_3F4

IO_L51P_M3A10_3E5

IO_L51N_M3A4_3E4

IO_L52P_M3A8_3E2

IO_L52N_M3A9_3E1

IO_L53P_M3CKE_3D4

IO_L53N_M3A12_3E3

IO_L54P_M3RESET_3D3

IO_L54N_M3A11_3D1

IO_L83P_3C2

IO_L83N_VREF_3C1

U2D


C_HEADER_3

C_HEADER_2C_HEADER_1

C_HEADER_0

C_HEADER_4

C_HEADER_5


C_HEADER_8


C_HEADER_11C_HEADER_12C_HEADER_13C_HEADER_14

C_HEADER_15


C_HEADER_18


C_HEADER_21


C_HEADER_CLK_PC_HEADER_CLK_N

C_CLK_OSC

C_CLK_EXT0_NC_CLK_EXT0_P

C_LED_0

C_LED_1C_LED_2

C_LED_3

C_LED_4

C_LED_5

C_LED_6

C_LED_7C_LED_8

C_LED_9

M_M1_REMOTEM_M0_REMOTE

C_CLK_INH_B

C_RESET_BC_PUSHSW_0

C_DIPSW_0

C_DIPSW_1C_DIPSW_2C_DIPSW_3

C_PUSHSW_1

C_DIPSW_4C_DIPSW_5C_DIPSW_6

C_DIPSW_7

MC_IC_D0

MC_IC_D1MC_IC_D2

MC_IC_D31

MC_IC_D32

M_INIT_B 100R96 M_INIT_B_R

M_D5 100R98 M_D5_R

M_D6 100R97 M_D6_R

58

Figure 30 : Schematic – Controller FPGA Power

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

D D

C C

B B

A A

Title

Number RevisionSize

A3

Date: 2013/06/15 Sheet ofFile: C:\Users\..\Sheet_Control_FPGA_Power.SchDocDrawn By:

Controller FPGA Power

GND GND

4.7uC96

GND

0.47uC97

GND

VCC2V5

4.7uC94

GND

4.7uDNP

C93

GND

4.7uC89

GND

0.47uC91

GND4.7uC103

GND GND

0.47uC104

GNDVCC1V2C

VCC2V5

4.7uC106

GND GND

0.47uC107

GND

VCC2V5

4.7uC100

GND GND

0.47uC101

GND

VCC2V5

4.7uC109

GND GND

0.47uC110

GND

VCC2V5

4.7uDNP

C92

GND

4.7uC95

GND

100uC88

0.47uC90

GNDGND

100uC99

100uC102

100uC105

100uC108

VCCAUXB1

VCCAUXE12

VCCAUXF7

VCCAUXG10

VCCAUXJ6

VCCAUXK9

VCCAUXL4

VCCAUXM12

VCCINTF9

VCCINTG6

VCCINTG8

VCCINTH7

VCCINTH9

VCCINTJ10

VCCINTJ8

VCCINTK7

VCCO_0 B12

VCCO_0 B4

VCCO_0 B8

VCCO_0 D9

VCCO_1 D14

VCCO_1 H14

VCCO_1 J12

VCCO_1 M14

VCCO_2 M7

VCCO_2 P12

VCCO_2 P4

VCCO_2 P8

VCCO_3 D2

VCCO_3 G4

VCCO_3 H2

VCCO_3 M2

U2F


GNDA1

GNDA15

GNDB10

GNDB6

GNDC13

GNDC3

GNDE11

GNDF14

GNDF2

GNDF6

GNDG7

GNDG9

GNDH8

GND J7

GND J9

GND K14

GND K2

GND K6

GND L11

GND N13

GND N3

GND P10

GND P6

GND R1

GND R15

U2G


0.47uC98

GND

59

Figure 31 : Schematic – Controller FPGA Header

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

D D

C C

B B

A A

Title

Number RevisionSize

A3

Date: 2013/06/15 Sheet ofFile: C:\Users\..\Sheet_Control_Header.SchDocDrawn By:

Controller FPGA Header


1uC111

TP19 TP20


C_HEADER_8C_HEADER_9C_HEADER_10C_HEADER_11C_HEADER_12C_HEADER_13C_HEADER_14C_HEADER_15

C_HEADER_16C_HEADER_17C_HEADER_18C_HEADER_19C_HEADER_20C_HEADER_21C_HEADER_22C_HEADER_23

C_HEADER_CLK_PC_HEADER_CLK_N

VCC2V5

GND GND GND

VCC2V5



12345678910111213141516171819202122232425262728293031323334353637383940

CN5

Header 40

GND

VIN VCC3V3

Compatible to SASEBO-GII

1uC112

GND

1uC113

GND

VCC3V3 VIN

60

Figure 32 : Schematic – Controller FPGA Peripheral

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

D D

C C

B B

A A

Title

Number RevisionSize

A3

Date: 2013/06/15 Sheet ofFile: C:\Users\..\Sheet_Control_Peripheral.SchDocDrawn By:

Controller FPGA Peripheral

SW8

C_LED_0

C_PUSHSW_0

10kR109

C_DIPSW_0C_DIPSW_1C_DIPSW_2C_DIPSW_3

10k

81

72

63

54

RA3

LED14LED

LED13LED

LED12LED

LED11LED

150R99

GND GND GND GND

C_LED_1C_LED_2C_LED_3

150R100

150R101

150R102

GNDGND GND

56789

10111213141516

43211

23

45

67

8

SW10

DIPSW-8

VCC2V5

10k

81

72

63

54

RA410kR110

SW9

C_PUSHSW_1

C_DIPSW_4C_DIPSW_5C_DIPSW_6C_DIPSW_7

LED20LED

LED19LED

LED18LED

LED17LED

LED16LED

LED15LED

GND GNDGND GND GND GND

150R103

150R104

150R105

150R106

150R107

150R108

C_LED_4C_LED_5C_LED_6C_LED_7C_LED_8C_LED_9

61

Figure 33 : Schematic – Controller FPGA Supervisor

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

D D

C C

B B

A A

Title

Number RevisionSize

A3

Date: 2013/06/15 Sheet ofFile: C:\Users\..\Sheet_Control_Supervisor.SchDocDrawn By:

Controller FPGA Supervisor

GND2 VCC 4

OUT 3INH1

U14

48.000000MHz

GND

0.01uC116

GND

10uC114

GND

BLM18PG221SN1L4

C_CLK_INH_BC_CLK_OSC

2.2kR112

GND

330R111

DNPJP4

5

1

234

J7 SMA

5

1

234

J6 SMA

GND

C_CLK_EXT0_N

1u

C115

GND

C_CLK_EXT0_P

0

R113

C_RESET_B

C_DONE

C_PROG_B

VCC2V5 VCC2V5

SW11

GND

RECONF

GND

SW12

GND GNDGND

0.1uC118

RESET

GND

DNP

C120

VCC2V5

10kR114

VCC2V5

0.1uDNP

C117

0.1uDNP

C119

MRC4

RSTIN5

MR3

RST 1

VSS

2

VCC16U15 STM6779YWB6F

GND

140~280ms




62

Figure 34 : Schematic – USB

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

D D

C C

B B

A A

Title

Number RevisionSize

A3

Date: 2013/06/15 Sheet ofFile: C:\Users\..\Sheet_USB.SchDoc Drawn By:

USB

FTDI_PWREN_BFTDI_SUSPEND_B

M_FTDI_RESET_B

GND

VCC3V3

GND

0.1uC141

GND

VCC3V3

GND

10uC124

GND

BLM18PG221SN1L8

12.000000MHz

NC2 X2 3X11 NC 4

U16

22pC139

22pC140

GND GND

GND

10uC126

GND

BLM18PG221SN1L9

VCC3V3

VCC3V3

0.1uC131

GND

0.1uC130

GND

0.1uC129

GND

0.1uC136

GND

0.1uC135

GND

VCC3V3

0.1uC134

GND

0.1uC133

GND

2.2kDNP

R117

VCC3V3

12.0k1%

R118

GND

2.2k

R124

VCC3V3

10kR126

VCC3V3

10kR125

VCC3V3

10kR123

2.2kR116

GND

CS 1

SK 2

DI 3

DO 4GND5

ORG6 DC7

VCC8U18

AT93C46D-TP25-B

1u

C128

1u

C132

GND

GND

1u

C127

1u

C125

USB_D_FILTER_PUSB_D_FILTER_N

0

R115

USBGND

USBVBUS

0.1uC121

USBGND

USBVBUS

EMI2

ACM9070-701-2PL-TL01

USBGND GND

VBUSUSBVBUS

GND

VBUS

0.1uC122

GND

VBUS

10uC123

VBUS 1

D- 2

D+ 3

GND 4

CN6USB-B

F1

FuseEMI1

DLW21HN900SQ2

BLM18PG221SN1L5

BLM18PG221SN1L6

BLM18PG221SN1L7

Place as close to USB Connector

FTDI_VCORE

FTDI_VCCIO

2.2kR121

10uC138

GND

0.1uC137

VCC3V3

GND2.2k

81

72

63

54

RA52.2k

81

72

63

54

RA62.2k

81

72

63

54

RA72.2k

81

72

63

54

RA8

2.2k

81

72

63

54

RA92.2k

81

72

63

54

RA102.2k

81

72

63

54

RA112.2k

81

72

63

54

RA12

USB_D_N

USB_D_P

TP22

TP21

0 DNPR119

FTDI_RESET_B

FTDI_VREGOUT

VCC3V3

VCC3V3

FTDI_VREGOUT

DNP

JP5

USB_FG

USB_VBUS

USB_GND

FTDI_RESET_B

C_FTDI_RESET_B 0 DNPR120

DNP

JP6

FTDI_ADBUS0_D0FTDI_ADBUS1_D1FTDI_ADBUS2_D2FTDI_ADBUS3_D3FTDI_ADBUS4_D4FTDI_ADBUS5_D5FTDI_ADBUS6_D6FTDI_ADBUS7_D7

FTDI_ACBUS0_RXF_BFTDI_ACBUS1_TXE_BFTDI_ACBUS2_RD_BFTDI_ACBUS3_WR_BFTDI_ACBUS4_SIWUAFTDI_ACBUS5_CLKOUTFTDI_ACBUS6_OE_BFTDI_ACBUS7

FTDI_BDBUS0_D0FTDI_BDBUS1_D1FTDI_BDBUS2_D2FTDI_BDBUS3_D3FTDI_BDBUS4_D4FTDI_BDBUS5_D5FTDI_BDBUS6_D6FTDI_BDBUS7_D7

FTDI_BCBUS0_RXF_BFTDI_BCBUS1_TXE_BFTDI_BCBUS2_RD_BFTDI_BCBUS3_WR_BFTDI_BCBUS4_SIWUBFTDI_BCBUS5FTDI_BCBUS6FTDI_BCBUS7_PWRSAV_B

GND

1

OSCI2

OSCO3

VPH

Y4

GND

5

REF6

DM7

DP8

VPL

L9

AGND

10

GND

11VCORE

12

TEST13

RESET#14

GND

15

ADBUS0 16

ADBUS1 17

ADBUS2 18

ADBUS3 19

VCCIO

20

ADBUS4 21

ADBUS5 22

ADBUS6 23

ADBUS7 24

GND

25

ACBUS0 26

ACBUS1 27

ACBUS2 28

ACBUS3 29

ACBUS4 30

VCCIO

31

ACBUS5 32

ACBUS6 33

ACBUS7 34

GND

35

SUSPEND# 36

VCORE

37

BDBUS0 38

BDBUS1 39

BDBUS2 40

BDBUS3 41

VCCIO

42

BDBUS4 43

BDBUS5 44

BDBUS6 45

BDBUS7 46

GND

47

BCBUS0 48

VREGOUT49

VREGIN50

GND

51

BCBUS1 52

BCBUS2 53

BCBUS3 54

VCCIO

56

BCBUS4 55

BCBUS5 57

BCBUS6 58

BCBUS7 59

PWREN# 60

EECLK62

EEDATA61

EECS63

VCORE

64

U17FT2232H

GND

10uC124

GND

BLM18PG221SN1L8

GND

10uC126

GND

BLM18PG221SN1L9

VCC3V3

VCC3V3

0.1uC131

GND

0.1uC130

GND

0.1uC129

GND

0.1uC136

GND

0.1uC135

GND

VCC3V3

0.1uC134

GND

0.1uC133

GND

1u

C128

1u

C132

GND

GND

1u

C127

1u

C125

0.1uC121

USBGND

USBVBUS

EMI2

ACM9070-701-2PL-TL01

USBGND GND

VBUSUSBVBUS

GND

VBUS

0.1uC122

GND

VBUS

10uC123

FTDI_VCORE

FTDI_VVVCCIO

0.1uC137

VCC3V3

GND

TP22

TP21

FTDI_VREGOUT

FTDI_V

VPH

Y4

VP

VVLL

9

VCORE

12

VCCIO

20

VCCIO

31

VCORE

37

VCCIO

42

VREGOUT49

VREGINII50

VCCIO

56

VCORE

64GND





63

4.3. Parts List Table 48 : SAKURA-G Parts List

Description Part Number Maker Designator Spec.

Capacitor UUD1C221MCL1GS Nichicon C1 220u

Capacitor GRM188B31H104KA Murata C2 0.1u

Capacitor C3216JB1C106KT TDK C3 10u

Capacitor C2012X7R1E104K/0.85 Murata C4, C17 0.1u

Capacitor C1608X5R0J106MT TDK C5, C16, C18, C19, C22, C26,

C30, C31, C34, C37, C78,

C114, C123, C124, C126,

C138

10u

Capacitor PCJ0J391MCL1GS Nichicon C6, C21 390u

Capacitor GRM188R60J475ME19D Murata C7, C9, C10, C12, C13, C15,

C43, C44, C56, C60, C66,

C70, C89, C94, C95, C96,

C100, C103, C106, C109

4.7u

Capacitor GRM32ER60J107ME20L Murata C20, C24, C42, C55, C59,

C65, C69, C88, C99, C102,

C105, C108

100u

Capacitor NFM18PC105R0J3 Murata C23, C79, C115, C125, C127,

C128, C132

1u

Capacitor C1005X7R1E104M (7) Murata C25, C27, C29, C33, C36,

C38, C39, C40, C82, C85,

C86, C118, C121, C122,

C129, C130, C131, C133,

C134, C135, C136, C137,

C141

0.1u

Capacitor GRM1555C1H102JA Murata C28, C32, C35 1000p

Capacitor C1005X5R1A474K TDK C45, C46, C47, C48, C57,

C58, C61, C62, C63, C64,

C67, C68, C71, C72, C73,

C74, C90, C91, C97, C98,

C101, C104, C107, C110

0.47u

Capacitor C1005JB0J105KT TDK C75, C76, C77, C111, C112,

C113

1u

Capacitor GRM155B11E103K Murata C80, C116 0.01u

64

Capacitor GRM1555C1H220J Murata C139, C140 22p

Connector B2P-VH(LF)(SN) JST CN1

Connector 87832-1420 Molex CN2, CN4

Header 2131D2*20GSE Linkman CN3, CN5

Connector 61729-0011BLF FCI CN6

Diode MMBD1501A Fairchild D1

EMI Filter DLW21HN900SQ2 Murata EMI1

EMI Filter ACM9070-701-2PL-TL01 TDK EMI2

Fuse MICROSMD050F-2 TE F1

SMA Jack 5-1814832-1 TE J1, J2, J3, J4, J5, J6, J7

Header 68001-202HLF FCI JP2

Inductor BLM18PG221SN1 Murata L1, L2, L3, L4, L5, L6, L7,

L8, L9

LED SML-310MTT86 Rohm LED1, LED2, LED3, LED4,

LED5, LED6, LED7, LED8,

LED9, LED10, LED11,

LED12, LED13, LED14,





LED27

Resistor KRL3264-C-R010-F-T1 Susumu R1 10m

Resistor ERJ-6ENF6652V Panasonic R2 66.5k

Resistor RK73B1ETTP561J KOA R3 560

Resistor RK73H1ETTP7502F KOA R4 75k






Resistor ERJ-6ENF1002V Panasonic R10 10k

Resistor RK73B1ETTP102J KOA R11, R39, R41, R43, R47,

R72, R73, R77, R93, R94,

R95

1k

Resistor RL1220S-1R0-F Susumu R12 1

Resistor RK73Z1JTTD KOA R13, R14, R16, R46, R90 0

65

Resistor RK73H1ETTP1R00F KOA R15 1

Resistor ERJ2RKF61R9X Panasonic R17 61.9

Resistor ERJ-2RKF4020X Panasonic R18, R19 402

Resistor ERJ-2RKF8060X Panasonic R20 806


Resistor ERJ-2RKF3570X Panasonic R22 357


Resistor ERJ-2RKF27R0X Panasonic R24, R64 27

Resistor RK73B1ETTP331J KOA

R25, R26, R27, R31, R32,

R38, R60, R65, R66, R71,

R111

330


R28, R29, R30, R33, R34,

R36, R58, R59, R63, R67,

R68, R70, R109, R110,

R114, R123, R125, R126

10k

Resistor RK73Z1ETTP KOA R37, R40, R62, R113 0

Resistor RK73B1ETTP101J KOA R42, R74 100


R48, R49, R50, R51, R52,

R53, R54, R55, R56, R57,

R99, R100, R101, R102,

R103, R104, R105, R106,

R107, R108

150

Resistor RK73B1ETTP222J KOA R61, R112, R116, R121,

R124 2.2k

Resistor RK73H1JTTD1000F KOA R75, R76, R91, R92 100

Resistor RK73B1JTTD101J KOA

R78, R79, R80, R81, R82,

R83, R84, R85, R86, R87,

R88, R89, R96, R97, R98

100

Resistor MCR18EZPJ000 Rohm R115 0

Resistor RK73H1ETTP1202F KOA R118 12.0k

Resistor

Array MNR04M0APJ103 Rohm RA1, RA2, RA3, RA4 10k

Resistor

Array MNR04M0APJ222 Rohm

RA5, RA6, RA7, RA8, RA9,

RA10, RA11, RA12 2.2k

SPDT

Switch MS-13AAP1 Nikkai SW1

Switch CHS-04TB1 Copal SW2

66

Electronics

Switch B3FS-1000P Omron SW3, SW4, SW6, SW7,

SW8, SW9, SW11, SW12

Switch CHS-08TB1 Copal

ElectronicsSW5, SW10

Test Pin RCTCTE KOA TP15, TP16, TP19, TP20

FPGA XC6SLX75-2CSG484C Xilinx U1

FPGA XC6SLX9-2CSG225C Xilinx U2

Regulator LT3083EQ#PBF LT U3, U7

Regulator MCP1726-ADJE/MF Microchip U4, U5, U6

Amplifier AD8000YRDZ ADI U8

Logic IC 74LVC157APW,118 NXP U9

SPI Flash

Memory AT45DB321D-SU Adesto U10, U13

Oscillator ECS-3525-480-B-TR ECS U11, U14 48MHz

Supervisor

IC STM6779YWB6F STMicro U12, U15

Crystal

Unit CX3225GB12000D0HEQZ1 AVX U16 12MHz

USB I/F IC FT2232HL-REEL FTDI U17

SPI

EEPROM AT93C46D-TH-B Atmel U18

Variable

Resistor

ST32ETA203 Copal

Electronics

VR1 20k

67

4.4. Board Layout

Figure 35 : L1 Pattern

Figure 36 : L2 Cut Pattern

68



69

Figure 39 : L5 Cut Pattern


70

Figure 41 : Top Silk

Figure 42 : Bottom Silk (flipped)

Please ask to sales for detail of board layout.

71

MORITA TECH CO.,LTD.

3-8-1 Kurikidai, Asao, Kawasaki, Kanagawa, 215-0032, JAPAN

TEL: +81-44-980-8139

FAX: +81-44-980-8140

[email protected]

http://www.morita-tech.co.jp/SAKURA/en/index.html

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