runtime fpga partial reconffiguration · 2009. 3. 27. · addition, limitations to this emerging...

Runtime FPGA Partial Reconffiguration

Eric J. McDonaldThe Aerospace Corporation

ABSTRACT

Field programmable gate arrays (FPGAs) are nowbeing integrated into many space-based applications.FPGAs are being used as replacements forapplication-specific integrated circuits (ASICs) withoutconsidering new options offered by their reprogrammnablenature. Runtime partial reconfiguration can potentiallyreduce the number of devices or the device size, therebyreducing both size and power consumption. A system thatrequires either transmit or receive capabilities at anygiven time, but not both, can switch between the twomodes in a fraction of a second using partialreconfiguration. The current approach requires that bothmodes be implemented simultaneously, thereby wastingpower and requiring more resources. The idea ofadaptively allocating limited FPGA resources is alsoapplicable to hardware-accelerated, software-defimedradios. The hardware accelerators are loaded intoFPGA(s) as they are needed. Partial reconfigurationallows swapping of accelerators much faster than ispossible with current methods, and with less disruption toother processes running in parallel. This technologysignificantly reduces power consumption critical for spaceand portable ground-based applications of FPGAtechnology. A software-defined radio was designed with areprogrammable forward error correction (FEC) blocksupporting multiple FEC codes to demonstrate onepractical use of this technology. This provides anoverview of the design flow necessary for partialreconfiguration and comments on the additionaloverhead necessary for creating such a design. Inaddition, limitations to this emerging technology areoutlined 1,2.

'1-4244-1488-1/08/$25.00 Q 2008 MEEE.

'IEEE AC paper #1443, Version 4, Updated December 3.,2007.

Author's Current Address:The Aerospace Corporation, PO Box 92957, Los Angeles, CA 90009-2957, USA.

Based on a presentation at the 2008 Big Sky Conference.

0885/8985/08/ USA $25.00 Q 2008 IEEE

CLl~s

and

DSP48s

BRAMsand

FIF70s

Fig. 1. Layout of a small Virtex-4 FPGA (LX15)

INTRODUCTION

Field programmable gate arrays (EPOAs) are quicklybecoming the usual targeted technology for manydevelopment efforts due to their low cost and rapiddevelopment time. Advances in digital technology providethe means to make each generation of FPGAs significantlymore attractive and useful than their predecessors. Eachgeneration introduces additional benefits and utilities besides

10 IEEE A&E SYSTEMS MAGAZINE, JULY 200810

Authorized licensed use limited to: University of Florida. Downloaded on December 10, 2008 at 08:27 from IEEE Xplore. Restrictions apply.

Table 1. Summary of Configuration Options

Port Bus Max. uSec/Fraine

Serial 1 bit 100 MHz 13.12

JTAG 1 bit 66 MHz 19.88

SelectMap 8 bits 100 MHz 1.64

ICAP 8 bits3 100 MHz 1.64

the expected larger size and faster speed. Exploring suitableapplications for the latest available products must be acontinuous endeavor because their performance and abilitiesimprove significantly with each new product release.Additionally, because each vendor's products havecharacteristics and utilities that are not necessarily shared bythe competition and are often unique, evaluating a specificvendor's product requires significant effort and prevents astraightforward side-by-side comparison. One advancementof significant importance is the ability to reconfigure aportion of an FPGA. This ability is referred to as partialreconfiguration (PR). The focus herein is to evaluate runtimepartial reconfiguration in Xilinx's Virtex-4 FPGAs as itapplies to the field of software-defined radio.

To date, at least three vendors provide products that offersome degree of partial reconfiguration (Xilinx [1], Atmel [2],Lattice [3]). The real advantage of partial reconfigurationoccurs when the reconfiguration takes place dynamicallyduring runtime. Runtime partial reconfiguration, or dynamicreconfiguration, allows the reconfiguration of a portion of anFPGA while the remainder continues to run continuouslywithout losing any data. Because partial reconfiguration iscoupled very closely to the underlying framework of theFPGA itself, each vendor's FPGAs will have significantdifferences that may appear as disadvantages or advantagesfor a given application. Previous work has been done thatpresents a summnary of the available FPGAs that offer partialreconfiguration [4]. Due to the rapid advancement of thefield, the information contained in [4] from 2003 has alreadybecome outdated. For example, [4] summarizes the availableoptions for the original Virtex family (the XCV 1000,specifically), which was upgraded in 2002 with the Virtex-IIfamily, which was again upgraded in 2005 with the Virtex-4family, and has presently been upgraded with the latestXilinx family, Virtex-5. Each release includes improvementsto the existing products and to partial reconfigurationspecifically. (This paper explores potential uses of theVirtex-4 devices and makes no claims as to the abilities offuture devices from Xilinx or other vendors.) An in-depth

Table 1. ExampleConfiguration Sizes and Times toConfigure with JTAG and SelectMAPIICAP

Design Framnes4 JTAG SelectMap/ICAP

Turbo 154 3.061 ins 0.252 insEncoder

Turbo 4092 81.34 ins 6.710 insDecoder

SS 5610 111 ins 9.2 insAcquisition

FFT 4752 94.47 ins 7.79 ins(8192 bins)

look at partial reconfiguration can be found in [5], whichincludes a low-level description of partial reconfiguration inXilinx's Virtex-JI devices as well as an overview of some ofthe available tools developed to assist with partialreconfiguration.

This paper is organized as follows: the next section gives avery brief overview of software-defined radio; followed by acloser look at partial reconfiguration; next how partialreconfiguration fits with software-defined radio, and finally,the concluding remarks.

SOFTWARE-DEFINED RADIO

Wireless communication abilities are becoming ubiquitousin the latest generation of portable electronics. Besides thelarge variety of cellular communication standards, cellphones often come equipped with the capability to connect towireless ear buds. The latest generations of cameras are evenstarting to become equipped with various wirelesscommunication options to transfer pictures to and from selectdevices. All the while, satellites are being launched thatemploy different modulations and methods for forward errorcorrection. In order to communicate with a wide array ofdevices, an overwhelming number of communicationstandards must be available at any given time. Hardwaredesigns that attempt to provide compatibility with the currentstandards, if even possible, will likely become obsoleteshortly after their release. Software-defined radios (SDRs),where the communication parameters are defined at runtimeby software, have become increasingly attractive. Acollection of readings covering many of the important topicsrelating to SDRs can be found in [6]. Advancements inFPGAs have made the realization of such SDRs possible [7].A modem software-defined radio would ideally possess amultitude of function blocks that are available at any giventime and must be able to handle the bandwidth of the

'Configuration of a framne requires 41 32-bit words of configuration data.

IEEE A&E SYSTEMS MAGAZINE, JULY 2008 1

'The ICAP has a 32-bit mode but is believed to function only in the 8-bit mode at thepresent time.

I I


required channel. Creating a design that contains all possibleoptions at the same time is not feasible. An FPGA'sreconfigurable nature, however, provides a good foundationfor creating a modular design that can load the desiredfunctions as needed. In particular, reconfiguring thefunctionality of a specific block while the remainder of thedesign continues to function provides a unique opportunity tocreate an extremely flexible and compact design.

PARTIAL RECONFIGURATION IN THE VIRTEX-4

Before exploring the potential uses of partialreconfiguration, it is important to be aware of the currentperformance and limitations of the targeted device. Becauseof the widespread use of Xilinx's FPGAs, the Virtex-4 familywas chosen as the example FPGA. Of major importance arereconfiguration speeds and methods, design hierarchylimitations relating to PR modules (PRMs) and the number ofallowed PR regions, and software support for generating PRdesigns.

In order to discuss some of the specifics related to PR, it isimportant to understand the general structure of the XilinxFPGA and how it is configured. Each device will havevariations to the size and location of various elements, but theoverall structure of a Virtex-4 FPGA can be seen in Figure 1,where CLBs are configurable logic blocks, BRAMs are blockrandom access memories, FIFOs are first-in first-out buffers,DCMs are digital clock managers, DSP48s are Xilinx'sdigital signal processing units, and IOBs are input-outputbuffers. The FPGA is configured by writing bits to itsconfiguration memory (CM). The configuration data isorganized into frames that target specific areas of the FPGAthrough frame addresses. When using PR, the partialbitstreams will contain configuration data for a whole frameif any portion of that frame is to be reconfigured.

Reconfiguration SpeedReconfiguration times will be highly dependent upon the

size and organization of the PR region(s). The Virtex-4'spredecessor, the Virtex-JI, allows for PR of whole columnsonly, which potentially requires partial bitstreams to besignificantly larger than necessary. Allowing forarbitrarily-shaped PR regions was a great improvement in theVirtex-4 design. Because design size will impact thereconfiguration time, the metric of uSec/Frame is used whencalculating the reconfiguration speed.

Frames are composed of 41 32-bit words. The smallestVirtex-4 device, the LX15, has 3,740 frames, and the largestdevice, the FX140, has 41,152 frames [8]. There are fourmethods of configuring a device: externally through the serialconfiguration port, the JTAG (Boundary Scan) port, or theSelectMap port, or internally (using an embeddedmicrocontroller or state machine) through the intemnalconfiguration access port (ICAP). Each of these methods willhave applications where they are the most desirable. Becausereconfiguration using an embedded microcontroller providesa very flexible and powerful platform for PR designs, the

next subsection will present more details relating to thistopic. A summary of the configuration speeds is shown inTable 1.

To give an idea of approximate configuration times forvarious PR applications, the estimated sizes of some commonblocks and their configuration times are included in Table 2.Note that a certain amount of overhead is involved in settingup the addressing for PR and has been roughly estimated bythe author as approximately 10% and has been ignored in allcalculations. Also, multiple frames with the sameconfiguration can be written at the same time, therebyshortening the bitstream.

The values in Table 2 were based on estimates in Xilinx'sPlanAhead software when targeting an approximate PRregion slice utilization of 90%. Actual sizes and times will bedependent upon design implementation, target device, regionutilization, and resource location. For the examples in Table

Fig. 2. PR design using embedded microcontroller

2, the turbo encoder and decoder were purchased cores fromTurbo Concepts [9], the spread-spectrum (SS) acquisitionblock was a custom design capable of checking 300 chipoffsets and 10 frequency offsets in parallel with variablecorrelation times up to 100,000 chips, and the fast Fouriertransform (FFT) was a Xilinx core with 8192 bins and 12-bitinputs. (It is expected that the configuration port is thebottleneck in determining the reconfiguration times.)

Reconfiguration Using an Embedded MicrocontrollerIn addition to supporting an embedded soft processor core

(Xilinx's MicroBlaze) in all Virtex-il and later FPGAs,Xilinx also provides several FPGA lines that includeembedded IBM PowerPC hard processor cores. The ability ofthese cores to process C/C++ code makes them an extremelyflexible option for reconfigurable designs. By controllingreconfiguration using a processor that is embedded within theFPGA itself, the need to interface with an external controller(such as a PC) can be eliminated, allowing for autonomousoperation (depending upon the embedded software designand desired functionality).

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TOP MODULE

a) Hierarchical view before PR partitioning.

Fig. 3. Example design showing two PR regions

One potential embedded system design is shown inFigure 2.

The example design shown in Figure 2 includes C/C++code that determines when reconfiguration is necessary.When needed, the microprocessor loads the desiredconfiguration data from external memory and reconfiguresthe PR region through the ICAP primitive. Reconfigurationin this example is expected to be triggered by an event on theFPGA itself, such as acquisition of a PN code, loss of signallock, detection of an interfering signal, a set timer, etc., butcould also be triggered by an external interrupt. The externalmemory could consist of ROM, Flash memory, or staticRAM that is loaded at start-up or even filled by the FPGAitself (in the case where the FPGA is configured as a receiverand receives configuration data as the payload of atransmission). Xilinx. provides extensive embeddedmicroprocessor design support, including reconfigurationsupport in the form of source code for software functions andhardware implementation code for the peripheral businterface and necessary processes. The embeddedmicrocontroller can easily be replaced by a custom statemachine that handles the loading of configuration data whenthe overhead of an embedded microcontroller is undesirable.

PR Design HierarchyBecause the flow from the Hardware Description

Language (HDL) to configuration bitstream is extremelycomplicated, limitations on design hierarchy exist to assistthe software tools in creating PR designs. The primarylimitation requires that the top-level module containsubmnodules that are either static modules (SMs) or partiallyreconfigurable modules (PRMs). All communication (with afew exceptions for global signals such as clocks) must beexplicitly declared using 8-bit bus macros provided byXilinx. The current design flow allows for multiple PRMs ina single design. An example design with two PRMs is shownin Figure 3.

The required hierarchy adds a significant amount of effortwhen converting an existing static design into one that is

Fig. 4. Transceiver design with turbo coding andconcatenated convolutional + Reed-Solomon Coding

ready for PR. Having all the PRMs at the top level will oftenrequire routing many signals to and from another moduledeep within the main static module. For example, atransceiver with FEC modules embedded deep within boththe transmit and receive portions of the design requiresrouting all the necessary signals up and down through theentire hierarchy in order to have partially reconfigurable FECmodules. This example is shown in Figure 4, where theoriginal unpartitioned design is shown in Figure 4A, with thepartitioned design shown in Figure 4B.

PR Software SupportWhen PR initially became available, there was very little

software support to assist in generating PR designs andbitstreams. Efforts within the academic community attemptedto ease the burden of designers wishing to employ PR andaccomplished a limited amount of automation [10, 11].Recently, Xilinx has released an Early Access design flowfor PR that integrates with their sophisticated floor-plannertool, PlanAhead, and their synthesis tool, ISE. Modificationsare made to the ISE tool, making it valid only for PR designssuch that PlanAhead can call the modified functions in anautomated command-line fashion, hiding the user from many



of the low-level details that were previously theresponsibility of the user. When determining the size andlocation of a PR region, PlanAhead provides statistics on therequired primitives (DSP48s, BRAMs, etc.), the availableresources in the defined area, and statistics on utilization thatgreatly help during the floor-planning stage. PlanAhead alsocomes with a design-rule checker that assists in correctingany violations due to placement. While the PR flow'sintegration into PlanAhead continues to become moreuser-friendly with each release, the present software supportmakes PR designs manageable. As PR becomes mainstream,it is expected that Xilinx and other FPGA vendors will morefully support this technology through improved tools anddocumentation.

SDR AND PARTIAL RECONFIGURATION

Determiining whether PR is appropriate for a givenapplication depends heavily upon the FPGA family, theapplication details, and the application environment.However, partial reconfiguration (PR) has moved beyondbeing an emerging technology where the majority of effortshave been for research only to a viable option for productdevelopment. As such, one field where it can be applied togreat advantage is software-defined radio.

Simplex Spread-Spectrum Transceiver with FECOne potential SDR use would be in a simplex transceiver,

where only transmit or receive capabilities are used at anygiven time and are never used at the same time. Assumingthat the waveform requires FEC as well as direct-sequencespread-spectrum (DSSS), the design could be organized asshown in Figure 5. Two PR regions are declared: one foreither the Tx modulator or the Rx demodulator, one for theTx FEC encoder, the Rx DSSS acquisition engine, or the RxFEC decoder.

DSSS acquisition typically requires a lot of resources butis used only during the acquisition phase. Once the spreadingcode has been acquired, those resources can be reconfiguredas the FEC decoder while the Rx demodulator continues totrack the spreading code.

Dynamic Bandwidth Resource Allocation TransceiverSystems employing dynamic bandwidth resource

allocation (DBRA) would benefit substantially from the useof PR. These systems alter the communication waveformdynamically to match channel conditions. For instance, if thesignal-to-noise ratio (SNR) drops such that an unacceptablehit-error rate (HER) occurs, a combination of modulationtype, data rate, or FEC configuration changes may beperformed to decrease the BER. Alternately, if a high SNR isdetected, reconfiguration could be used to increasethroughput while still maintaining the desired BER.

Figure 6 shows one possible scenario with a transceiveremploying DBRA where the Tx waveform changes fromturbo-coded binary phase shift-keying (BPSK) to Gaussianminimum shift-keying (GMSK) with a concatenated

Fig. 5. Simplex transceiver withspread-spectrum and FEC

Fig. 6. Dynamic bandwidth resourceallocation transceiver

Channelizer(

FFT

Fig. 7. Cognitive radio receiver

convolutional encoder, followed by Reed-Solomon (RS)encoding. The Rx waveform switches from turbo-codedBPSK to 8-ary phase shift-keying (8PSK) to the concatenatedViterbi and Reed-Solomon decoder.

Cognitive RadioAnother example for the use of PR in SDR applications

comes in the field of cognitive radio (CR). A CR receiver

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Software-DefinedRadio

onPC

Funion3Z

ZunionU2FntonE]

FastExternalMemory(-I GB)

Fig. 8. Hardware acceleration of software-defuined radio

must scan the available spectrum using an FFT, locateenergy, create a channel that attempts to match the spectralshape, perform modulation recognition, and then try todemodulate. Because the spectrum must always (or at leastvery often) be monitored, the FFT module is left as static, butuse of the modulation recognition and demodulator aremutually exclusive, providing an opportunity to takeadvantage of PR. It is expected that switching betweenmodulation recognition and demodulation will occur often asthe receiver searches the available signals for the correct one.If reconfiguration could be achieved quickly enough, the FF1'module could potentially be made reconfigurable as well.Partitioning for this CR receiver example can be seen inFigure 7.

Hardware Acceleration (Future Work)While much research has been done in the field of

hardware acceleration, including the application of PR to thisfield, it is still worth illustrating how PR can be applied tothis problem. Considering a fully software-defined radioreceiver, it is clear that certain functions exceed thethroughput of even the most powerful general purposeprocessor (GPP). Situations where the hardware can greatlyreduce the throughput - such as decimation and despreading-have obvious benefits. Additionally, many of the latest FECcodes are computationally intensive, making them untenablefor software-only receivers.

If some latency is acceptable and enough memory exists, itis possible to implement a multichannel receiver in softwarewhile buffering data and time-sharing the FPGA as necessaryto process the data when necessary. Using an embeddedmicroprocessor and a memory manager, portions of theFPGA could be partially reconfigured (similar to a contextswitch) to process one channel's data and then reconfiguredto process another channel's data. Because the data can bebuffered during the reconfiguration, the only limitation is theaverage throughput of the FPGA, assuming that the memoryis sufficiently deep to avoid any losses during reconfigurationand buffering. Figure 8 shows a block diagram of such asystem.

CONCLUSIONS

Exploring the usefulness of PR in the field ofsoftware-defined radio has shown both its feasibility andbenefit. Several potential uses were detailed to illustrate howone might take advantage of this emerging technology.Resource utilization for a select number of function blockswere shown along with the required reconfiguration times.The latest software from Xilinx was found to relieve the userfrom the burden of following a complex design methodologywhen creating PR designs.

The design time overhead involved when creating a PRdesign is acceptable but requires progressing through a slowlearning curve before any results can be obtained. Much ofthe necessary support will likely come from the PRcommunity and not necessarily from the vendor. The fullbenefits of PR will not be evident until it becomescommonplace in industry and the vendors place moreresources on supporting the PR design flow and keeping thetools and documentation up to date. However, the adaptivityof PR combined with the desire for software-defined radiosmakes a strong argument for pursuing partial reconfiguration.

FXERENCES

[1] Xilinx Virtex-4 Users Guide, www.xilinx.com.

[2] Atmel AT40KAL Users Guide, www.atmel.com.

[3] LatticeXP Family Data Sheet, www.latticesemni.comn.

[4] S. Donthi and R.L. Haggard,A survey of dynamically reconfigurable FPGA devices,

in Proc. of the 35* Southeastern Symposium on SystemTheory, Cookeville, TN, March 16-18, 2003.

[51 D. Mesquita, F. Moraes, J. Palma, L. Mailer and N. Calazans,Remote and partial reconfiguration of FPGAs: tools and trends,

in Proc. of the International Parallel and Distributed ProcessingSymposium, April 22-26, 2003.

[6] Z. Zvonar and J. Mitola,Software Radio Technologies,

May 2001, Wiley-IEEE Press.

[7] E. Grayver and P. Dafesh,Multi-modulation programmable transceiver system withturbo coding,

in Proc. of the IEEE Aerospace Conference,Big Sky, MT. March 5-12, 2005.

[8] Xilinx Virtex-4 Configuration Guide, www.xilinx.com..

[9] www.turboconcept.com.

[10] P. .lames-Roxby and S.A. Guccione,Automated extraction of run-time parameterisable cores fromprogrammable device configurations,

in Proc. of the IEEE Symposium on Field-ProgrammableCustom Computing Machines,Napa Valley, CA, April 17-19, 2000.

[11] E. Horta, J.W. Lockwood, D.E. Taylor and D. Parlour,Dynamic hardware plugins in an FPGA with partial run-timereconfiguration,

in Proc. of the Design Automation Conference,

June 10-14,2002. A



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