psec-4 waveform digitizing asic + analog card · 2015. 9. 23. · analog bandwidth 1.6 ghz adc...
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PSEC-4 Waveform Digitizing ASIC + Analog Card
Eric Oberla
LAPPD collab meeting III
9-Dec-2011
Front-end of SuperModule DAQ system
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PSEC-4
ACTUAL PERFORMANCE
Sampling Rate 2.5-15 GSa/s
# Channels 6
Sampling Depth 256 points (17-100 ns)
Input Noise <1 mV RMS
Analog Bandwidth 1.6 GHz
ADC conversion Up to 12 bit @ 1.5 GHz
Dynamic Range 0.1-1.1 V
Latency 2 µs (min) – 16 µs (max)
Internal Trigger yes
• Waveform digitizing ASIC
• Sampling rate capability > 10GSa/s
• Analog bandwidth > 1 GHz
• Medium event-rate capability (up to ~100 KHz)
800MHz sine @ 13.3 GS/s
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PSEC-4
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PSEC-4 architecture
Charge pump
Phase Compa-rator
To switched capacitor array – sample & hold
locked sampling @ 10GSa/s w/ on chip DLL……
Timing generation with a delay locked loop (DLL):
• 1536x parallel Wilkinson ADC (entire chip)
• Region of interest readout (40 MHz) -> data to FPGA
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Evaluation Card• 4 boards made (3 available in this time zone)
6 channels (1 PSEC-4) per board
• USB 2.0 interface • Current firmware revision – 2• Acquisition software available with oscilloscope GUI
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PSEC-4 Performance
σ ~ 0.75mV
Noise
Frequency
Response
f3dB = 1.6 GHz
• Low noise <1 mV
• ~1V dynamic range with excellent linearity
• Analog bandwidth of 1.6 GHz
• Sampling rates up to 15 GSa/s
DC Response
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PSEC-4 timing (preliminary)• Without time base calibration (assuming nominal 100 ps per
sample interval)• Time jitter measured at DLL output ~ 13 ps• Sample several hundred Gaussian waveforms on 2 channels :
2 -channel timing (over entire window ~10ps sigma)
Data from 1 channel shown
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PSEC-4 timing (preliminary)• Without time base calibration (assuming nominal 100 ps per sample
interval)• Sample several hundred Gaussian waveforms on 2 channels:
2 channel timing (window subset - 3.8ps sigma)
Working out various time-base calibration methods with Kurtis Nishimura (UH) --should be implemented soon!
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Argonne Test Stand• Working to implement PSEC-4 eval at laser lab (APS)
First pulses from 33mm MCP set-up captured with PSEC-4 @ 10GS/s
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Argonne Test Stand• Some 33 mm MCP pulses :
• Still some noise/triggering issues to resolve before using PSEC-4 data for analysis. Coming soon…
Photodiode trigger
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Analog Card• 30 chan. PSEC-4 readout board, input matched to 30 strip anode
• Digital I/O and Power thru 240 pin SAMTEC ( digital card)
--boards due back next week--
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Analog Card• 30 chan. PSEC-4 readout board, input matched to 30 strip anode
• Digital I/O and Power thru 240 pin SAMTEC ( digital card)
--boards due back next week--
front back
2.3”
8.66”
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PSEC4
PSEC4
PSEC4
PSEC4
PSEC4
PSEC4
PSEC4
PSEC4
PSEC4
PSEC4
Analog Card – 5 PSEC-4 ASICs (30 channels)system ABW ~ 1 GHz (anode limited)-- 4 Analog Cards per module--flexibility allows for integration of alternative front-end
. ASICsPSEC4
PSEC4
PSEC4
PSEC4
PSEC4
PSEC4
PSEC4
PSEC4
PSEC4
PSEC4
Analog Card Super Module
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Analog Card Super Module
Analog (blue)+ Digital(yellow) cards mechanical mounting
Drawing courtesy of Rich Northrup
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Summary/plans
• PSEC-4 performance meets initial project goals of a (functional) high bandwidth, fast sampling ASIC
• Continued performance testing paper
• More data runs w/ 33mm & 8 inch MCP setup
- Integration of PSEC-4 data into analysis pipeline
- Any necessary firmware improvements
- Start PSEC-4/scope analysis comparison
• Analog Card back next week – waiting on digital card for full system testing, but preliminary tests/integration by the end of the year
• PSEC-5? Adding a deeper buffer and faster readout speed desired (reduce chip deadtime)
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DAQ systemLAPPD Collaboration
• Backside of Super Module:
Digital Card
Digital Card
Digital Card
Digital Card
Digital Card – 4 per module- PSEC-4 control, trigger handling, &
. calibration
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DAQ systemLAPPD Collaboration
• Backside of Super Module:
Digital Card
Digital Card
Digital Card
Digital CardFPGA
Center Card -System control-Clock distribution-Feature extraction -CPU interface
Gigabit Ethernet
Write pointer passed along array - generates ‘sampling window’ (~5-10 switches closed at once):
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Switched Capacitor Array Sampling
Input20fF
Tiny charge: 1mV ~ 100e-
Charge pump
Phase Compa-rator
To switched capacitor array – sample & hold
locked sampling @ 10GSa/s w/ on chip DLL……
Timing generation with a delay locked loop (DLL):
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Wilkinson ADC – easy to integrate on-chip