submicron scaling of iii-v hbts for 40-200 ghz analog & digital ics
DESCRIPTION
Submicron Scaling of III-V HBTs for 40-200 GHz Analog & Digital ICs. Mark Rodwell University of California, Santa Barbara . [email protected] 805-893-3244, 805-893-3262 fax. State-of-art in HBTs, 2000: cutoff frequencies. ~0.1 um emitters. ~1 um emitters (0.4 um). ~1 um emitters. - PowerPoint PPT PresentationTRANSCRIPT
Rodwell et al, UCSB: Keynote talk, 2000 IEEE Bipolar/BICMOS Circuits and Technology Meeting, Minneapolis, September
Submicron Scaling of III-V HBTs for 40-200 GHz Analog & Digital ICs
Mark RodwellUniversity of California, Santa Barbara
[email protected] 805-893-3244, 805-893-3262 fax
Rodwell et al, UCSB: Keynote talk, 2000 IEEE Bipolar/BICMOS Circuits and Technology Meeting, Minneapolis, September
State-of-art in HBTs, 2000: cutoff frequencies
Si / SiGe have significantly poorer material parameters …but are much better scaled in size and current density
0 50 100 150 200 250 300 350
Frequency, GHz
SiGe
InP
AlGaAs/GaAs & GaInP/GaAs
ft
fmax
ft
ft
fmax
fmax
~1 um emitters
~1 um emitters(0.4 um)
~0.1 um emitters
Rodwell et al, UCSB: Keynote talk, 2000 IEEE Bipolar/BICMOS Circuits and Technology Meeting, Minneapolis, September
State-of-Art in HBTs, 2000: small-scale circuits
0 20 40 60 80 100
Frequency, GHz
A
SiGe
InP
amplifiers
logic
logic
amplifiers
Si / SiGe has rough parity in logic with InP despite lower ft, fmaxdue to higher current density, better emitter contacts
Si/SiGe has significantly slower amplifiers due to lower ft, fmax
Si/SiGe has much better scales of integration, etc
Rodwell et al, UCSB: Keynote talk, 2000 IEEE Bipolar/BICMOS Circuits and Technology Meeting, Minneapolis, September
160 Gb/s is more than possible ! UCSB
160 Gb/s LIA simulations using UCSB HBT model
Zach Griffith
PortinNum=1
PortinnNum=2
PortoutnNum=3
PortoutNum=4
V_DCSRC1Vdc=Vee1 V
V_DCSRC2Vdc=Vee2 V
RR3R=Rf Ohm
RR4R=Rf Ohm
SHBT_594_modelX5Area=Area_ inAvia=Avia_ in
SHBT_594_modelX6Area=Area_ inAvia=Avia_ in
SHBT_594_modelX7Area=Area_ inAvia=Avia_ in
SHBT_ 594_modelX8Area=Area_ inAvia=Avia_ in
SHBT_594_modelX2Area=Area_2Avia=Avia_ 2
RR9R=Re1 Ohm
I_P robeI_P robe_ FBn
I_ P robeI_ P robe_CS1
I_P robeI_P_R2n
RR2R=Re2 Ohm
I_P robeI_P robe_CS2
RR8R=Re1 Ohm
I_ P robeI_ P robe_FB
I_P robeI_P_R2
SHBT_594_modelX1Area=Area_2Avia=Avia_2
RR1R=Re2 Ohm
I_P robeI_P robe_ in SHBT_ 594_model
X3Area=Area_1Avia=Avia_ 1
I_P robeI_P robe_ innSHBT_594_model
X4Area=Area_1Avia=Avia_ 1
RR7R=Rcs2 Ohm
RR10R=Rcs1 Ohm
RR11R=Ree Ohm
RR12R=Ree Ohm
RR5R=Rl Ohm
RR6R=Rl Ohm
PortinNum=1
PortinnNum=2
PortoutnNum=3
PortoutNum=4
V_DCSRC1Vdc=Vee1 V
V_DCSRC2Vdc=Vee2 V
RR3R=Rf Ohm
RR4R=Rf Ohm
SHBT_ 594_modelX5Area=Area_ inAvia=Avia_ in
SHBT_ 594_modelX6Area=Area_ inAvia=Avia_ in
SHBT_594_ modelX2Area=Area_ 2Avia=Avia_ 2
RR9R=Re1 Ohm
I_ P robeI_ P robe_FBn
I_ P robeI_ P robe_CS1
I_ P robeI_ P_R2n
RR2R=Re2 Ohm
I_P robeI_P robe_ CS2
RR8R=Re1 Ohm
I_ P robeI_ P robe_FB
I_ P robeI_ P_R2
SHBT_594_modelX1Area=Area_ 2Avia=Avia_ 2
RR1R=Re2 Ohm
I_P robeI_P robe_ in SHBT_ 594_model
X3Area=Area_1Avia=Avia_1
I_ ProbeI_ Probe_ innSHBT_594_ model
X4Area=Area_1Avia=Avia_1
RR7R=Rcs2 Ohm
RR11R=Ree Ohm
RR10R=Rcs1 Ohm
RR12R=Ree Ohm
RR5R=Rl Ohm
RR6R=Rl Ohm
SHBT_ 594_modelX7Area=Area_ inAvia=Avia_ in
SHBT_ 594_modelX8Area=Area_ inAvia=Avia_ in
0 1 2 3 4 5 6 7 8 9 10 11 12 13
time, psec
-0.22
-0.20
-0.18
-0.16
-0.14
-0.12
-0.10
-0.08
-0.06
-0.04
-0.02
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
0.22
out_
diff
0 1 2 3 4 5 6 7 8 9 10 11 12 13
time, psec
-0.22
-0.20
-0.18
-0.16
-0.14
-0.12
-0.10
-0.08
-0.06
-0.04
-0.02
0.00
0.02
0.04
0.06
0.08
0.10
0.12
0.14
0.16
0.18
0.20
0.22
out_
diff
AgilentConexant
Rodwell et al, UCSB: Keynote talk, 2000 IEEE Bipolar/BICMOS Circuits and Technology Meeting, Minneapolis, September
for x 2 improvement of all parasitics: ft, fmax, logic speed…base 2: 1 thinnercollector 2:1 thinneremitter, collector junctions 4:1 narrowercurrent density 4:1 higheremitter Ohmic 4:1 less resistive
Scaling Laws for fast HBTs
Challenges with Scaling:Collector mesa HBT: collector under base Ohmics. Base Ohmics must be one transfer lengthsets minimum size for collector Emitter Ohmic: hard to improve…how ?Current Density: dissipation, reliabilityLoss of breakdownavalanche Vbr never less than collector Egap (1.12 V for Si, 1.4 V for InP) ….sufficient for logic, insufficient for power
emitterbase contact
collectorcontact
SI substrate
InGaAs subcollector
InP collector
InGaAscollector
InP subcollector
InGaAs baseundercut
collector junction
base contactemitter
base contact
SI substrate
base
sub collector
base contact pad
collectorcontact
polymer polymer
collector-base junction
Narrow-mesa with 1E20 carbon-doped base
undercut-collector
transferred-substrate
Rodwell et al, UCSB: Keynote talk, 2000 IEEE Bipolar/BICMOS Circuits and Technology Meeting, Minneapolis, September
Submicron Transferred-Substrate HBT
0
5
10
15
20
25
30
10 100 1000
Gai
ns, d
B
Frequency, GHz
fmax
= 1.1 THzft = 204 GHz
Mason's gain, U
H21
MSG
emitter, 0.4 x 6 mm2
collector, 0.4 x 6 mm2
Ic = 6 mA, V
ce = 1.2 V
UCSBMichelle Lee
3000 Å collector400 Å base with 52 meV gradingAlInAs / GaInAs / GaInAs HBT
(?)
Rodwell et al, UCSB: Keynote talk, 2000 IEEE Bipolar/BICMOS Circuits and Technology Meeting, Minneapolis, September
Record ft HBT UCSBYoram Betser
Emitter 1 x 8 mm2, Collector 2 x 8.5 mm2.0
10
20
30
40
50
1 10 102
Gai
ns
(dB
)
Frequency (GHz)
h21
U
VCE
= 1 V, JC = 1.5 mA/um2
fMAX
= 295 GHz
f t = 295 GHz
2000 Å collector300 Å base with 52 meV gradingAlInAs / GaInAs / GaInAs HBT
Rodwell et al, UCSB: Keynote talk, 2000 IEEE Bipolar/BICMOS Circuits and Technology Meeting, Minneapolis, September
1E9 1E10 1E11 1E12
freq, Hz
-20
-15
-10
-5
0
5
10
15
20
dB(h
21)
UdB
(sho
rt..S
(2,1
))
m1freq=303.0GHzdB(short..S(2,1))=0.000
m1
m2freq=165.0GHzdB(short..S(2,1))=0.000
m2
0
1
2
3
4
5
6
7
8
0 1 2 3 4 5 6
Ic - V
ce characteristics
I c (mA
)
Vce
(volts)
IB in steps
of 20 uA 105 A/cm2
High Speed, High Breakdown DHBTs
ft = 165 GHz; fmax = 303 GHz
5 V breakdown at 105 A/cm2
UCSBpk SundararajanM Dahlstrom
0
5000
1 104
1.5 104
2 104
0 2 4 6 8 10
J c (A/c
m2 )
Vce
(volts)
BVCEO>9 V
1x 8 micron emitter, 2x 10 micron collector
Rodwell et al, UCSB: Keynote talk, 2000 IEEE Bipolar/BICMOS Circuits and Technology Meeting, Minneapolis, September
High Speed Amplifiers
18 dB, DC-50 GHz
UCSBDino Mensa
PK Sundararajan
8.2 dB, DC-80 GHz
-20
-15
-10
-5
0
5
10
15
20
0 10 20 30 40 50
397 GHz gain x bandwidth from 2 HBTs
S22
S11
S21
Rodwell et al, UCSB: Keynote talk, 2000 IEEE Bipolar/BICMOS Circuits and Technology Meeting, Minneapolis, September
HBT distributed amplifier UCSBPK Sundararajan11 dB, DC-87 GHz
AFOSR
TWA with internal ft-doubler cells
Rodwell et al, UCSB: Keynote talk, 2000 IEEE Bipolar/BICMOS Circuits and Technology Meeting, Minneapolis, September
InP-HBT W-band Amplifiers
Balanced Amplifier: 10.7dBm at 78GHz
(transferred-substrate HBT)
InGaAs-collector: Vbr=1.5 V low power
InP-collector: Vbr~5 V higher powers expected
UCSB AROCaltech
Common-Base Amplifier: 9.7dBm at 82.5 GHz
James Guthrie
Rodwell et al, UCSB: Keynote talk, 2000 IEEE Bipolar/BICMOS Circuits and Technology Meeting, Minneapolis, September
66 GHz HBT master-slave flip-flop
Objectives: 100 + GHz logic
Approach: transferred-substrate HBTs, microwave / digital design
Simulations: 95 GHz clock rate in SPICE
Accomplishments:operation to 66 GHz
UCSB
33.0 GHz static divider output at 66.0 GHz input
-100
-80
-60
-40
-20
0
0 50 100 150 200
divi
der o
utpu
t, m
V
time, ps
Michelle Lee
Rodwell et al, UCSB: Keynote talk, 2000 IEEE Bipolar/BICMOS Circuits and Technology Meeting, Minneapolis, September
UCSB3500-HBT 20 GHz Sine ROM
(it is hard to build large ICs in a university cleanroom)
input latches
decoder core
receivers & drivers
ROM core
selectors
receivers
output latches
Yoram BetserWOM
IVC
t
Iref
Ik
Low Voltage Swing
Digital Signal
Io
o
k
III
qkTV 0ln
Rodwell et al, UCSB: Keynote talk, 2000 IEEE Bipolar/BICMOS Circuits and Technology Meeting, Minneapolis, September
Delta-Sigma ADC18 GHz clock rate 150 HBTs
gm gm
Integrator
clock
(bias)Integrator
output M/SFlip flop
1 bitDAC
1 bitDAC
Input
(bias)
Delayed Clock
ADC BlockDiagram
-120
-100
-80
-60
-40
-20
0
1 10 100 1000 10000
Pow
er S
pect
rum
(dB
bel
ow fu
ll sc
ale)
Frequency (MHz)
InputOutput
OSR = 128F
clock = 20 GHz
SNR = 90 dB in 1 MHz
Matlab Simulation
<-signalADC noise
= 150 dB in 1 Hz
UCSB
6.2 ENOB for a 1 GHz signal( 2 GS/s equivalent Nyquist)
5 5
50 50
6.6K1.25K6.6K
250
1.25K
-4v
5 5
6.6K1.25K6.6K
250
1.25K
clock buffers
RTZ DAC
(transmission linedelay to setDAC gatiing clocktowards later half of the eye )
clock
M/S latched comparatormaster slave
integrator 1
integrator 2
(off-wafer op-amps setscommon-mode bias)
(off-wafer op-amps setscommon-mode bias)
input
clock
delayedclock
Shrinivasan Jaganathan
Rodwell et al, UCSB: Keynote talk, 2000 IEEE Bipolar/BICMOS Circuits and Technology Meeting, Minneapolis, September
185 GHz HBT Amplifier UCSBMiguel Urteaga
0.2pF
50 301.2ps
50
300.2ps
801.2ps
0.6ps
801.2ps
50
IN
OUT
140 150 160 170 180 190 200 210 220Frequency, GHz
-5-4-3
-2-101
234
S21,
dB
140 150 160 170 180 190 200 210 220
Frequency, GHz
-18
-16
-14
-12
-10
-8
-6
-4
-2
0
S11,
S22,
dB
S22
S11
AFOSR
Rodwell et al, UCSB: Keynote talk, 2000 IEEE Bipolar/BICMOS Circuits and Technology Meeting, Minneapolis, September
19 GHz 2-bit adder UCSBThomas Mathew
C1C1
C1out = A0B0 + B0C0 + A0C0
C1out = A0B0 + B0C0 + A0C0
C1 C1
C1 C1
DIODE LEVEL SHIFTER
C0
B0
C0
B0
B0 B0
C0 C0
A0 A0
CK CK
LOGIC STAGE
C1 C1
B1 B1
C1 C1
B1 B1
A1 A1
CKCK
C2out = A1B1 + B1C1 + A1C1C2out = A1B1 + B1C1 + A1C1
LATCHSTAGE
B0 = B1 = High (0.0V), A0 = A1 = Low (-0.3V), C0 = C2out for testing
-0.3
-0.25
-0.2
-0.15
-0.1
-0.05
0
0 100 200 300 400 500
fmax ck
= 19GHz, fout
= 9 .5GHz
Vou
t(Vol
ts)
Time(ps)
S0 = A0 + B0 + C0
S0 = A0 + B0 + C0
C0 C0
C0
B0 B0
B0
A0 A0
CK CK CKCK
3 INPUT XOR
LATCHSTAGE
LATCH FOR PIPELINE DELAY
C0 = High (0.0V), A0 = Low (-0.3V), B0 = S0 for testing