project report
TRANSCRIPT
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• Introduction to Flash Memories• Flash memory fault models
- Disturbance faults
- Conventional memory faults• Flash memory test algorithms
- March-like test/diagnosis algorithms
- Diagonal test/diagnosis algorithm• Flash memory BIST• Flash memory BISD• Conclusion
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INTRODUCTION
Flash memory testing is challenging,• Rapid scaling down of technology• Floating gate reliability issue.
APPROACHES TO TEST FLASH• Reasonable fault models• Efficient test algorithms• Built-in self-test (BIST)/Built-in self-diagnosis
(BISD)
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Flash Memory Program and Erase
• Program(1 to 0): channel hot-electron (CHE) injection or Fowler-Nordheim (FN) electron tunneling
• Erase (0 to 1): FN electron tunneling• By the entire chip or large blocks (flash erasure)
PROGRAM – WRITE 0
ERASE – WRITE 1
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FLASH DISTURBANCES• Program Disturbances
Word-Line Erase Disturbance
Word-line Program Disturbance
Bit-line Program Disturbance
Bit-line Erase Disturbance• Read disturbances• Over erase/program
disturbance
PROGRAM DISTURBANCES
READ DISTURBANCES
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CONVENTIONAL MEMORY FAULT
• Address-Decoder Fault (AF)• Stuck-At Fault (SAF)• Transition Fault (TF)• Stuck-Open Fault (SOF)• Bridging Fault (BF)
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ALGORITHM NOTATION
• r0 : read 0 from a memory location• r1 : read 1 from a memory location• w0 : write 0 to a memory location• w1 : write 1 to a memory location• ⇑ : increasing memory addressing• ⇓ : decreasing memory addressing• ⇕ : either increasing or decreasing
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TEST ALGORITHMS
• March-C Algorithm
{ (w0); (r0,w1); (r1,w0); (r0); (r0,w1⇕ ⇑ ⇑ ⇕ ⇓); (r1,w0); (r0)}⇓ ⇕
- All faults not detected• March-Based Flash Test: March-FT
(f); (r1,w0,r0); (r0);(f); (r1,w0,r0); (r0)⇓ ⇕ ⇑ ⇕- Address decoder faults and coupling
faults not detected
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MARCH ALGORITHMS
• Modified March-like Algorithm• Step1: f; {w1}; B{f,{rB'1}}⇑ ⇑• Step2:
f; {r0,w1}; {r1};f; {r0,w1}; {r1}⇑ ⇑ ⇓ ⇓- Source line interconnect faults (SLIF)
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DIAGONAL ALGORTIHM• Diagonal Test
{(f); !D1(r1,w0,r0); D1(r1,w0,r0); !D1(r0);⇑ ⇑ ⇑(f); D1(r1,w0,r0); !D1(r1); D2(r1,w0,r0);⇓ ⇑ ⇓
⇑D1(r0)}
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DIAGNOSITIC ALGORTIHM• Diagonal-FD
{(f); D1(w0; i,!D1(r1); j!D1(r1));⇑ ⇑ ⇑⇓D2(w0; i,D1(r1); j,D1(r1)); !D1(w0);⇑ ⇑ ⇑
⇑D1(w0; i,!D1(r0); j,!D1(r0));⇑ ⇑(f); D2(w0; i,D1(r0); j,D1(r0))}⇓ ⇑ ⇑
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TYPES OF BIST
• Hardwired BIST- Custom Circuitry• Soft BIST- Exploits the processor• Programmable BIST- Mixture of hardwired BIST and soft BIST
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BIST• Allows to perform self-testing• Reduce dependence on an external automated test equipment (ATE)
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TPG State Diagram
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BISD
BISD - includes a BIST module, extra circuitry to generate the fault signatures to support diagnostics.
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BISD Architecture
• High Voltage (HI-V) Tests- TExecution(HI-V Erase) < TExecution(Erase)
• Internal Parallel Test- Test time is reduced by approximately 64%
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CONCLUSION• Flash memory fault models and test algorithms
are proposed
− Both march-based and diagonal tests are effective
• Flash memory BIST/BISD is feasible- Use BIST to reduce the number of test pins- Use BISD to support diagnosis• Futurescope
− Diagnosis methodology for flash memories
− BISR
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References• [1]Piero Olivo, Marcello Dalpasso, “Self-Learning Signature Analysis for Non-Volatile Memory Testing,” International Test Conference, 1996.• [2]Mohammad Gh. Mohammad, Kewal K. Saluja, Alex Yap, “TestingFlash Memories,” Proc. 21st International Conference on VLSI Design,2008.• [3]G. Giglio, T. Masi, M. Mastrocola, F. Morgana , “A New Approach In Flash-Memory Testing To Increase Quality And Reduce Cycle Time On Improvements ” ,
International Integrated Reliability Workshop Final Report, 2002.• [4]Vincenzo Mastrocola, Gaetano Palumbo, Promod Kumar, Francesco Pipitone, Giuseppe Introvaia, “Built In Self Test for low cost testing of a 60MHz synchronous Flash
Memory ” , Proc. Seventh International On- Line Testing Workshop, 2001.• [5]Jen-Chieh Yeh, Chi-Feng Wu, Kuo-Liang Cheng, Yung-Fa Chou , “Flash Memory Built-In Self-Test Using March-Like Algorithms ”, Proc. of the First IEEE International
Workshop on Electronic Design, Test and Applications (DELTA’02)• [6]Sau-Kwo Chiu, Jen-Chieh Yeh, Chih-Tsun Huang, and Cheng-Wen Wu , “Diagonal Test and Diagnostic Schemes for Flash Memories ”, Proc. ITC International Test
Conference• [7]Chih-Sheng Hou and Jin-Fu Li , “Disturbance Fault Testing on Various NAND Flash Memories ”, Proc. 2012 17th IEEE European Test Symposium (ETS) .• [8]P. Bernardi, M. Rebaudengo, M. Sonza Reorda, M. Violante , “A P1500-compatible programmable BIST approach for the test of Embedded Flash Memories ”, Proc.
Design,Automation and Test in Europe Conference and Exhibition (DATE’03)• [9] Stefano Gregori, Alessandro Cabrini, Osama Khouri, Guido Torelli, ”On-Chip Error Correcting Techniques for New-Generation Flash Memories ”, Proc. Of The Ieee, Vol.
91, No. 4, April 2003 .• [10]Mohammad Gh. Mohammad and Laila Terkawi . “Fault Collapsing for Flash Memory Disturb Faults ”,Proc. European Test Symposium (ETS’05)• [11]Kaname Yamasaki, Iwao Suzuki, Azumi Kobayashi, Keiichi Horie, Yasuharu Kobayashi, Hideyuki Aoki, Hideki Hayashi, Kenichi Tada, Koki Tsutsumida, Keiichi Higeta,
“External Memory BIST for System-in- Package ”, Proc. International Test Conference .• [12]Shibaji Banerjee , Dipanwita Roy Chowdhury , “Built-In Self-Test for Flash Memory Embedded in SoC ”, Proc. of the Third IEEE International Workshop on Electronic
Design, Test and Applications (DELTA’06)• [13]Jen-Chieh Yeh, Yan-Ting Lai, Yuan-Yuan Shih and Cheng-Wen Wu , “Flash Memory Built-In Self-Diagnosis with Test Mode Control ”, Proceedings of the 23rd IEEE
VLSI Test Symposium (VTS’05) .• [14]Mu-Hsien Hsu, Yu-Tsao Hsing, Jen-Chieh Yeh, and Cheng-Wen Wu , “Fault-Pattern Oriented Defect Diagnosis for Flash Memory ”, Proceedings of the 2006 IEEE
International Workshop on Memory Technology, Design, and Testing (MTDT’06) .• [15]Wei-Lun Wang Zheng-Wei Song , “An Automatic Design for Flash Memory Testing ”, IEEE International Workshop on Memory Technology, Design, and Testing, 2006.
MTDT '06. 2006.• [16]Jen-Chieh Yeh, Kuo-Liang Cheng, Yung-Fa Chou and Cheng-Wen Wu, “Flash Memory Testing and Built-In Self Diagnosis With March- Like Test Algorithm”, Proc. IEEE
Transactions on Computer-Aided Design of Integrated Circuits and Systems.• [17]Stefano DI CARLO, Michele FABIANO, Roberto PIAZZA, Paolo PRINETTO , “Exploring Modeling and Testing of NAND Flash memories ”, Design & Test Symposium
(EWDTS), 2010 East-West.• [18]Yu-Ying Hsiao, Chao-Hsun Chen, and Cheng-Wen Wu, ”Built-In Self-Repair Schemes for Flash Memories ”, Proc. Computer-Aided Design Of Integrated Circuits And
Systems, Vol. 29, No. 8, August 2010 .• [19]Che-Wei Chou, Chih-Sheng Hou, and Jin-Fu Li , “Built-In Self-Diagnosis and Test Time Reduction Techniques for NAND Flash Memories ”, International Symposium on
VLSI Design, Automation and Test (VLSI-DAT), 2011.• [20]Ji Hyuck Yun, Jin Hyuk Yoon, Eyee Hyun Nam, and Sang Lyul Min , “An Abstract Fault Model for NAND Flash Memory ”, Proc. Embedded Systems Letters, Vol. 4, No.
4, December 2012 .• [21]M. Marinescu, “Simple and efficient algorithms for functional RAM testing," Proc. International Test Conference.• [22]C.-F. Wu, C.-T. Huang, K.-L. Cheng, and C.-W. Wu, “Simulationbased test algorithm generation for random access memories”, in Proc.IEEE VLSI Test Symp. (VTS),
Montreal, Apr. 2000 .
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THANK YOU!