Project 2 8 Bit ALU

To directly quote Wikipedia, because they have an excellent description that we never could have put into words, “In computing, an arithmetic and logic unit (ALU) is a digital circuit that performs arithmetic and logical operations. The ALU is a fundamental building block of the central processing unit of a computer, and even the simplest microprocessors contain one for purposes such as maintaining timers. The processors found inside modern CPUs and graphics processing units (GPUs) accommodate very powerful and very complex ALUs; a single component may contain a number of ALUs.

Mathematician John von Neumann proposed the ALU concept in 1945, when he wrote a report on the foundations for a new computer called the EDVAC. Research into ALUs remains an important part of computer science, falling under Arithmetic and logic structures in the ACM Computing Classification System.”

Our ALU is made up of three 1-bit 8-1 MUX, eight components for each calculation, and one 8-bit 8-1 MUX. We built the 8-to-1 MUX with a hierarchical design. We combined the results of a broken down 8-bit bus into bit-wise AND, and, OR gates to produce the 8-to-1 bus.

The three 1-bit multiplexers are responsible for c_out, output overflow and sign bit, all of which are controlled by the input alu_sel. There also exists an enable switch which outputs zero when switched off regardless of any other entries.

We made sure that each AND and OR gate gives the right output. The decimal conversion of the bits in the waveform shown is for the bit-wise operation.

http://en.wikipedia.org/wiki/Computinghttp://en.wikipedia.org/wiki/Digital_circuithttp://en.wikipedia.org/wiki/Arithmetichttp://en.wikipedia.org/wiki/Logicalhttp://en.wikipedia.org/wiki/Central_processing_unithttp://en.wikipedia.org/wiki/Central_processing_unithttp://en.wikipedia.org/wiki/Microprocessorhttp://en.wikipedia.org/wiki/Graphics_processing_unithttp://en.wikipedia.org/wiki/John_von_Neumannhttp://en.wikipedia.org/wiki/EDVAChttp://en.wikipedia.org/wiki/Computer_sciencehttp://en.wikipedia.org/wiki/ACM_Computing_Classification_Systemhttp://en.wikipedia.org/wiki/ACM_Computing_Classification_System

8 Bit OR:

8 BIT OR WAVEFORM:

The output is the larger of the two inputs. Also note, this will be the output of the ALU when the selector hits zero, remember that as we go along.

8 BIT AND:

8 BIT AND WAVEFORM:

The AND gates output only bits that are present at the same bit location in both inputs. And like with the above, note that this is the output of the ALU when the selector hits 5 (rather than 0 in the previous case).

Another subdesign we needed to form the multiplexer was a 4-input 8-bit AND gate with one output. The creation of the AND makes the design of the multiplexer much easier. The output was derived by sending all four inputs through the And gates, by using the 8-bit AND subdesign.

4-input 8-bit AND DESIGN:

4-input 8-bit AND WAVEFORM:

The waveform shows us that the ANDing of the four inputs is correct.

The final subdesign is the selector, we have 3-bit selector to output three bits separately. The diagram below shows the input separated into three separate wires and each then connected to individual 8-bit buses. The waveform shows that the values in the alu_sel are separated.

Alu_select:

Alu_select WAVEFORM:

The other half of the selector is the inverter which basically takes individual bits in the bus and outputs the inverse, waveform also shown below the schematic.

8 bit inverter:

8 bit Inverter WAVEFORM:

s0 s1 s2 Select Output 0 0 0 A + B 0 0 1 ~A 0 1 0 A + ~B + c_in 0 1 1 A + B + c_in 1 0 0 AxorB 1 0 1 AB 1 1 0 A-1+c_in 1 1 1 A + c_in

The table above helps us recognize what values of the alu selector correspond to which input. The first three rows correspond to an individual bit from alu_sel input, which gives us the result wanted in the multiplexer. Finally, we add an enable switch, since the multiplexer produces

the main output. For instance, the inverter used above the table would fall under the select output of 1.

8 bit 8-to-1 multiplexer:

8 bit 8-to-1 multiplexer WAVEFORM:

The proper output is sent depending on the alu_sel input when enable is turned on, as shown in the waveform above. As noted previously when alu_sel is 0, the function the output is supposed to represent is the 8 bit or subdesign made earlier.

When alu_sel is 1, the function the output is supposed to represent is a NOT A (aka, the 8bit inverter we listed above).

Moving on, you have the case for when the selector hits 2. This is where A+NOTB+c_in comes into play. The design for that thing looks like this:

A+NOTB+c_in:

A+NOTB+c_in WAVEFORM:

For any case that c_in is one, we then see that a subtraction is made, we see in the waveform, the beginning shows A is 143, B is 132, so not ~B would be 123. Since c_in is off, we are adding 143 and 132, this is equal to 10: the output, plus 256, c_out.

When the selector hits 3, it’s pretty much the same as when the selector hits 2, except in this instance, B = 1 instead of zero, making it A+B+c_in.

A+B+c_in:

A+B+c_in WAVEFORM:

As you can see, it’s nearly the exact same as in case three, except we are not using an inverter on B.

Moving on, let’s say the ALU selector picks the number 4, when alu_sel hits 4, the outcome becomes XOR (in this case AxorB).

AxorB:

AxorB WAVEFORM:

Applying a truth table to the above function gives you this result:

A B AxorB O O O O 1 1 1 O 1 1 1 O

As noted above, when the selector hits 5, you then use the 8bit AND gate

Now when the selector hits 6, then you absolutely must use the “A-1 + c_in” output.

A-1 + c_in:

A-1 + c_in WAVEFORM:

Finally we have the case of when the alu_sel is 7, it then gives you the “A+c_in” output (which is really just a simple use of the adder application we created in the last project, it probably would have been more efficient if we just used the 8 bit adder, but we didn’t think to do it until the last minute and the test cases have already been written!).

A+c_in:

A+c_in WAVEFORM:

Initially A is 255 and c_in is 0, so the output becomes 255. When c_in is turned off, the output goes to 0, and now c_out is on, so our new answer is 256. Immediately after this, the overflow flag comes on which is expected.

And with that, our ALU is completed and created:

References:

http://en.wikipedia.org/wiki/Arithmetic_Logic_Unit

Mano, M. Morris, and Charles R. Kime. "4." Logic and computer design fundamentals. 4. ed. Toronto: Pearson Prentice Hall.

http://en.wikipedia.org/wiki/Arithmetic_Logic_Unit