www.sagax.huwww.sagax.huSagax, Sagax, LtdLtd..

HallerHaller u. 11u. 11--13.13.

1096 Budapest, HUNGARY1096 Budapest, HUNGARY

Digital ConvertersDigital Converters

CH1

PCIHOST

Interface

PCI BUS connector

FPGALOGIC and DSP

resource

MCUConfigEEPROM

ControlEEPROM

PROM JTAG

FPGA JTAG

Dedicateddata

connection

RS-232serial controlinterface

Front-endBUS

ControlBUS

CLK DRVX2/X4/X8SCLK OSC

10MHz

ExternalCLK in/out

LCLK OSC 33MHz

SamplingCLK

LocalCLK

I2C

FPGA CFG

SamplingCLK

for converters

Differentconversionfront-end

configurations

ExternalTRG in/out

CH2

CH3

CH4

FIFO FPGAADCAnalogpreamp

FIFO FPGADACAnalogdriver

WIDE-BAND

(Di rect sampled)RX

TX

Full bandwidth

FIFO FPGAADCAnalogpreamp

FIFO FPGADACAnalogdriver

WIDE-BAND

(Di rect sampled)RX

TX

Full bandwidth

Members of the converter family

Universal digital converter family for wide-band and phased array software radio applications

DCUDCU--214:214:

Max. 4 analog I/O channelsMax. 4 analog I/O channels

Max. 2 independent channelsMax. 2 independent channels

1 clock I/O channel1 clock I/O channel

80Msps/14bit sampling80Msps/14bit sampling

500MHz bandwidth500MHz bandwidth

XilinxXilinx Spartan II FPGASpartan II FPGA

32bit/33MHz PCI interface32bit/33MHz PCI interface

133Mbyte/sec signaling rate133Mbyte/sec signaling rate

The members of the converter product family are based on the same

digital back-end base structure. We offer two basic conversion front-

end structure for wide-band and channelised applications.

Matlab based time and frequency domain analiser toolOpen application Programming Interface (API) and sample code areavailable for developers

DDC FPGAADCAnalogpreamp

DUC FPGADACAnalogdriver

NARROW- BAND

(Channelized)RX

TX

Reduced bandwidth

DDC FPGAADCAnalogpreamp

DUC FPGADACAnalogdriver

NARROW- BAND

(Channelized)RX

TX

Reduced bandwidth

In wide-band the samples are available trough a FIFO for the

FPGA/DSP processing elements

In narrow-band (channelised) version DDC/DUC chips are used for

selecting the required channel and reduce the bandwidth

DCUDCU--214:214:

Max. 4 analog I/O channelsMax. 4 analog I/O channels

Max. 4 independent digital tunerMax. 4 independent digital tuner

1 clock I/O channel1 clock I/O channel

80Msps/14bit sampling80Msps/14bit sampling

500MHz bandwidth500MHz bandwidth

XilinxXilinx Spartan II FPGASpartan II FPGA

32bit/33MHz PCI interface32bit/33MHz PCI interface

133Mbyte/sec signaling rate133Mbyte/sec signaling rate

DCUDCU--304:304:

Max. 4 analog I/O channelsMax. 4 analog I/O channels

1 clock I/O channel1 clock I/O channel

80Msps/14bit sampling80Msps/14bit sampling

500MHz bandwidth500MHz bandwidth

80 bit front80 bit front--end busend bus

XilinxXilinx VirtexVirtex II FPGAII FPGA

64bit/66MHz PCI interface64bit/66MHz PCI interface

528Mbyte/sec signaling rate528Mbyte/sec signaling rate

DRUDRU--304:304:

Max. 16 independent analog Max. 16 independent analog

I/O channelsI/O channels

1 clock I/O channel1 clock I/O channel

80Msps/14bit sampling80Msps/14bit sampling

500MHz bandwidth500MHz bandwidth

XilinxXilinx VirtexVirtex II FPGAII FPGA

Max. 16 independent Max. 16 independent

digital tunerdigital tuner

Software support