pipeline demo control
DESCRIPTION
Pipeline Demo CONTROL. WB. WB. M. M. ADD. EX. ADD. ZERO. ALU. RESULT. PC. INSTRUCTION MEMORY. ADDRESS. INSTRUCTION. 1. MUX. 0. 0. MUX. 1. MIPS: 5-Stage Pipeline. PCSrc. EX/MEM. MEM/WB. ID/EX. WB. 0. RegWrite. MemToReg. MUX. CONTROL. Branch. 1. MemRead. MemWrite. - PowerPoint PPT PresentationTRANSCRIPT
Pipeline DemoCONTROL
INSTRUCTIONMEMORY
ADDRESS INSTRUCTION
REGISTERS
READ REGISTER 1 /
READ REGISTER 2
WRITE REGISTER
WRITE DATA
READ DATA 1
READ DATA 2
DATAMEMORY
ADDRESS
WRITE DATA
READDATA
ALU
ZERO
RESULT
ADD
ADD
PC
4
MU
X
0
1
EX
M
WBRegWriteMemToRegC
ON
TR
OL
BranchMemRead
MemWrite
RegDstALUOpALUSrc
MU
X
0
1
ALUCONTROL
Sign Extend
MU
X
0
1I[15-11]
I[20-16]
I[15-0]
M
WB WB
MU
X
1
0
RegWrite
Mem
ToR
eg
<< 2 Mem
Rea
d Mem
Writ
e
Branch
PCSrc
IF/ID
ID/EX EX/MEM MEM/WB
MIPS: 5-Stage Pipeline
ALUOp
RegDst
ALUSrc
Zero
I[5-0]
Stage 1: Instruction Fetch
INSTRUCTIONMEMORY
ADDRESS INSTRUCTION
REGISTERS
READ REGISTER 1 /
READ REGISTER 2
WRITE REGISTER
WRITE DATA
READ DATA 1
READ DATA 2
DATAMEMORY
ADDRESS
WRITE DATA
READDATA
ALUZERO
RESULT
ADD
ADD
PC
4
MU
X
0
1
EX
M
WBRegWriteMemToRegC
ON
TR
OL
BranchMemRead
MemWrite
RegDstALUOpALUSrc
MU
X
0
1
ALUCONTROL
Sign Extend
MU
X
0
1I[15-11]
I[20-16]
I[15-0]
M
WB WB
MU
X
1
0
RegWrite
Mem
ToR
eg
<< 2 Mem
Rea
d Mem
Writ
e
Branch
PCSrc
IF/ID
ID/EX EX/MEM MEM/WB
Stage 2: Instruction Decode (and Register Fetch)
INSTRUCTIONMEMORY
ADDRESS INSTRUCTION
DATAMEMORY
ADDRESS
WRITE DATA
READDATA
ALUZERO
RESULT
ADD
ADD
PC
4
MU
X
0
1
MU
X
0
1
ALUCONTROL
MU
X
0
1
M
WB WB
MU
X
1
0
Mem
ToR
eg
<< 2 Mem
Rea
d Mem
Writ
e
Branch
PCSrc
EX/MEM MEM/WB
REGISTERS
READ REGISTER 1 /
READ REGISTER 2
WRITE REGISTER
WRITE DATA
READ DATA 1
READ DATA 2
EX
M
WBRegWriteMemToRegC
ON
TR
OL
BranchMemRead
MemWrite
RegDstALUOpALUSrc
Sign Extend
I[15-11]
I[20-16]
I[15-0]
RegWrite
IF/ID
ID/EX
Stage 3: Execute (or ALU Operation)
INSTRUCTIONMEMORY
ADDRESS INSTRUCTION
REGISTERS
READ REGISTER 1 /
READ REGISTER 2
WRITE REGISTER
WRITE DATA
READ DATA 1
READ DATA 2
DATAMEMORY
ADDRESS
WRITE DATA
READDATA
ADD
PC
4
MU
X
0
1
RegWriteMemToRegC
ON
TR
OL
BranchMemRead
MemWrite
RegDstALUOpALUSrc
Sign Extend
I[15-11]
I[20-16]
I[15-0]
WB
MU
X
1
0
RegWrite
Mem
ToR
eg
Mem
Rea
d Mem
Writ
e
Branch
PCSrc
IF/ID
MEM/WB
ALU
ZERO
RESULT
ADD
EX
M
WB
MU
X
0
1
ALUCONTROL
MU
X
0
1
M
WB
<< 2
ID/EX EX/MEM
ALUOp
RegDst
ALUSrc
I[5-0]
Stage 4: Memory Access (and Branch Resolution)
INSTRUCTIONMEMORY
ADDRESS INSTRUCTION
REGISTERS
READ REGISTER 1 /
READ REGISTER 2
WRITE REGISTER
WRITE DATA
READ DATA 1
READ DATA 2 ALU
ZERO
RESULT
ADD
ADD
4EX
M
WBRegWriteMemToRegC
ON
TR
OL
BranchMemRead
MemWrite
RegDstALUOpALUSrc
MU
X
0
1
ALUCONTROL
Sign Extend
MU
X
0
1I[15-11]
I[20-16]
I[15-0]
MU
X
1
0
RegWrite
Mem
ToR
eg
<< 2
PCSrc
IF/ID
ID/EX
DATAMEMORY
ADDRESS
WRITE DATA
READDATA
M
WB WB
Mem
Rea
d Mem
Writ
e
Branch
EX/MEM MEM/WB
PC
MU
X
0
1
Zero
Stage 5: Write Back
INSTRUCTIONMEMORY
ADDRESS INSTRUCTION
DATAMEMORY
ADDRESS
WRITE DATA
READDATA
ALUZERO
RESULT
ADD
ADD
PC
4
MU
X
0
1
EX
M
WBRegWriteMemToRegC
ON
TR
OL
BranchMemRead
MemWrite
RegDstALUOpALUSrc
MU
X
0
1
ALUCONTROL
Sign Extend
MU
X
0
1I[15-11]
I[20-16]
I[15-0]
M
WB
RegWrite
Mem
ToR
eg
<< 2 Mem
Rea
d Mem
Writ
e
Branch
PCSrc
IF/ID
ID/EX EX/MEM
WB
MEM/WB
MU
X
1
0
REGISTERS
READ REGISTER 1 /
READ REGISTER 2
WRITE REGISTER
WRITE DATA
READ DATA 1
READ DATA 2
Following a Load Instruction – Clock Cycle 1
INSTRUCTIONMEMORY
ADDRESS INSTRUCTION
REGISTERS
READ REGISTER 1 /
READ REGISTER 2
WRITE REGISTER
WRITE DATA
READ DATA 1
READ DATA 2
DATAMEMORY
ADDRESS
WRITE DATA
READDATA
ALUZERO
RESULT
ADD
ADD
PC
4
MU
X
0
1
EX
M
WBRegWriteMemToRegC
ON
TR
OL
BranchMemRead
MemWrite
RegDstALUOpALUSrc
MU
X
0
1
ALUCONTROL
Sign Extend
MU
X
0
1I[15-11]
I[20-16]
I[15-0]
M
WB WB
MU
X
1
0
RegWrite
Mem
ToR
eg
<< 2 Mem
Rea
d Mem
Writ
e
Branch
PCSrc
IF/ID
ID/EX EX/MEM MEM/WB
LW before<1> before<2> before<4>before<3>
INSTRUCTIONMEMORY
ADDRESS INSTRUCTION
DATAMEMORY
ADDRESS
WRITE DATA
READDATA
ALUZERO
RESULT
ADD
ADD
PC
4
MU
X
0
1
MU
X
0
1
ALUCONTROL
MU
X
0
1
M
WB WB
MU
X
1
0
Mem
ToR
eg
<< 2 Mem
Rea
d Mem
Writ
e
Branch
PCSrc
EX/MEM MEM/WB
REGISTERS
READ REGISTER 1 /
READ REGISTER 2
WRITE REGISTER
WRITE DATA
READ DATA 1
READ DATA 2
EX
M
WBRegWriteMemToRegC
ON
TR
OL
BranchMemRead
MemWrite
RegDstALUOpALUSrc
Sign Extend
I[15-11]
I[20-16]
I[15-0]
RegWrite
IF/ID
ID/EX
Following a Load Instruction – Clock Cycle 2
after<1> LW before<1> before<3>before<2>
INSTRUCTIONMEMORY
ADDRESS INSTRUCTION
REGISTERS
READ REGISTER 1 /
READ REGISTER 2
WRITE REGISTER
WRITE DATA
READ DATA 1
READ DATA 2
DATAMEMORY
ADDRESS
WRITE DATA
READDATA
ADD
PC
4
MU
X
0
1
RegWriteMemToRegC
ON
TR
OL
BranchMemRead
MemWrite
RegDstALUOpALUSrc
Sign Extend
I[15-11]
I[20-16]
I[15-0]
WB
MU
X
1
0
RegWrite
Mem
ToR
eg
Mem
Rea
d Mem
Writ
e
Branch
PCSrc
IF/ID
MEM/WB
ALUZERO
RESULT
ADD
EX
M
WB
MU
X
0
1
ALUCONTROL
MU
X
0
1
M
WB
<< 2
ID/EX EX/MEM
ALUOp
RegDst
ALUSrc
Following a Load Instruction – Clock Cycle 3
LWafter<2> after<1> before<2>before<1>
INSTRUCTIONMEMORY
ADDRESS INSTRUCTION
REGISTERS
READ REGISTER 1 /
READ REGISTER 2
WRITE REGISTER
WRITE DATA
READ DATA 1
READ DATA 2 ALU
ZERO
RESULT
ADD
ADD
4EX
M
WBRegWriteMemToRegC
ON
TR
OL
BranchMemRead
MemWrite
RegDstALUOpALUSrc
MU
X
0
1
ALUCONTROL
Sign Extend
MU
X
0
1I[15-11]
I[20-16]
I[15-0]
MU
X
1
0
RegWrite
Mem
ToR
eg
<< 2
PCSrc
IF/ID
ID/EX
DATAMEMORY
ADDRESS
WRITE DATA
READDATA
M
WB WB
Mem
Rea
d Mem
Writ
e
Branch
EX/MEM MEM/WB
PC
MU
X
0
1
Zero
Following a Load Instruction – Clock Cycle 4
LWafter<3> after<2> before<1>after<1>
INSTRUCTIONMEMORY
ADDRESS INSTRUCTION
DATAMEMORY
ADDRESS
WRITE DATA
READDATA
ALUZERO
RESULT
ADD
ADD
PC
4
MU
X
0
1
EX
M
WBRegWriteMemToRegC
ON
TR
OL
BranchMemRead
MemWrite
RegDstALUOpALUSrc
MU
X
0
1
ALUCONTROL
Sign Extend
MU
X
0
1I[15-11]
I[20-16]
I[15-0]
M
WB
RegWrite
Mem
ToR
eg
<< 2 Mem
Rea
d Mem
Writ
e
Branch
PCSrc
IF/ID
ID/EX EX/MEM
WB
MEM/WB
MU
X
1
0
REGISTERS
READ REGISTER 1 /
READ REGISTER 2
WRITE REGISTER
WRITE DATA
READ DATA 1
READ DATA 2
Following a Load Instruction – Clock Cycle 5
LWafter<4> after<3> after<1>after<2>
Key Concept 1 – Long Registers to Preserve Each Step’s Results
INSTRUCTIONMEMORY
ADDRESS INSTRUCTION
REGISTERS
READ REGISTER 1 /
READ REGISTER 2
WRITE REGISTER
WRITE DATA
READ DATA 1
READ DATA 2
DATAMEMORY
ADDRESS
WRITE DATA
READDATA
ALUZERO
RESULT
ADD
ADD
PC
4
MU
X
0
1
EX
M
WBRegWriteMemToRegC
ON
TR
OL
BranchMemRead
MemWrite
RegDstALUOpALUSrc
MU
X
0
1
ALUCONTROL
Sign Extend
MU
X
0
1I[15-11]
I[20-16]
I[15-0]
M
WB WB
MU
X
1
0
RegWrite
Mem
ToR
eg
<< 2 Mem
Rea
d Mem
Writ
e
Branch
PCSrc
IF/ID
ID/EX EX/MEM MEM/WB
ALUOp
RegDst
ALUSrc
Zero
Key Concept 2 – Set Control Signals Once, Use Long Registers to Remember Them from Step to Step
INSTRUCTIONMEMORY
ADDRESS INSTRUCTION
REGISTERS
READ REGISTER 1 /
READ REGISTER 2
WRITE REGISTER
WRITE DATA
READ DATA 1
READ DATA 2
DATAMEMORY
ADDRESS
WRITE DATA
READDATA
ALUZERO
RESULT
ADD
ADD
PC
4
MU
X
0
1
EX
M
WBRegWriteMemToRegC
ON
TR
OL
BranchMemRead
MemWrite
RegDstALUOpALUSrc
MU
X
0
1
ALUCONTROL
Sign Extend
MU
X
0
1I[15-11]
I[20-16]
I[15-0]
M
WB WB
MU
X
1
0
RegWrite
Mem
ToR
eg
<< 2 Mem
Rea
d Mem
Writ
e
Branch
PCSrc
IF/ID
ID/EX EX/MEM MEM/WB
ALUOp
RegDst
ALUSrc
Zero
Key Concept 3 – Even Remember The Things You Don’t Need Right Away
INSTRUCTIONMEMORY
ADDRESS INSTRUCTION
REGISTERS
READ REGISTER 1 /
READ REGISTER 2
WRITE REGISTER
WRITE DATA
READ DATA 1
READ DATA 2
DATAMEMORY
ADDRESS
WRITE DATA
READDATA
ALUZERO
RESULT
ADD
ADD
PC
4
MU
X
0
1
EX
M
WBRegWriteMemToRegC
ON
TR
OL
BranchMemRead
MemWrite
RegDstALUOpALUSrc
MU
X
0
1
ALUCONTROL
Sign Extend
MU
X
0
1I[15-11]
I[20-16]
I[15-0]
M
WB WB
MU
X
1
0
RegWrite
Mem
ToR
eg
<< 2 Mem
Rea
d Mem
Writ
e
Branch
PCSrc
IF/ID
ID/EX EX/MEM MEM/WB
ALUOp
ALUSrc
Zero
Following a Set of Instructions
LW ____,____SUB ____,____,____BEQ ____,____,____ ; this branch will not be takenOR ____,____,____ADD ____,____,____
IF/ID
Following a Set of Instructions – Clock Cycle 1
LW before<1> before<2> before<3> before<4>
REGISTERS
READ REGISTER 1 /
READ REGISTER 2
WRITE REGISTER
WRITE DATA
READ DATA 1
READ DATA 2
DATAMEMORY
ADDRESS
WRITE DATA
READDATA
ALUZERO
RESULT
ADD
EX
M
WBRegWriteMemToRegC
ON
TR
OL
BranchMemRead
MemWrite
RegDstALUOpALUSrc
MU
X
0
1
ALUCONTROL
Sign Extend
MU
X
0
1I[15-11]
I[20-16]
I[15-0]
M
WB WB
MU
X
1
0
RegWrite
Mem
ToR
eg
<< 2 Mem
Rea
d Mem
Writ
e
Branch
ID/EX EX/MEM MEM/WB
INSTRUCTIONMEMORY
ADDRESS INSTRUCTION
ADD
PC
4
MU
X
0
1
PCSrc
Following a Set of Instructions – Clock Cycle 2
SUB LW before<1> before<2> before<3>
DATAMEMORY
ADDRESS
WRITE DATA
READDATA
ALUZERO
RESULT
ADD
MU
X
0
1
ALUCONTROL
MU
X
0
1
M
WB WB
MU
X
1
0
Mem
ToR
eg
<< 2 Mem
Rea
d Mem
Writ
e
Branch
EX/MEM MEM/WB
INSTRUCTIONMEMORY
ADDRESS INSTRUCTION
ADD
PC
4
MU
X
0
1
REGISTERS
READ REGISTER 1 /
READ REGISTER 2
WRITE REGISTER
WRITE DATA
READ DATA 1
READ DATA 2
EX
M
WBRegWriteMemToRegC
ON
TR
OL
BranchMemRead
MemWrite
RegDstALUOpALUSrc
Sign Extend
I[15-11]
I[20-16]
I[15-0]
RegWrite
IF/ID
ID/EX
PCSrc
Following a Set of Instructions – Clock Cycle 3
BEQ SUB LW before<1> before<2>
DATAMEMORY
ADDRESS
WRITE DATA
READDATA
WB
MU
X
1
0
Mem
ToR
eg
Mem
Rea
d Mem
Writ
e
Branch
MEM/WB
INSTRUCTIONMEMORY
ADDRESS INSTRUCTION
ADD
PC
4
MU
X
0
1
REGISTERS
READ REGISTER 1 /
READ REGISTER 2
WRITE REGISTER
WRITE DATA
READ DATA 1
READ DATA 2
RegWriteMemToRegC
ON
TR
OL
BranchMemRead
MemWrite
RegDstALUOpALUSrc
Sign Extend
I[15-11]
I[20-16]
I[15-0]
RegWrite
IF/ID
ALUZERO
RESULT
ADD
EX
M
WB
MU
X
0
1
ALUCONTROL
MU
X
0
1
M
WB
<< 2
ID/EX EX/MEM
ALUOp
RegDst
ALUSrc
PCSrc
Following a Set of Instructions – Clock Cycle 4
OR BEQ SUB LW before<1>M
UX
1
0
Mem
ToR
eg
INSTRUCTIONMEMORY
ADDRESS INSTRUCTION
ADD
PC
4
MU
X
0
1
REGISTERS
READ REGISTER 1 /
READ REGISTER 2
WRITE REGISTER
WRITE DATA
READ DATA 1
READ DATA 2
RegWriteMemToRegC
ON
TR
OL
BranchMemRead
MemWrite
RegDstALUOpALUSrc
I[15-11]
I[20-16]
RegWrite
IF/ID
ALUZERO
RESULT
ADD
EX
M
WB
MU
X
0
1
ALUCONTROL
MU
X
0
1
<< 2
ID/EX
ALUOp
RegDst
ALUSrc
Sign ExtendI[15-0] I[5-0]
DATAMEMORY
ADDRESS
WRITE DATA
READDATA
M
WB WB
Mem
Rea
d Mem
Writ
e
Branch
EX/MEMZ
ero
PCSrc
Following a Set of Instructions – Clock Cycle 5
ADD OR BEQ SUB LW
Mem
ToR
eg
INSTRUCTIONMEMORY
ADDRESS INSTRUCTION
ADD
PC
4
MU
X
0
1
ALUZERO
RESULTMU
X
0
1
ALUCONTROL
MU
X
0
1
ALUOp
RegDst
ALUSrc
I[5-0]
DATAMEMORY
ADDRESS
WRITE DATA
READDATA
M
WB WB
Mem
Rea
d Mem
Writ
e
Branch
EX/MEMZ
ero
PCSrc
ADD
<< 2
MU
X
1
0
REGISTERS
READ REGISTER 1 /
READ REGISTER 2
WRITE REGISTER
WRITE DATA
READ DATA 1
READ DATA 2
RegWriteMemToRegC
ON
TR
OL
BranchMemRead
MemWrite
RegDstALUOpALUSrc
Sign Extend
I[15-11]
I[20-16]
I[15-0]
RegWrite
IF/IDEX
M
WB
ID/EX
Following a Set of Instructions – Clock Cycle 6
after<1> ADD OR BEQ SUB
Mem
ToR
eg
INSTRUCTIONMEMORY
ADDRESS INSTRUCTION
ADD
PC
4
MU
X
0
1
DATAMEMORY
ADDRESS
WRITE DATA
READDATA
WB
Mem
Rea
d Mem
Writ
e
Branch
Zero
PCSrc
REGISTERS
READ REGISTER 1 /
READ REGISTER 2
WRITE REGISTER
WRITE DATA
READ DATA 1
READ DATA 2
RegWriteMemToRegC
ON
TR
OL
BranchMemRead
MemWrite
RegDstALUOpALUSrc
Sign Extend
I[15-11]
I[20-16]
I[15-0]
RegWrite
IF/ID
MU
X
1
0
ALUZERO
RESULT
ADD
EX
M
WB
MU
X
0
1
ALUCONTROL
MU
X
0
1
<< 2
ID/EX
ALUOp
RegDst
ALUSrc
I[5-0]
M
WB
EX/MEM
Following a Set of Instructions – Clock Cycle 7
after<2> after<1> ADD OR BEQ
Mem
ToR
eg
INSTRUCTIONMEMORY
ADDRESS INSTRUCTION
ADD
PC
4
MU
X
0
1
DATAMEMORY
ADDRESS
WRITE DATA
READDATA
WB
Mem
Rea
d Mem
Writ
e
Branch
Zero
REGISTERS
READ REGISTER 1 /
READ REGISTER 2
WRITE REGISTER
WRITE DATA
READ DATA 1
READ DATA 2
RegWriteMemToRegC
ON
TR
OL
BranchMemRead
MemWrite
RegDstALUOpALUSrc
Sign Extend
I[15-11]
I[20-16]
I[15-0]
RegWrite
IF/ID
MU
X
1
0
ALUZERO
RESULT
ADD
EX
M
WB
MU
X
0
1
ALUCONTROL
MU
X
0
1
<< 2
ID/EX
ALUOp
RegDst
ALUSrc
I[5-0]
M
WB
EX/MEM
Following a Set of Instructions – Clock Cycle 8
after<3> after<2> after<1> ADD OR
Mem
ToR
eg
INSTRUCTIONMEMORY
ADDRESS INSTRUCTION
ADD
PC
4
MU
X
0
1
DATAMEMORY
ADDRESS
WRITE DATA
READDATA
WB
Mem
Rea
d Mem
Writ
e
Branch
Zero
RegWriteMemToRegC
ON
TR
OL
BranchMemRead
MemWrite
RegDstALUOpALUSrc
Sign Extend
I[15-11]
I[20-16]
I[15-0]
RegWrite
IF/ID
MU
X
1
0
ALUZERO
RESULT
ADD
EX
M
WB
MU
X
0
1
ALUCONTROL
MU
X
0
1
<< 2
ID/EX
ALUOp
RegDst
ALUSrc
I[5-0]
M
WB
EX/MEM
MU
X
1
0
REGISTERS
READ REGISTER 1 /
READ REGISTER 2
WRITE REGISTER
WRITE DATA
READ DATA 1
READ DATA 2
Following a Set of Instructions – Clock Cycle 9
after<4> after<3> after<2> after<1> ADD
Mem
ToR
eg
INSTRUCTIONMEMORY
ADDRESS INSTRUCTION
ADD
PC
4
MU
X
0
1
DATAMEMORY
ADDRESS
WRITE DATA
READDATA
WB
Mem
Rea
d Mem
Writ
e
Branch
Zero
RegWriteMemToRegC
ON
TR
OL
BranchMemRead
MemWrite
RegDstALUOpALUSrc
Sign Extend
I[15-11]
I[20-16]
I[15-0]
RegWrite
IF/ID
MU
X
1
0
ALUZERO
RESULT
ADD
EX
M
WB
MU
X
0
1
ALUCONTROL
MU
X
0
1
<< 2
ID/EX
ALUOp
RegDst
ALUSrc
I[5-0]
M
WB
EX/MEM
MU
X
1
0
REGISTERS
READ REGISTER 1 /
READ REGISTER 2
WRITE REGISTER
WRITE DATA
READ DATA 1
READ DATA 2
INSTRUCTIONMEMORY
ADDRESS INSTRUCTION
REGISTERS
READ REGISTER 1 /
READ REGISTER 2
WRITE REGISTER
WRITE DATA
READ DATA 1
READ DATA 2
DATAMEMORY
ADDRESS
WRITE DATA
READDATA
ALUZERO
RESULT
ADD
ADD
PC
4
MU
X
0
1
EX
M
WBRegWriteMemToRegC
ON
TR
OL
BranchMemRead
MemWrite
RegDstALUOpALUSrc
MU
X
0
1
ALUCONTROL
Sign Extend
MU
X
0
1I[15-11]
I[20-16]
I[15-0]
M
WB WB
MU
X
1
0
RegWrite
Mem
ToR
eg
<< 2 Mem
Rea
d Mem
Writ
e
Branch
PCSrc
IF/ID
ID/EX EX/MEM MEM/WB