philips uociii-v1.8 manual entrenamiento

DATA SHEET

Preliminary specificationFile under Integrated Circuits, <Handbook>

2003 Nov 11

INTEGRATED CIRCUITS

UOCIII seriesVersatile signal processor for low-and mid-range TV applications

CONFIDENTIAL

DEVICE SPECIFICATION

Previous date: 2003 Oct 09Version: 18

2003 Nov 11 2

Philips Semiconductors Preliminary specification

Versatile signal processor for low- andmid-range TV applications UOCIII series

CONFIDENTIAL

GENERAL DESCRIPTION

The UOCIII series combines the functions of a VideoSignal Processor (VSP) together with a FLASH embeddedTEXT/Control/Graphics µ-Controller (TCG µ-Controller)and US Closed Caption decoder. In addition the followingfunctions can be added:

• Adaptive digital (4H/2H) PAL/NTSC combfilter

• Teletext decoder with 10 page text memory

• Multi-standard stereo decoder

• BTSC stereo decoder

• Digital sound processing circuit

• Digital video processing circuit

The UOCIII series consists of the following 3 basicconcepts:

• Stereo versions. These versions contain the TVprocessor with a stereo audio selector, the TCGµ-Controller, the multi-standard stereo or BTSCdecoder, the digital sound processing circuit and thedigital video processing circuit. Options are the adaptivedigital PAL/NTSC comb filter and a teletext decoder with10 page text memory.

• AV stereo versions. These versions contain the TVprocessor with stereo audio selector and the TCGµ-Controller. Options are the digital sound processingcircuit, the digital video processing circuit, the adaptivedigital PAL/NTSC comb filter and a teletext decoder witha 10 page text memory.

• Mono sound versions. These versions contain the TVprocessor with a selector for mono audio signals and theTCG µ-Controller. Options are the adaptive digitalPAL/NTSC combfilter and a teletext decoder with 10page text memory.

The most important features of the complete IC series aregiven in the following feature lists. The exact featurecontent of the various ICs is given in Table 1 on page 7.

The ICs are mounted in a QFP-128 envelope(1) and can beused in economy television receivers with 90° and 110°picture tubes. They have supply voltages of 5V, 3.3V. Alsoan 1.8V supply is needed, but this can be simply derivedby adding an emitter follower at a reference voltage fromthe device.

UOCIII is supported by a comprehensive Global TVSoftware Development kit to enable easy programmingand fast time-to-market (see also Chapter “LICENSEINFORMATION” on page 6.

(1) Both standard and “face down” versions of the QFP1280.8mm pitch package are available.

FEATURES

Analogue Video Processing (all versions)

• Multi-standard vision IF circuit with alignment-free PLLdemodulator

• Internal (switchable) time-constant for the IF-AGC circuit

• Switchable group delay correction and sound trap (withswitchable centre frequency) for the demodulated CVBSsignal

• DVB/VSB IF circuit for preprocessing of digital TVsignals.

• Video switch with 3 external CVBS inputs and a CVBSoutput. All CVBS inputs can be used as Y-input for Y/Csignals. However, only 2 Y/C sources can be selectedbecause the circuit has 2 chroma inputs. It is possible toadd an additional CVBS(Y)/C input (CVBS/YX and CX)when the YUV interface and the RGB/YPRPB input arenot needed.

• Automatic Y/C signal detector

• Adaptive digital (4H/2H) PAL/NTSC comb filter foroptimum separation of the luminance and thechrominance signal.

• Integrated luminance delay line with adjustable delaytime

• Picture improvement features with peaking (withswitchable centre frequency, depeaking, variablepositive/negative peak ratio, variable pre-/overshootratio and video dependent coring), dynamic skin tonecontrol, gamma control and blue- and black stretching.All features are available for CVBS, Y/C andRGB/YPBPR signals.

• Switchable DC transfer ratio for the luminance signal

• Only one reference (24.576 MHz) crystal required forthe TCG µ-Controller, digital sound processor, Teletext-and the colour decoder

• Multi-standard colour decoder with automatic searchsystem and various “forced mode” possibilities

• Internal base-band delay line

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CONFIDENTIAL

• Indication of the Signal-to-Noise ratio of the incomingCVBS signal

• Linear RGB/YPBPR input with fast insertion.

• YUV interface. When this feature is not required somepins can be used as additional RGB/YPBPR input. It isalso possible to use these pins for additional CVBS (orY/C) input (CVBS/YX and CX).

• Tint control for external RGB/YPBPR signals

• Scan Velocity Modulation output. The SVM circuit isactive for all the incoming CVBS, Y/C and RGB/YPBPRsignals. The SVM function can also be used during thedisplay of teletext pages.

• RGB control circuit with ‘Continuous CathodeCalibration’, white point and black level off-setadjustment so that the colour temperature of the darkand the light parts of the screen can be chosenindependently.

• Contrast reduction possibility during mixed-mode ofOSD and Text signals

• Adjustable ‘wide blanking’ of the RGB outputs

• Horizontal synchronization with two control loops andalignment-free horizontal oscillator

• Vertical count-down circuit

• Vertical driver optimized for DC-coupled vertical outputstages

• Horizontal and vertical geometry processing withhorizontal parallelogram and bow correction andhorizontal and vertical zoom

• Low-power start-up of the horizontal drive circuit

Analogue video processing (stereo versions)

• The low-pass filtered ‘mixed down’ I signal is availablevia a single ended or balanced output stage.

Analogue video processing (mono versions)

• The low-pass filtered ‘mixed down’ I signal is availablevia a single ended output stage

Digital Video Processing (some versions)

• Double Window mode applications. It is possible todisplay a video and a text window or 2 text windows inparallel.

• Linear and non-linear horizontal scaling of the videosignal to be displayed.

Sound Demodulation (all versions)

• Separate SIF (Sound IF) input for single reference QSS(Quasi Split Sound) demodulation.

• AM demodulator without extra reference circuit

• The mono intercarrier sound circuit has a selectiveFM-PLL demodulator which can be switched to thedifferent FM sound frequencies (4.5/5.5/6.0/6.5 MHz).The quality of this system is such that the externalband-pass filters can be omitted. In the stereo versionsof UOCIII the use of this demodulator is optional forspecial applications. Normally the FM demodulators ofthe stereo demodulator/decoder part are used (seebelow).

• The FM-PLL demodulator can be set to centrefrequencies of 4.72/5.74 MHz so that a second soundchannel can be demodulated. In such an application it isnecessary that an external bandpass filter is inserted.

• The vision IF and mono intercarrier sound circuit can beused for the demodulation of FM radio signals. With anexternal FM tuner also signals with an IF frequency of10.7 MHz can be demodulated.

• Switch to select between 2nd SIF from QSSdemodulation or external FM (SSIF)

Audio Interfaces and switching (stereo versions withAudio DSP)

• Audio switch circuit with 4 stereo inputs, a stereo outputfor SCART/CINCH, 1 stereo output for HEADPHONE.The headphone channel has an analogue volumecontrol circuit for the L and R channel. Finally 1 stereoSPEAKER output with digital controls.

• AVL (Automatic Volume Levelling) circuit for theheadphone channel.

• Digital input crossbar switch for all digital signal sourcesand destinations

• Digital output crossbar for exchange of channelprocessing functionality

• Digital audio input interface (stereo I2S input interface)

• Digital audio output interface (stereo I2S outputinterface)

Audio interfaces and switching (AV stereo versionswithout Audio DSP)

• Audio switch circuit with 4 stereo inputs, a stereo outputfor SCART/CINCH and a stereo SPEAKER output withanalogue volume control.

• Analogue mono AVL circuit at left audio channel

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CONFIDENTIAL

Audio interfaces and switching (mono versions)

• Audio switch circuit with 4 external audio (mono) inputsand a volume controlled output

• AVL circuit

Stereo Demodulator and Decoder (full stereoversions)

• Demodulator and Decoder Easy Programming (DDEP)

• Auto standard detection (ASD)

• Static Standard Selection (SSS)

• DQPSK demodulation for different standards,simultaneously with 1-channel FM demodulation

• NICAM decoding (B/G, I, D/K and L standard)

• Two-carrier multistandard FM demodulation (B/G, D/Kand M standard)

• Decoding for three analog multi-channel systems (A2,A2+ and A2*) and satellite sound

• Adaptive de-emphasis for satellite FM

• Optional AM demodulation for system L, simultaneouslywith NICAM

• Identification A2 systems (B/G, D/K and M standard)with different identification time constants

• FM pilot carrier present detector

• Monitor selection for FM/AM DC values and signals,with peak and quasi peak detection option

• BTSC MPX decoder

• SAP decoder

• dbx® noise reduction (4)

• Japan (EIAJ) decoder

• FM radio decoder

• Soft-mute for DEMDEC outputs DEC, MONO and SAP

• FM overmodulation adaptation option to avoid clippingand distortion

Audio Multi Channel Decoder (stereo versions withAudio DSP)

• Dolby® Pro Logic® (DPL) (1)

• Five channel processing for Main Left and Right,Subwoofer, Centre and Surround. To exploit this featurean external DAC is required.

Volume and tone control for loudspeakers (stereoversions with Audio DSP)

• Automatic Volume Level (AVL) control

• Smooth volume control

• Master volume control

• Soft-mute

• Loudness

• Bass, Treble

• Dynamic Bass Boost (DBB) (2)

• Dynamic Virtual Bass (DVB) (3)

• BBE® Sound processing (4)

• Graphic equaliser

• Processed or non processed subwoofer

• Programmable beeper

Reflection and delay for loudspeaker channels(stereo versions with Audio DSP)

• Dolby® Pro Logic® Delay (1)

• Pseudo hall/matrix function

Psycho acoustic spatial algorithms, downmix andsplit in loudspeaker channels (stereo versions withAudio DSP)

• Extended Pseudo Stereo (EPS) (5)

• Extended Spatial Stereo (ESS) (6)

• Virtual Dolby® Surround (VDS 422,423) (1)

• SRS 3D and SRS TruSurround® (4)

RDS/RBDS

• Demodulation of the European Radio Data system(RDS) or the USA Radio Broadcast Data System(RBDS) signal

• RDS and RBDS block detection

• Error detection and correction

• Fast block synchronisation

• Synchronisation control (flywheel)

• Mode control for RDS/RBDS processing

• Different RDS/RBDS block information output modes

(1) Dolby is a trademark of Dolby Laboratories

(2) Also referred to as “Dynamic UltraBass”(3) Also referred to as “Dynamic Bass Enhancement”(4) For the use of these products a licence is required. More

details are given in the chapter “LICENSE INFORMATION” onpage 6

(5) Also referred to as “I-Mono” or “Incredible Mono”(6) Also referred to as “I-Stereo” or “Incredible Stereo”

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CONFIDENTIAL

µ-Controller

• 80C51 µ-controller core standard instruction set andtiming

• 0.4883 µs machine cycle

• maximum of 256k x 8-bit flash programmable ROM

• maximum of 8k x 8-bit Auxiliary RAM

• 12-level Interrupt controller for individual enable/disablewith two level priority

• Two 16-bit Timer/Counter registers

• One 24-bit Timer (16-bit timer with 8-bit Pre-scaler)

• WatchDog timer

• Auxiliary RAM page pointer

• 16-bit Data pointer

• Stand-by, Idle and Power Down modes

• 24 general-purpose I/O pins

• 14 bits PWM for Voltage Synthesis Tuning

• 8-bit A/D converter with 4 multiplexed inputs

• 5 PWM (6-bits) outputs for analogue control functions

• Remote Control Pre-processor (RCP)

• Universal Asynchronous Receiver Transmitter (UART)

Data Capture

• Text memory up to 10 pages

• Inventory of transmitted Teletext pages stored in theTransmitted Page Table (TPT) and Subtitle Page Table(SPT)

• Data Capture for US Closed Caption

• Data Capture for 525/625 line WST, VPS (PDC systemA) and 625 line Wide Screen Signalling (WSS) bitdecoding

• Automatic selection between 525 WST/625 WST

• Automatic selection between 625 WST/VPS on line 16of VBI

• Real-time capture and decoding for WST Teletext inHardware, to enable optimized µ-processor throughput

• Automatic detection of FASTEXT transmission

• Real-time packet 26 engine in Hardware for processingaccented, G2 and G3 characters

• Signal quality detector for video and WST/VPS datatypes

• Comprehensive teletext language coverage

• Vertical Blanking Interval (VBI) data capture of WSTdata

Display

• Teletext and Enhanced OSD modes

• Features of level 1.5 WST and US Close Caption

• 50Hz/60Hz display timing modes

• Two page operation for 16:9 screens

• Serial and Parallel Display Attributes

• Single/Double/Quadruple Width and Height forcharacters

• Smoothing capability of both Double Size, Double Width& Double Height characters

• Scrolling of display region

• Variable flash rate controlled by software

• Soft colours using CLUT with 4096 colour palette

• Globally selectable scan lines per row (9/10/13/16/) andcharacter matrix [12x9, 12x13, 12x16, 16x18, (VxH)]

• Fringing (Shadow) selectable from N-S-E-W direction

• Fringe colour selectable

• Contrast reduction of defined area

• Cursor

• Special Graphics Characters with two planes, allowingfour colours per character

• 64 software redefinable On-Screen display characters

• 4 WST Character sets (G0/G2) in single device (e.g.Latin, Cyrillic, Greek, Arabic)

• G1 Mosaic graphics, Limited G3 Line drawingcharacters

• WST Character sets and Closed Caption Character setin single device

• SVM for Text

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CONFIDENTIAL

LICENSE INFORMATION

dbx

dbx is a registered trademark of Carillon Electronics Corp. A license is required for the use of this product. For furtherinformation, please contact THAT Corporation, 45 Summer street, Milford, Massachusetts 01757-1656, USA.

Tel: 1-508-478-9200, FAX: 1-508-478-0990

Dolby

“Dolby”, “Pro Logic” and the double-D symbol are trademarks of Dolby Laboratories, San Francisco, USA, products areavailable to licensees of Dolby Laboratories Licensing Corporation, 100 Potrero Avenue, San Francisco, CA, 94103,USA,

Tel: 1-415-558-0200, Fax: 1-415-863-1373

Supply of this Implementation of Dolby Technology does not convey a license nor imply a right under any patent, or anyother Industrial or Intellectual Property Right of Dolby Laboratories, to use this Implementation in any finished end-useror ready-to-use final product. It is hereby notified that a license for such use is required from Dolby Laboratories.

BBE

BBE is a registered trademark of BBE Sound, Inc., 5381 Production Drive, Huntington Beach, California 92649, USA.The use of BBE needs licensing from BBE Sound, Inc.

Tel: 1-714-897-6766, Fax: 1-714-895-6728

The SRS TruSurround technology rights incorporated in the TDA120xxH are owned by SRS Labs, a U.S. Corporationand licensed to Philips Semiconductors B.V. Purchaser of TDA120xxH must sign a license for use of the chip and displayof the SRS Labs trademarks. Any products incorporating the TDA120xxH must be sent to SRS Labs for review. SRSand TruSurround are protected under US and foreign patents issued and/or pending. TruSurround, SRS and (O) symbolare trademarks of SRS Labs, Inc. in the United States and selected foreign countries. Neither the purchase of the chipTDA120xxH, nor the corresponding sale of audio enhancement equipment conveys the right to sell commercializedrecordings made with any SRS technology. SRS Labs requires all set makers to comply with all rules and regulations asoutlined in the SRS Trademark Usage Manual separately provided.

Philips

“Dynamic Ultra BassTM”, “Dynamic Bass Enhancement”, “I-Mono” and “I-Stereo” are denominators for Philips patentedtechnologies. The use of the IC does not imply any copyrights nor the right to use the same denominators but insteadgeneric ones such as listed below.

Generic name/ Philips name

• Dynamic Virtual Bass (DVB)/Dynamic UltraBass

• Dynamic Bass Boost (DBB)/Dynamic Bass Enhancement

• Extended Pseudo Stereo (EPS)/I-Mono

• Extended Spatial Stereo (ESSI)/I-Stereo

GTV

Delivery and use of the GTV Software Development Kit requires a separate License sold by Philips Semiconductors B.V.Please contact your nearest Philips Semiconductors sales office for further details.

2003 Nov 11

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Versatile signal processor for low

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OVERVIEW OF THE VARIOUS VERSIONS

Table 1 Overview of types

TYPE NUMBER(1)

SOUND SYSTEMNUMBER OFTELETEXT

PAGES

CO

MB

FILT

ER

CO

LOU

R D

EC

OD

ER

ST

ER

EO

FM

RA

DIO

MO

NO

FM

RA

DIO

RD

S/R

BD

S

dbx®

Dolby®

ProLogic®

VirtualD

olby®(V

DS

)

SR

S®

3D S

tereo

SR

S®

TruS

urround

BB

ET

M

DW

/ PAN

OR

AM

A

RO

M S

IZE

(k)

AU

X R

AM

SIZ

E (k)

DIS

PLAY

RA

M (k)

DR

CS

RA

M (k)STEREO

DECO-DER

AUDIODSP

MONO 0 10

TDA11000H/H1 √ √ NTSC √ 128 4 1.25 2.25

TDA11001H/H1 √ √ √ NTSC √ 128 4 1.25 2.25

TDA11010H/H1 √ √ MULTI √ 128 4 1.25 2.25

TDA11011H/H1 √ √ √ MULTI √ 128 4 1.25 2.25

TDA11020H/H1 √ √ MULTI √ 128 4 10 2.25

TDA11021H/H1 √ √ √ MULTI √ 128 4 10 2.25

TDA12000H/H1(2) BTSC(3) √ √ NTSC √ √ 128/256 8 1.25 2.25

TDA12001H/H1(2) BTSC(3) √ √ √ NTSC √ √ 128/256 8 1.25 2.25

TDA12006H/H1 BTSC(3) √ √ NTSC √ √ √ √ √ 128/256 8 1.25 2.25

TDA12007H/H1 BTSC(3) √ √ √ NTSC √ √ √ √ √ 128/256 8 1.25 2.25

TDA12008H/H1 BTSC(3) √ √ NTSC √ √ √ √ √ √ √ √ √ 128/256 8 1.25 2.25

TDA12009H/H1 BTSC(3) √ √ √ NTSC √ √ √ √ √ √ √ √ √ 128/256 8 1.25 2.25

TDA12010H/H1(2) MULTI √ √ MULTI √ √ 128/256 8 1.25 2.25

TDA12011H/H1(2) MULTI √ √ √ MULTI √ √ 128/256 8 1.25 2.25

TDA12016H/H1 MULTI √ √ MULTI √ √ √ √ √ 128/256 8 1.25 2.25

TDA12017H/H1 MULTI √ √ √ MULTI √ √ √ √ √ 128/256 8 1.25 2.25

TDA12018H/H1 MULTI √ √ MULTI √ √ √ √ √ √ √ √ √ 128/256 8 1.25 2.25

TDA12019H/H1 MULTI √ √ √ MULTI √ √ √ √ √ √ √ √ √ 128/256 8 1.25 2.25

TDA12020H/H1(2) MULTI √ √ MULTI √ √ 128/256 8 10 2.25

TDA12021H/H1(2) MULTI √ √ √ MULTI √ √ 128/256 8 10 2.25

TDA12026H/H1 MULTI √ √ MULTI √ √ √ √ √ 128/256 8 10 2.25

TDA12027H/H1 MULTI √ √ √ MULTI √ √ √ √ √ 128/256 8 10 2.25

TDA12028H/H1 MULTI √ √ MULTI √ √ √ √ √ √ √ √ √ 128/256 8 10 2.25

TDA12029H/H1 MULTI √ √ √ MULTI √ √ √ √ √ √ √ √ √ 128/256 8 10 2.25

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Note

1. The “standard” version is indicated with “H” and the “facedown” version with “H1”

2. For these versions the feature content can be found from the type number. More details are given in the next Section.

3. When the BTSC demodulation is active the EIAJ demodulation is also activated.

TDA12060H/H1 √ MULTI √ 128/256 8 1.25 2.25

TDA12061H/H1 √ √ MULTI √ 128/256 8 1.25 2.25

TDA12062H/H1(2) √ MULTI √ 128/256 8 1.25 2.25

TDA12063H/H1(2) √ √ MULTI √ 128/256 8 1.25 2.25

TDA12066H/H1 √ √ MULTI √ √ √ √ √ 128/256 8 1.25 2.25

TDA12067H/H1 √ √ √ MULTI √ √ √ √ √ 128/256 8 1.25 2.25

TDA12068H/H1 √ √ MULTI √ √ √ √ √ √ √ √ 128/256 8 1.25 2.25

TDA12069H/H1 √ √ √ MULTI √ √ √ √ √ √ √ √ 128/256 8 1.25 2.25

TDA12070H/H1 √ MULTI √ 128/256 8 10 2.25

TDA12071H/H1 √ √ MULTI √ 128/256 8 10 2.25

TDA12072H/H1(2) √ MULTI √ 128/256 8 10 2.25

TDA12073H/H1(2) √ √ MULTI √ 128/256 8 10 2.25

TDA12076H/H1 √ √ MULTI √ √ √ √ √ 128/256 8 10 2.25

TDA12077H/H1 √ √ √ MULTI √ √ √ √ √ 128/256 8 10 2.25

TDA12078H/H1 √ √ MULTI √ √ √ √ √ √ √ √ 128/256 8 10 2.25

TDA12079H/H1 √ √ √ MULTI √ √ √ √ √ √ √ √ 128/256 8 10 2.25

TYPE NUMBER(1)

SOUND SYSTEMNUMBER OFTELETEXT

PAGES

CO

MB

FILT

ER

CO

LOU

R D

EC

OD

ER

ST

ER

EO

FM

RA

DIO

MO

NO

FM

RA

DIO

RD

S/R

BD

S

dbx®

Dolby®

ProLogic®

VirtualD

olby®(V

DS

)

SR

S®

3D S

tereo

SR

S®

TruS

urround

BB

ET

M

DW

/ PAN

OR

AM

A

RO

M S

IZE

(k)

AU

X R

AM

SIZ

E (k)

DIS

PLAY

RA

M (k)

DR

CS

RA

M (k)STEREO

DECO-DER

AUDIODSP

MONO 0 10

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Type Number Definition and Feature Indication

The complete type number of these versions is given below.

TDA12000H1/N1VXY0AA

The explanation of the various parts of the type number is given below:

• The first 8 characters indicate the type number, the last 2 characters vary depending on the version.

• The next 1 or 2 characters indicate the envelope. The normal QFP128 version is indicated with “H” and the “face-downversion” with “H1”.

• The first 3 characters after the slash (/) indicate the IC version.

• The characters “X” and “Y” give an indication of the Feature Content. More information is given in the Tables 2 and 3.

• The last 3 characters give an indication of the ROM code.

Table 2 Feature Indication, first character (X) Table 3 Feature Indication, second character (Y)

FIR

ST

IND

ICAT

ION

(X

)

RO

Msi

ze /

0 =

128K

dbx

®

Dol

by®

Pro

Logi

c®

Virt

ualD

olby

®(V

DS

)

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

A 1 0 1 0

B 1 0 1 1

C 1 1 0 0

D 1 1 0 1

E 1 1 1 0

F 1 1 1 1

SE

CO

ND

IND

ICAT

ION

(Y

)

SR

S®

3D

Ste

reo

SR

S®

Tru

Sur

roun

d

BB

ET

M

DW

/ PA

NO

RA

MA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

A 1 0 1 0

B 1 0 1 1

C 1 1 0 0

D 1 1 0 1

E 1 1 1 0

F 1 1 1 1

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QUICK REFERENCE DATA

Note

1. The supply voltage for the analogue audio part of the IC can be 5V or 8V. For a supply voltage of 5V the maximumsignal amplitudes at in and outputs are 1Vrms. For a supply voltage of 8V the maximum output signal amplitude is2 Vrms.

2. The YUV/YPBPR input signal amplitudes are based on a colour bar signal with 75/100% saturation.

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

Supply

VP analogue supply voltage TV processor 4.7 5.0 5.3 V

IP supply current (5.0 V) − 190 − mA

VDDA digital supply TV processor / analogue supply periphery 3.0 3.3 3.6 V

IDDA supply current (3.3 V) − 36 − mA

VDDC/P digital supply to core/periphery 1.65 1.8 1.95 V

IDDC/P supply current (1.8 V) − 440 − mA

VPAudio(1) audio supply voltage 4.7 8.0 8.4 V

IPAudio(1) supply current (5.0/8.0 V) − 0.5 − mA

Ptot total power dissipation − 1.87 − W

Input voltages

ViVIFrms) video IF amplifier sensitivity (RMS value) − 75 150 µV

ViSIF(rms) QSS sound IF amplifier sensitivity (RMS value) − 45 tbf dBµV

ViSSIF(rms) sound IF amplifier sensitivity (RMS value) − 1.0 − mV

ViAUDIO(rms) external audio input (RMS value) − 1.0 1.3 V

ViCVBS(p-p) external CVBS/Y input (peak-to-peak value) − 1.0 1.4 V

ViCHROMA(p-p) external chroma input voltage (burst amplitude)(peak-to-peak value)

− 0.3 1.0 V

ViRGB(p-p) RGB inputs (peak-to-peak value) − 0.7 0.8 V

ViY(p-p) luminance input signal (peak-to-peak value) − 1.4 / 1.0 − V

ViU(p-p) /ViPB(p-p)

U / PB input signal (peak-to-peak value); note 2 − −1.33 /+0.7

− V

ViV(p-p) /ViPR(p-p)

V / PR input signal (peak-to-peak value); note 2 − −1.05 /+0.7

− V

Output signals

Vo(IFVO)(p-p) demodulated CVBS output (peak-to-peak value) − 2.0 − V

Vo(QSSO)(rms) sound IF intercarrier output (RMS value) − 100 − mV

Vo(AMOUT)(rms) demodulated AM sound output (RMS value) − 250 − mV

Vo(AUDIO)(rms)(1) non-controlled audio output signals (RMS value) 1.0 − − V

Vo(CVBSO)(p-p) selected CVBS output (peak-to-peak value) − 2.0 − V

Io(AGCOUT) tuner AGC output current range 0 − 1 mA

VoRGB(p-p) RGB output signal amplitudes (peak-to-peak value) − 1.2 − V

IoHOUT horizontal output current 10 − − mA

IoVERT vertical output current (peak-to-peak value) − 1 − mA

IoEWD EW drive output current − − 1.2 mA

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BLOCK DIAGRAMS

V-D

RIV

E EW

DEH

TO

QS

S S

OU

ND

IFA

GC

QS

S M

IXE

RA

M D

EM

OD

ULA

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R

VIS

ION

IF/A

GC

/AF

CP

LL D

EM

OD

.

VID

EO

AM

P.

SO

UN

D T

RA

PG

RO

UP

DE

LAY

VID

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SW

ITC

H

VID

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IDE

NT

.

VID

EO

FIL

TE

RS

2H/4

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CO

MB

FIL

TE

R

DE

CO

DE

R

PA

L/S

EC

AM

/NT

SC

BA

SE

-BA

ND

DE

LAY

LIN

E

H/V

SY

NC

SE

P.

H-O

SC

. + P

LL2n

d LO

OP

H-S

HIF

TH

-DR

IVE

VE

RT

ICA

L

GE

OM

ET

RY

& E

AS

T-W

ES

T

SIF

IN/D

VB

IN

AG

CO

UT

VIF

IN

CV

BS

3/Y

3

C2/

C3

CV

BS

4/Y

4

C4

CV

BS

O/

SS

IF

ALL

-ST

AN

DA

RD

ST

ER

EO

DE

CO

DE

RA

M

AU

DIO

SE

LEC

T

SC

AR

T/C

INC

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/OU

TI2

SLS

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LR

AU

DIO

CO

NT

RO

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TR

EB

BLE

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SS

FE

AT

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HO

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PE

AK

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SC

AN

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ITY

RG

B/Y

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B IN

SE

RT

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V IN

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RF

AC

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CO

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BR

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SAT

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MM

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TR

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BLA

CK

ST

RE

TC

H

µ-P

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CE

SS

OR

AN

D T

ELE

TE

XT

DE

CO

DE

R

BL

RG

BC

R

RO

GO

BO

BC

LIN

BLK

IN

RG

B C

ON

TR

OL

OS

D/T

EX

T IN

SE

RT

CC

C

WH

ITE

-P. A

DJ.

CO

NT

R/B

RIG

HT

N

RG

B M

ATR

IX

Fig

.1 B

lock

dia

gram

of t

he “

Ste

reo”

TV

pro

cess

or

SV

M

A/D

CO

NV

ER

TE

R

AD

C/D

AC

DA

Cs

I/Os

C Y

H/V

DV

BO

/FM

RO

SW

ITC

H

RE

FO

LR

HP

-OU

T

RE

F

Y D

ELA

Y A

DJ.

SC

AV

EM

ON

TE

XT

SK

IN T

ON

E

U/V

TIN

T

U/V

DE

LAY

SA

TU

RA

TIO

N

MO

DU

LAT

ION

BLU

E S

TR

ET

CH

CV

BS

2/Y

2

IFV

O/S

VO

/

YS

YN

C

YUV IN/OUT

YU

V

DV

BO

/IFV

O/

QS

SO

/AM

OU

T

SO

UN

D P

LL

DE

EM

PH

AS

IS

DIG

ITA

L S

IGN

AL

PR

OC

ES

SIN

G F

EA

TU

RE

S

BL R

/PRG

/Y

B/P

B

Vo

Uo

Yo

Yi

Ui

Vi

SW

O1

BL

G/Y

(CV

BS

x/Y

x)

B/P

B R/P

R

(Cx)

CV

BS

I

RD

S

PIP

FM

RO

DIG

ITA

L

2003 Nov 11 12



CONFIDENTIAL

V-D

RIV

E EW

DEH

TO

QS

S S

OU

ND

IFA

GC

QS

S M

IXE

RA

M D

EM

OD

ULA

TO

R

VIS

ION

IF/A

GC

/AF

CP

LL D

EM

OD

.

VID

EO

AM

P.

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PG

RO

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IDE

NT

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FIL

TE

RS

2H/4

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B F

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ER

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CO

DE

R

PA

L/S

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AM

/NT

SC

BA

SE

-BA

ND

DE

LAY

LIN

E

H/V

SY

NC

SE

P.

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SC

. + P

LL2n

d LO

OP

H-S

HIF

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RT

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L

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OM

ET

RY

& E

AS

T-W

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T

SIF

IN/D

VB

IN

AG

CO

UT

VIF

IN

CV

BS

3/Y

3

C2/

C3

CV

BS

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4C

4

CV

BS

O/

SS

IF

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UT

PE

AK

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SC

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LOC

ITY

RG

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SE

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AC

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SAT

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-P. A

DJ.

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NT

R/B

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HT

N

RG

B M

ATR

IX

Fig

.2 B

lock

dia

gram

of t

he “

AV

-ste

reo”

TV

pro

cess

or w

ith a

udio

DS

P

SV

M

I/Os

C Y

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RE

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XT

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TIN

T

U/V

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LAY

SA

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ION

BLU

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TR

ET

CH

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BS

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IFV

O/S

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YS

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AM

QS

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/AM

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T

DV

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/IFV

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D P

LL

DE

EM

PH

AS

IS

DIG

ITA

L S

IGN

AL

PR

OC

ES

SIN

G F

EA

TU

RE

S

BL

G/Y

R/P

RB

/PB

SW

O1

BL

G/YB

/PB

Vo

Uo

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Yi

Vi

Ui

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BS

x/Y

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x)R

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BS

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RD

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T

SC

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EB

BLE

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SS

FE

AT

UR

ES

AD

C/D

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Cs

LR

HP

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T

FM

RO

DIG

ITA

L

2003 Nov 11 13



CONFIDENTIAL

V-D

RIV

E EW

DEH

TO

QS

S S

OU

ND

IFA

GC

QS

S M

IXE

RA

M D

EM

OD

ULA

TO

R

VIS

ION

IF/A

GC

/AF

CP

LL D

EM

OD

.

VID

EO

AM

P.

SO

UN

D T

RA

PG

RO

UP

DE

LAY

VID

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ITC

H

VID

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NT

.

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FIL

TE

RS

2H/4

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MB

FIL

TE

R

DE

CO

DE

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PA

L/S

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AM

/NT

SC

BA

SE

-BA

ND

DE

LAY

LIN

E

H/V

SY

NC

SE

P.

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SC

. + P

LL2n

d LO

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HIF

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RT

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RY

& E

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T

SIF

IN/D

VB

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AG

CO

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IN

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BS

3/Y

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C2/

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CV

BS

4/Y

4C

4

CV

BS

O/

SS

IF

HO

UT

PE

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ING

SC

AN

VE

LOC

ITY

RG

B/Y

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SE

RT

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V IN

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RF

AC

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I

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WH

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-P. A

DJ.

CO

NT

R/B

RIG

HT

N

RG

B M

ATR

IX

Fig

.3 B

lock

dia

gram

of t

he “

AV

-ste

reo”

TV

pro

cess

or w

ithou

t aud

io D

SP

SV

M

I/Os

C Y

H/V

DV

BO

/FM

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SW

ITC

H

RE

FO

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F

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SC

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XT

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ION

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TR

ET

CH

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/

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C

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AM

QS

SO

/AM

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T

DV

BO

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UN

D P

LL

DE

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PH

AS

IS

DIG

ITA

L S

IGN

AL

PR

OC

ES

SIN

G F

EA

TU

RE

S

BL

G/Y

R/P

RB

/PB

SW

O1

BL

G/YB

/PB

Vo

Uo

Yo

Yi

Vi

Ui

(CV

BS

x/Y

x)(C

x)R

/PR

PIP

CV

BS

I

RD

S

AU

DIO

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T

SC

AR

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INC

H IN

/OU

TLS

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T

LR

VO

LUM

E C

ON

TR

OL

FM

RO

DIG

ITA

L

2003 Nov 11 14



CONFIDENTIAL

AG

CO

UT

RO

GO

BO

BC

LIN

BLK

IN

CV

BS

3/Y

3

SIF

IN/D

VB

IN

AUDOUT/AMOUT

Fig

. 4 B

lock

dia

gram

of t

he “

Mon

o” T

V p

roce

ssor

C2/

C3

VIS

ION

IF/A

GC

/AF

C

PLL

DE

MO

D.

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SW

ITC

H

VID

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IDE

NT

.

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FIL

TE

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PA

L/S

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AM

/NT

SC

DE

CO

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PH

AS

ISA

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CO

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SE

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DE

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LIN

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CO

NT

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HT

N

OS

D/T

EX

T IN

SE

RT

CC

CW

HIT

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. AD

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RG

BB

L

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V

U/V

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F

RG

B/Y

UV

/YP

RP

B IN

SE

RT

RE

F

CO

R SA

TU

RA

TIO

NB

LAC

K S

TR

ET

CH

QS

S S

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ND

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GC

QS

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IXE

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M D

EM

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TO

R

SO

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2/Y

2

VIF

IN

CV

BS

O/P

IP

QSSO/AMOUT

BLU

E S

TR

ET

CH

AUDIO2AUDIO3

AUDEEM

(AVL)

(SSIF)

DV

B M

IXE

R

SV

M

IFV

O/S

VO

/

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V IN

TE

RFA

CE

VI

UI

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VO

UO

YO

PE

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ING

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VE

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ITY

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ION

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E

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NC

SE

P.

H-O

SC

. + P

LL

H-D

RIV

E

2nd

LOO

PH

-SH

IFT

VE

RT

ICA

L +

EW

V

GE

OM

ET

RY

EH

TO

(EW

D)

AN

D D

RIV

E

YS

YN

C

4H/2

H

CO

MB

FIL

TE

R

Y D

ELA

Y A

DJ.

Y

U/V

DE

LAY

µ-P

RO

CE

SS

OR

AN

D T

ELE

TE

XT

DE

CO

DE

R

DIG

ITA

L S

IGN

AL

PR

OC

ES

SIN

G F

EA

TU

RE

S

YUV IN/OUT

SW

ITC

H

SK

IN T

ON

E

SW

O1

BL

G/Y

B/P

BR

/PR

(CV

BS

/Yx)

(Cx)

SC

AV

EM

ON

TE

XT

DV

BO

/IFV

OF

MR

O

RD

S

(RE

FO

)

CV

BS

I

GA

MM

A C

ON

TR

OL

DIG

ITA

L

BL

G/Y

R/P

RB

/PB

I/Os

CV

BS

4/Y

4

C4

AUDIO4

AUDIO5

2003 Nov 11

15

Philips S

emiconductors

Prelim

inary specification


- andm

id-range TV

applicationsU

OC

III series

CO

NF

IDE

NT

IAL

PINNING OF THE VARIOUS VERSIONS

SYMBOL

“STANDARD”VERSION

“FACE DOWN”VERSION

DESCRIPTION

ST

ER

EO

+AV

ST

ER

EO

AV S

TE

RE

ON

O A

UD

IO D

SP

MO

NO

ST

ER

EO

+AV

ST

ER

EO

AV S

TE

RE

ON

O A

UD

IO D

SP

MO

NO

VSSP2 1 1 1 128 128 128 ground

VSSC4 2 2 2 127 127 127 ground

VDDC4 3 3 3 126 126 126 digital supply to SDACs (1.8V)

VDDA3(3.3V) 4 4 4 125 125 125 supply (3.3 V)

VREF_POS_LSL 5 − − 124 − − positive reference voltage SDAC (3.3 V)

VREF_NEG_LSL+HPL 6 − − 123 − − negative reference voltage SDAC (0 V)

VREF_POS_LSR+HPR 7 − − 122 − − positive reference voltage SDAC (3.3 V)

VREF_NEG_HPL+HPR 8 − − 121 − − negative reference voltage SDAC (0 V)

VREF_POS_HPR 9 − − 120 − − positive reference voltage SDAC (3.3 V)

XTALIN 10 10 10 119 119 119 crystal oscillator input

XTALOUT 11 11 11 118 118 118 crystal oscillator output

VSSA1 12 12 12 117 117 117 ground

VGUARD/SWIO 13 13 13 116 116 116 V-guard input / I/O switch (e.g. 4 mA current sinking capability fordirect drive of LEDs)

DECDIG 14 14 14 115 115 115 decoupling digital supply

VP1 15 15 15 114 114 114 1st supply voltage TV-processor (+5 V)

PH2LF 16 16 16 113 113 113 phase-2 filter

PH1LF 17 17 17 112 112 112 phase-1 filter

GND1 18 18 18 111 111 111 ground 1 for TV-processor

SECPLL 19 19 19 110 110 110 SECAM PLL decoupling

DECBG 20 20 20 109 109 109 bandgap decoupling

EWD/AVL (1) 21 21 21 108 108 108 East-West drive output or AVL capacitor

2003 Nov 11

16

Philips S

emiconductors

Prelim

inary specification


- andm

id-range TV

applicationsU

OC

III series

CO

NF

IDE

NT

IAL

VDRB 22 22 22 107 107 107 vertical drive B output

VDRA 23 23 23 106 106 106 vertical drive A output

VIFIN1 24 24 24 105 105 105 IF input 1

VIFIN2 25 25 25 104 104 104 IF input 2

VSC 26 26 26 103 103 103 vertical sawtooth capacitor

IREF 27 27 27 102 102 102 reference current input

GNDIF 28 28 28 101 101 101 ground connection for IF amplifier

SIFIN1/DVBIN1 (2) 29 29 29 100 100 100 SIF input 1 / DVB input 1

SIFIN2/DVBIN2 (2) 30 30 30 99 99 99 SIF input 2 / DVB input 2

AGCOUT 31 31 31 98 98 98 tuner AGC output

EHTO 32 32 32 97 97 97 EHT/overvoltage protection input

AVL/SWO/SSIF/REFO/REFIN (2)(3)

33 33 33 96 96 96 Automatic Volume Levelling / switch output / sound IF input /subcarrier reference output / external reference signal input for Isignal mixer for DVB operation

AUDIOIN5 − − 34 − − 95 audio 5 input

AUDIOIN5L 34 34 − 95 95 − audio-5 input (left signal)

AUDIOIN5R 35 35 − 94 94 − audio-5 input (right signal)

AUDOUTSL 36 36 − 93 93 − audio output for SCART/CINCH (left signal)

AUDOUTSR 37 37 − 92 92 − audio output for SCART/CINCH (right signal)

DECSDEM 38 38 38 91 91 91 decoupling sound demodulator

QSSO/AMOUT/AUDEEM (2) 39 39 39 90 90 90 QSS intercarrier output / AM output / deemphasis (front-end audioout)

GND2 40 40 40 89 89 89 ground 2 for TV processor

SYMBOL



DESCRIPTION

ST

ER

EO

+AV

ST

ER

EO

AV S

TE

RE

ON

O A

UD

IO D

SP

MO

NO

ST

ER

EO

+AV

ST

ER

EO

AV S

TE

RE

ON

O A

UD

IO D

SP

MO

NO

2003 Nov 11

17

Philips S

emiconductors

Prelim

inary specification


- andm

id-range TV

applicationsU

OC

III series

CO

NF

IDE

NT

IAL

PLLIF 41 41 41 88 88 88 IF-PLL loop filter

SIFAGC/DVBAGC (2) 42 42 42 87 87 87 AGC sound IF / internal-external AGC for DVB applications

DVBO/IFVO/FMRO (2) 43 43 43 86 86 86 Digital Video Broadcast output / IF video output / FM radio output

DVBO/FMRO (2) 44 44 − 85 85 − Digital Video Broadcast output / FM radio output

VCC8V 45 45 45 84 84 84 8 Volt supply for audio switches

AGC2SIF 46 − − 83 − − AGC capacitor second sound IF

VP2 47 47 47 82 82 82 2nd supply voltage TV processor (+5 V)

IFVO/SVO/CVBSI (2) 48 48 48 81 81 81 IF video output / selected CVBS output / CVBS input


AUDIOIN4L 49 49 − 80 80 − audio-4 input (left signal)

AUDIOIN4R 50 50 − 79 79 − audio-4 input (right signal)

CVBS4/Y4 51 51 51 78 78 78 CVBS4/Y4 input

C4 52 52 52 77 77 77 chroma-4 input


AUDIOIN2L/SSIF (3) 53 53 − 76 76 − audio 2 input (left signal) / sound IF input

AUDIOIN2R 54 54 − 75 75 − audio 2 input (right signal)



AUDIOIN3L 56 56 − 73 73 − audio 3 input (left signal)

AUDIOIN3R 57 57 − 72 72 − audio 3 input (right signal)


C2/C3 59 59 59 70 70 70 chroma-2/3 input

SYMBOL



DESCRIPTION

ST

ER

EO

+AV

ST

ER

EO

AV S

TE

RE

ON

O A

UD

IO D

SP

MO

NO

ST

ER

EO

+AV

ST

ER

EO

AV S

TE

RE

ON

O A

UD

IO D

SP

MO

NO

2003 Nov 11

18

Philips S

emiconductors

Prelim

inary specification


- andm

id-range TV

applicationsU

OC

III series

CO

NF

IDE

NT

IAL

AUDOUTLSL 60 62 − 69 67 − audio output for audio power amplifier (left signal)

AUDOUTLSR 61 63 − 68 66 − audio output for audio power amplifier (right signal)

AUDOUT/AMOUT/FMOUT − − 62 − − 67 audio output / AM output / FM output, volume controlled

AUDOUTHPL 62 − − 67 − − audio output for headphone channel (left signal)

AUDOUTHPR 63 − − 66 − − audio output for headphone channel (right signal)

CVBSO/PIP 64 64 64 65 65 65 CVBS / PIP output

SVM 65 65 65 64 64 64 scan velocity modulation output

FBISO/CSY 66 66 66 63 63 63 flyback input/sandcastle output or composite H/V timing output

HOUT 67 67 67 62 62 62 horizontal output

VSScomb 68 68 68 61 61 61 ground connection for comb filter

VDDcomb 69 69 69 60 60 60 supply voltage for comb filter (5 V)

VIN (R/PRIN2/CX) 70 70 70 59 59 59 V-input for YUV interface (2nd R input / PR input or CX input)

UIN (B/PBIN2) 71 71 71 58 58 58 U-input for YUV interface (2nd B input / PB input)

YIN (G/YIN2/CVBS-YX) 72 72 72 57 57 57 Y-input for YUV interface (2nd G input / Y input or CVBS/YX input))

YSYNC 73 73 73 56 56 56 Y-input for sync separator

YOUT 74 74 74 55 55 55 Y-output (for YUV interface)

UOUT (INSSW2) 75 75 75 54 54 54 U-output for YUV interface (2nd RGB / YPBPR insertion input)

VOUT (SWO1) 76 76 76 53 53 53 V-output for YUV interface (general purpose switch output)

INSSW3 77 77 77 52 52 52 3rd RGB / YPBPR insertion input

R/PRIN3 78 78 78 51 51 51 3rd R input / PR input

G/YIN3 79 79 79 50 50 50 3rd G input / Y input

B/PBIN3 80 80 80 49 49 49 3rd B input / PB input

SYMBOL



DESCRIPTION

ST

ER

EO

+AV

ST

ER

EO

AV S

TE

RE

ON

O A

UD

IO D

SP

MO

NO

ST

ER

EO

+AV

ST

ER

EO

AV S

TE

RE

ON

O A

UD

IO D

SP

MO

NO

2003 Nov 11

19

Philips S

emiconductors

Prelim

inary specification


- andm

id-range TV

applicationsU

OC

III series

CO

NF

IDE

NT

IAL

GND3 81 81 81 48 48 48 ground 3 for TV-processor

VP3 82 82 82 47 47 47 3rd supply for TV processor

BCLIN 83 83 83 46 46 46 beam current limiter input

BLKIN 84 84 84 45 45 45 black current input

RO 85 85 85 44 44 44 Red output

GO 86 86 86 43 43 43 Green output

BO 87 87 87 42 42 42 Blue output

VDDA1 88 88 88 41 41 41 analog supply for TCG µ-Controller and digital supply forTV-processor (+3.3 V)

VREFAD_NEG 89 89 89 40 40 40 negative reference voltage (0 V)

VREFAD_POS 90 90 90 39 39 39 positive reference voltage (3.3 V)

VREFAD 91 − − 38 − − reference voltage for audio ADCs (3.3/2 V)

GNDA 92 92 92 37 37 37 ground

VDDA(1.8V) 93 93 93 36 36 36 analogue supply for audio ADCs (1.8 V)

VDDA2(3.3) 94 94 94 35 35 35 supply voltage SDAC (3.3 V)

VSSadc 95 95 95 34 34 34 ground for video ADC and PLL

VDDadc(1.8) 96 96 96 33 33 33 supply voltage video ADC and PLL

INT0/P0.5 97 97 97 32 32 32 external interrupt 0 or port 0.5 (4 mA current sinking capability fordirect drive of LEDs)

P1.0/INT1 98 98 98 31 31 31 port 1.0 or external interrupt 1

P1.1/T0 99 99 99 30 30 30 port 1.1 or Counter/Timer 0 input

VDDC2 100 100 100 29 29 29 digital supply to core (1.8 V)

VSSC2 101 101 101 28 28 28 ground

SYMBOL



DESCRIPTION

ST

ER

EO

+AV

ST

ER

EO

AV S

TE

RE

ON

O A

UD

IO D

SP

MO

NO

ST

ER

EO

+AV

ST

ER

EO

AV S

TE

RE

ON

O A

UD

IO D

SP

MO

NO

2003 Nov 11

20

Philips S

emiconductors

Prelim

inary specification


- andm

id-range TV

applicationsU

OC

III series

CO

NF

IDE

NT

IAL

P0.4/I2SWS 102 − − 27 − − port 0.4 or I2S word select

P0.4 − 102 102 − 27 27 port 0.4

P0.3/I2SCLK 103 − − 26 − − port 0.3 or I2S clock

P0.3 − 103 103 − 26 26 port 0.3

P0.2/I2SDO2 104 − − 25 − − port 0.2 or I2S digital output 2

P0.2 − 104 104 − 25 25 port 0.2

P0.1/I2SDO1 105 − − 24 − − port 0.1 or I2S digital output 1

P0.1 − 105 105 − 24 24 port 0.1

P0.0/I2SDI1/O 106 − − 23 − − port 0.0 or I2S digital input 1 or I2S digital output

P0.0 − 106 106 − 23 23 port 0.0

P1.3/T1 107 107 107 22 22 22 port 1.3 or Counter/Timer 1 input

P1.6/SCL 108 108 108 21 21 21 port 1.6 or I2C-bus clock line

P1.7/SDA 109 109 109 20 20 20 port 1.7 or I2C-bus data line

VDDP(3.3V) 110 110 110 19 19 19 supply to periphery and on-chip voltage regulator (3.3 V)

P2.0/TPWM 111 111 111 18 18 18 port 2.0 or Tuning PWM output

P2.1/PWM0 112 112 112 17 17 17 port 2.1 or PWM0 output



P3.0/ADC0 115 115 115 14 14 14 port 3.0 or ADC0 input


VDDC1 117 117 117 12 12 12 digital supply to core (+1.8 V)

DECV1V8 118 118 118 11 11 11 decoupling 1.8 V supply

SYMBOL



DESCRIPTION

ST

ER

EO

+AV

ST

ER

EO

AV S

TE

RE

ON

O A

UD

IO D

SP

MO

NO

ST

ER

EO

+AV

ST

ER

EO

AV S

TE

RE

ON

O A

UD

IO D

SP

MO

NO

2003 Nov 11

21

Philips S

emiconductors

Prelim

inary specification


- andm

id-range TV

applicationsU

OC

III series

CO

NF

IDE

NT

IAL

Note

1. The function of this pin can be chosen by means of the AVLE bit.

2. The functional content of these pins is dependent on the mode of operation and on some I2C-bus control bits. More details are given in table 4.

3. With the ESSIF bit the SSIF input can be selected either on pin 33 or pin 53. For the “face down” versions these pin numbers are 96 and 76respectively.



VSSC/P 121 121 121 8 8 8 digital ground for µ-Controller core and periphery



VDDC3 124 124 124 5 5 5 digital supply to core (1.8V)

VSSC3 125 125 125 4 4 4 ground

P1.2/INT2 126 126 126 3 3 3 port 1.2 or external interrupt 2

P1.4/RX 127 127 127 2 2 2 port 1.4 or UART bus

P1.5/TX 128 128 128 1 1 1 port 1.5 or UART bus

SYMBOL



DESCRIPTION

ST

ER

EO

+AV

ST

ER

EO

AV S

TE

RE

ON

O A

UD

IO D

SP

MO

NO

ST

ER

EO

+AV

ST

ER

EO

AV S

TE

RE

ON

O A

UD

IO D

SP

MO

NO

2003 Nov 11

22

Philips S

emiconductors

Prelim

inary specification


- andm

id-range TV

applicationsU

OC

III series

CO

NF

IDE

NT

IAL

Table 4 Pin functions for various modes of operation

Note

1. The function of this pin is controlled by the bits CMB2-CMB0 in subaddress 4AH.

2. The functions of the pins 43/44 (standard pinning) or 85/86 (face-down pinning) are controlled by the IFO2-IFO0 bits in subaddress 31H.

3. The function of this pin is determined by the SVO1/SVO0 bits in subaddress 39H.

4. This functionality is only valid for the mono versions. In the “stereo” and “AV-stereo” versions this pin has the function of audio output for theheadphone channel (left signal).

IC MODE

DVB MODE

ANALOGUE TV MODE

FM RADIO MODEFM-PLL MODE

(QSS = 0)QSS MODE (QSS = 1)

FUNCTIONFM

DEMODULATIONQSS/AM DEMODULATION

QSS-FMDEMODULATION

IFA/IFB/IFC bits 101/111 000/001/010/011/100/110 101/111

FMR bit 0 0 0 1

FMI bit − − 0 1 −AVLE bit 1 0 1 0 1 0 1 0 1 0

CMB2/CMB1/CMB0 bits 010/011 100 000/001/010/011/101/110

AM bit − − 0 1 0 1 − −Standard Face-down

pin 21 pin 108 AVL EWD AVL EWD AVL EWD AVL EWD AVL EWD

pin 29 pin 100 DVBIN1 − SIFIN1 SIFIN1

pin 30 pin 99 DVBIN2 − SIFIN2 SIFIN2

pin 33 (1) pin 96 (1) SWO REFIN SWO/SSIF/REFO

AVL/SWO/SSIF/REFO

SWO/SSIF/REFO AVL/SWO/SSIF/REFO

SWO/SSIF/REFO

AVL/SWO/SSIF/REFO

SWO/SSIF/REFO

AVL/SWO/SSIF/REFO

pin 39 pin 90 − AUDEEM QSSO AMOUT QSSO AMOUT AUDEEM AUDEEM

pin 42 pin 87 DVBAGC − SIFAGC SIFAGC

pin 43 (2) pin 86 (2) DVBO IFVO IFVO FMRO

pin 44 (2) pin 85 (2) DVBO − − FMRO

pin 48 (3) pin 81 (3) SVO/CVBSI IFVO/SVO/CVBSI IFVO/SVO/CVBSI IFVO/SVO/CVBSI

pin 62 (4) pin 67 (4) AUDOUT AUDOUT AUDOUT AMOUT AUDOUT AMOUT AUDOUT AUDOUT

2003 Nov 11 23



CONFIDENTIAL

Fig.5 Pin configuration “stereo” and “AV-stereo” versions with Audio DSP

69

70

8180

7978

77

76

75

74

73

72

71

88

8786

85

8483

82

6566

68

67

89

96

9594

93

9291

90

13

14

1516

17

18

1920

2122

23

24

25

26

2728

9

10

1112

29

3132

30

5

6

78

1

2

34

41 42 43 44 45 46 47 48 49 51 52 53 54 565533 34 35 36 37 38 39 40 57 58 59 60 61 62 646350

QFP-128 0.8mm pitch “standard version”

GNDA11

2

111

110

109

108

107

106

105

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

104

103

102

101

100 99 98 97

P0.

1/I2

SD

O1

P0.

2/I2

SD

O2

P0.

0/I2

SD

I1

VS

SC

2

P0.

3/I2

SC

LK

P0.

4/I2

SW

S

VD

DC

2

VS

SC

3

VDDA3(3.3V) VDDA(1.8V)

VD

DC

3

P3.

2/A

DC

2

P3.

3/A

DC

3V

SS

C1/

P

INT

0/P

0.5

P3.

0/A

DC

0

P3.

1/A

DC

1

P2.

3/P

WM

2

P1.

6/S

CL

P2.

2/P

WM

1

P2.

1/P

WM

0

P2.

0/P

MW

P1.

7/S

DA

P1.

3/T

1

P2.

4/P

WM

3

VD

DP

(3.3

V)

VD

DC

1(1.

8)

VREF_POS_LSL

VDDA2(3.3V)

P1.

2/IN

T2

VDRA

VIFIN1

VIFIN2VSC

SECPLL

DECDIG

PH1LF

DECBG

AVL/EWDVDRB

IREF

AGCOUT

DVBIN1/SIFIN1DVBIN2/SIFIN2

P1

.4/R

X

VP1

XTALIN

XTALOUTVSSA1

GNDIF

VREF_POS_LSR+HPL

VREF_NEG_HPL+HPR

VREF_POS_HPR

VREF_NEG_LSL+LSR

FBISO/CSY

CV

BS

O/P

IP

AU

DIO

IN5L

SVM

GN

D2

DV

BO

//IF

VO

/FM

RO

DV

BO

/FM

RO

AG

C2S

IF

AU

DIO

IN4L

SIF

AG

C/D

VB

AG

C

PLL

IF

AU

DIO

IN5R

AU

DO

UT

LSL

AU

DO

UT

LSR

AU

DIO

IN4R

VC

C8V

CV

BS

3/Y

3

AU

DIO

IN2L

AU

DIO

IN2R

/SS

IF

CV

BS

4/Y

4

AU

DIO

IN3L

AU

DIO

IN3RC4

AU

DO

UT

HP

L

AU

DO

UT

HP

R

CV

BS

2/Y

2

VP

2

SV

O/IF

OU

T/C

VB

SI

C2/

C3

DE

CS

DE

M

AM

OU

T/Q

SS

O/A

UD

EE

M

EHTO

VDDcomb

VDDA1(3.3V.)BOGO

RO

VREFAD_NEG

HOUT

VREFAD_POS

VSScomb

INSSW3

R/PR-3

BLKIN

BCLIN

B/PB-3G/Y-3

YIN(G/Y-2/CVBS/Y-X)

VOUT(SWO1)

UOUT(INSW-2)YOUT

UINVIN(R/PR-2/C-X)

(B/PB-2)

YSYNC

VP3GND3

VREFAD

P1.

O/IN

T1

P1.

1/T

0

VDDadc(1.8)VSSadc

RE

FIN

/RE

FO

UT

VGUARD/SWIO

P2.

5/P

WM

4

DE

CV

1V8

GND1

AU

DO

UT

SL

AU

DO

UT

SR

P1.

5/T

X

VDDC4

VSSC4

VSSP2

AV

L/S

WO

/SS

IF/

PH2LF

2003 Nov 11 24



CONFIDENTIAL

Fig.6 Pin configuration of “AV stereo” versions without Audio DSP

69

70

8180

7978

77

76

75

74

73

72

71

88

8786

85

8483

82

6566

68

67

89

96

9594

93

9291

90

13

14

1516

17

18

1920

2122

23

24

25

26

2728

9

10

1112

29

3132

30

5

6

78

1

2

34


112

111

110

109

108

107

106

105

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

104

103

102

101

100 99 98 97

P0.

1

P0.

2

P0.

0

P0.

3P

0.4

VDDA3(3.3V)

P3.

2/A

DC

2

P3.

3/A

DC

3V

SS

C1/

P

INT

0/P

0.5

P3.

0/A

DC

0

P3.

1/A

DC

1

P2.

3/P

WM

2

P1.

6/S

CL

P2.

2/P

WM

1

P2.

1/P

WM

0

P2.

0/P

MW

P1.

7/S

DA

P1.

3/T

1

P2.

4/P

WM

3

VD

DP

(3.3

V)

VD

DC

1(1.

8)

-

P1.

2/IN

T2

VDRA

VIFIN1

VIFIN2VSC

SECPLL

DECDIG

PH1LF

DECBG

AVL/EWDVDRB

IREF

AGCOUT


P1

.4/R

X

VP1

XTALIN

XTALOUTVSSA1

GNDIF

-

-

-

-

FBISO/CSYSVMEHTO

VDDcomb

VDDA1(3.3V.)BOGO

RO

HOUT

VSScomb

INSSW3

R/PR-3

BLKIN

BCLIN

B/PB-3G/Y-3

YIN(G/Y-2/CVBS/Y-X)

VOUT(SWO1)

UOUT(INSW-2)YOUT

UINVIN(R/PR-2/C-X)

(B/PB-2)

YSYNC

VP3GND3

-

P1.

O/IN

T1

P1.

1/T

0

VDDadc(1.8)VSSadc

VGUARD/SWIO

P2.

5/P

WM

4

DE

CV

1V8

GND1

P1.

5/T

X

VDDC4

PH2LF

VSSP2VSSC4

41 42 43 44 45 46 47 48 49 51 52 53 54 565533 34 35 36 37 38 39 40 57 58 59 60 61 62 646350

CV

BS

O/P

IP

AU

DIO

IN5L

GN

D2

DV

BO

//IF

VO

/FM

RO - -

AU

DIO

IN4L

SIF

AG

C/D

VB

AG

C

PLL

IF

AU

DIO

IN5R

AU

DIO

IN4R

VC

C8V

CV

BS

3/Y

3

AU

DIO

IN2L

/SS

IF

AU

DIO

IN2R

CV

BS

4/Y

4

AU

DIO

IN3L

AU

DIO

IN3RC4

AU

DO

UT

LSL

AU

DO

UT

LSR

CV

BS

2/Y

2

VP

2

SV

O/IF

OU

T/C

VB

SI

C2/

C3

DE

CS

DE

M

AM

OU

T/Q

SS

O/A

UD

EE

M

RE

FIN

/RE

FO

UT

AU

DO

UT

SL

AU

DO

UT

SR

AV

L/S

WO

/SS

IF/

VS

SC

3

VD

DC

3

VS

SC

2V

DD

C2

GNDAVDDA(1.8V)

VDDA2(3.3V)

VREFAD_NEG

VREFAD_POS

- -

2003 Nov 11 25



CONFIDENTIAL

Fig.7 Pin configuration “mono” versions

69

70

8180

7978

77

76

75

74

73

72

71

88

8786

85

8483

82

6566

68

67

89

96

9594

93

9291

90

13

14

1516

17

18

1920

2122

23

24

25

26

2728

9

10

1112

29

3132

30

5

6

78

1

2

34

41 42 43 44 45 46 47 48 49 51 52 53 54 565533 34 35 36 37 38 39 40 57 58 59 60 61 62 646350


112

111

110

109

108

107

106

105

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

104

103

102

101

100 99 98 97

P0.

1

P0.

2

P0.

0

P0.

3P

0.4

P3.

2/A

DC

2

P3.

3/A

DC

3V

SS

C1/

P

INT

0/P

0.5

P3.

0/A

DC

0

P3.

1/A

DC

1

P2.

3/P

WM

2

P1.

6/S

CL

P2.

2/P

WM

1

P2.

1/P

WM

0

P2.

0/P

MW

P1.

7/S

DA

P1.

3/T

1

P2.

4/P

WM

3

VD

DP

(3.3

V)

VD

DC

1(1.

8)

-

P1.

2/IN

T2

VDRA

VIFIN1

VIFIN2VSC

SECPLL

DECDIG

PH1LF

DECBG

AVL/EWDVDRB

IREF

AGCOUT


P1

.4/R

X

VP1

XTALIN

XTALOUTVSSA1

GNDIF

-

-

-

-

FBISO/CSY

CV

BS

O/P

IP

AU

DIO

IN5

SVM

GN

D2

DV

BO

//IF

VO

/FM

RO - -

AU

DIO

IN4

SIF

AG

C/D

VB

AG

C

PLL

IF

- - --

VC

C8V

CV

BS

3/Y

3

AU

DIO

IN2 -

CV

BS

4/Y

4

AU

DIO

IN3

C4

AU

DO

UT

/AM

OU

T -

CV

BS

2/Y

2

VP

2

SV

O/IF

OU

T/C

VB

SI

C2/

C3

DE

CS

DE

M

AM

OU

T/Q

SS

O/A

UD

EE

M

EHTO

VDDcomb

VDDA1(3.3V.)BOGO

RO

HOUT

VSScomb

INSSW3

R/PR-3

BLKIN

BCLIN

B/PB-3G/Y-3

YIN(G/Y-2/CVBS/Y-X)

VOUT(SWO1)

UOUT(INSW-2)YOUT

UINVIN(R/PR-2/C-X)

(B/PB-2)

YSYNC

VP3GND3

-

P1.

O/IN

T1

P1.

1/T

0

VDDadc(1.8)VSSadc

RE

FIN

/RE

FO

UT

VGUARD/SWIO

P2.

5/P

WM

4

DE

CV

1V8

GND1

- -

P1.

5/T

XA

VL/

SW

O/S

SIF

/

PH2LF

-

VDDA3(3.3V)

VDDC4

VSSP2VSSC4

VS

SC

3

VD

DC

3

VS

SC

2V

DD

C2

GNDAVDDA(1.8V)

VDDA2(3.3V)

VREFAD_NEG

VREFAD_POS

2003 Nov 11 26



CONFIDENTIAL

Fig.8 Pin configuration “stereo” and “AV-stereo” versions with Audio DSP

69

70

8180

7978

77

76

75

74

73

72

71

88

8786

85

8483

82

6566

68

67

89

96

9594

93

9291

90

13

14

1516

17

18

1920

2122

23

24

25

26

2728

9

10

1112

29

3132

30

5

6

78

1

2

34

41 42 43 44 45 46 47 48 49 51 52 53 54 565533 34 35 36 37 38 39 40 57 58 59 60 61 62 646350

QFP-128 0.8 mm pitch “face down version”

GN

DA

112

111

110

109

108

107

106

105

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

104

103

102

101

100 99 98 97

P0.1/I2SDO1

P0.2/I2SDO2

P0.0/I2SDI1

VSSC2

P0.3/I2SCLK

P0.4/I2SWS

VDDC2

VSSC3

VD

DA

3(3.

3V)

VD

DA

(1.8

V)

VDDC3

P3.2/ADC2

P3.3/ADC3

VSSC1/P

INT0/P0.5

P3.0/ADC0

P3.1/ADC1

P2.3/PWM2

P1.6/SCL

P2.2/PWM1

P2.1/PWM0

P2.0/PMW

P1.7/SDA

P1.3/T1

P2.4/PWM3

VDDP(3.3V)

VDDC1(1.8)

VR

EF

_PO

S_L

SL

VD

DA

2(3.

3V)

P1.2/INT2

VD

RA

VIF

IN1

VIF

IN2

VS

C

SE

CP

LL

DE

CD

IG

PH

1LF

DE

CB

GA

VL/

EW

D

VD

RB

IRE

F

AG

CO

UT

DV

BIN

1/S

IFIN

1

DV

BIN

2/S

IFIN

2

P1.4/RXV

P1

XTA

LIN

XTA

LOU

T

VS

SA

1

GN

DIF

VR

EF

_PO

S_L

SR

+H

PL

VR

EF

_NE

G_H

PL+

HP

R

VR

EF

_PO

S_H

PR

VR

EF

_NE

G_L

SL+

LSR

FB

ISO

/CS

Y

CVBSO/PIP

AUDIOIN5L

SV

M

GND2

DVBO//IFVO/FMRO

DVBO/FMRO

AGC2SIF

AUDIOIN4L

SIFAGC/DVBAGC

PLLIF

AUDIOIN5R

AUDOUTLSL

AUDOUTLSR

AUDIOIN4R

VCC8V

CVBS3/Y3

AUDIOIN2L/SSIFAUDIOIN2R

CVBS4/Y4

AUDIOIN3L

AUDIOIN3R

C4

AUDOUTHPL

AUDOUTHPR

CVBS2/Y2

VP2SVO/IFOUT/CVBSI

C2/C3

DECSDEMAMOUT/QSSO/AUDEEM

EH

TO

VD

Dco

mb

VD

DA

1(3.

3V.)

BO

GO

RO

VR

EFA

D_N

EG

HO

UT

VR

EFA

D_P

OS

VS

Sco

mb

INS

SW

3

R/P

R-3

BL

KIN

BC

LIN

B/P

B-3

G/Y

-3

YIN

(G/Y

-2/C

VB

S/Y

-X)

VO

UT

(SW

O1

)U

OU

T(I

NS

W-2

)

YO

UT

UIN

VIN

(R/P

R-2

/C-X

)(B

/PB-2

)

YS

YN

C

VP

3G

ND

3

VR

EFA

D

P1.O/INT1P1.1/T0

VD

Dad

c(1.

8)

VS

Sad

c

REFIN/REFOUT

VG

UA

RD

/SW

IO

P2.5/PWM4

DECV1V8

GN

D1

AUDOUTSL

AUDOUTSR

P1.5/TX

VD

DC

4V

SS

C4

VS

SP

2

AVL/SWO/SSIF/

PH

2LF

2003 Nov 11 27



Fig.9 Pin configuration of “AV stereo” versions without Audio DSP

69

70

8180

7978

77

76

75

74

73

72

71

88

8786

85

8483

82

6566

68

67

89

96

9594

93

9291

90

13

14

1516

17

18

1920

2122

23

24

25

26

2728

9

10

1112

29

3132

30

5

6

78

1

2

34

41 42 43 44 45 46 47 48 49 51 52 53 54 565533 34 35 36 37 38 39 40 57 58 59 60 61 62 646350

QFP-128 0.8mm pitch “face down version”

112

111

110

109

108

107

106

105

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

104

103

102

101

100 99 98 97

P0.1P0.2

P0.0

P0.3

P0.4

-

P3.2/ADC2

P3.3/ADC3

VSSC1/P

INT0/P0.5

P3.0/ADC0

P3.1/ADC1

P2.3/PWM2

P1.6/SCL

P2.2/PWM1

P2.1/PWM0

P2.0/PMW

P1.7/SDA

P1.3/T1

P2.4/PWM3

VDDP(3.3V)

VDDC1(1.8)

P1.2/INT2

VD

RA

VIF

IN1

VIF

IN2

VS

C

SE

CP

LL

DE

CD

IG

PH

1LF

DE

CB

GA

VL/

EW

D

VD

RB

IRE

F

AG

CO

UT

DV

BIN

1/S

IFIN

1

DV

BIN

2/S

IFIN

2

P1.4/RX

VP

1

XTA

LIN

XTA

LOU

T

VS

SA

1

GN

DIF

- - --

FB

ISO

/CS

Y

CVBSO/PIP

AUDIOIN5L

SV

M

GND2

DVBO//IFVO/FMRO

-

-

AUDIOIN4L

SIFAGC/DVBAGC

PLLIF

AUDIOIN5R

-

-

AUDIOIN4R

VCC8V

CVBS3/Y3

AUDIOIN2L/SSIFAUDIOIN2R

CVBS4/Y4

AUDIOIN3L

AUDIOIN3R

C4

AUDOUTLSLAUDOUTLSR

CVBS2/Y2

VP2SVO/IFOUT/CVBSI

C2/C3


EH

TO

VD

Dco

mb

VD

DA

1(3.

3V.)

BO

GO

RO

HO

UT

VS

Sco

mb

INS

SW

3

R/P

R-3

BL

KIN

BC

LIN

B/P

B-3

G/Y

-3

YIN

(G/Y

-2/C

VB

S/Y

-X)

VO

UT

(SW

O1

)U

OU

T(I

NS

W-2

)

YO

UT

UIN

VIN

(R/P

R-2

/C-X

)(B

/PB-2

)

YS

YN

C

VP

3G

ND

3

P1.O/INT1P1.1/T0

VD

Dad

c(1.

8)

VS

Sad

c

REFIN/REFOUT

VG

UA

RD

/SW

IO

P2.5/PWM4

DECV1V8

GN

D1

AUDOUTSL

AUDOUTSR

P1.5/TX

AVL/SWO/SSIF/P

H2L

F

VD

DA

3(3.

3V)

VD

DC

4V

SS

C4

VS

SP

2

VSSC3

VDDC3

VSSC2

VDDC2

GN

DA

VD

DA

(1.8

V)

VD

DA

2(3.

3V)

VR

EFA

D_N

EG

VR

EFA

D_P

OS-

2003 Nov 11 28



CONFIDENTIAL

Fig.10 Pin configuration “mono” versions

69

70

8180

7978

77

76

75

74

73

72

71

88

8786

85

8483

82

6566

68

67

89

96

9594

93

9291

90

13

14

1516

17

18

1920

2122

23

24

25

26

2728

9

10

1112

29

3132

30

5

6

78

1

2

34

41 42 43 44 45 46 47 48 49 51 52 53 54 565533 34 35 36 37 38 39 40 57 58 59 60 61 62 646350

QFP-128 0.8mm pitch “face down version”

112

111

110

109

108

107

106

105

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

104

103

102

101

100 99 98 97

P0.1

P0.2

P0.0

P0.3

P0.4

P3.2/ADC2

P3.3/ADC3

VSSC1/P

INT0/P0.5

P3.0/ADC0

P3.1/ADC1

P2.3/PWM2

P1.6/SCL

P2.2/PWM1

P2.1/PWM0

P2.0/PMW

P1.7/SDA

P1.3/T1

P2.4/PWM3

VDDP(3.3V)

VDDC1(1.8)

-

P1.2/INT2

VD

RA

VIF

IN1

VIF

IN2

VS

C

SE

CP

LL

DE

CD

IG

PH

1LF

DE

CB

GA

VL/

EW

D

VD

RB

IRE

F

AG

CO

UT

DV

BIN

1/S

IFIN

1

DV

BIN

2/S

IFIN

2

P1.4/RX

VP

1

XTA

LIN

XTA

LOU

T

VS

SA

1

GN

DIF

- - --

FB

ISO

/CS

Y

CVBSO/PIP

AUDIOIN5

SV

M

GND2

DVBO//IFVO/FMRO

-

-

AUDIOIN4

SIFAGC/DVBAGC

PLLIF

-

-

-

-

VCC8V

CVBS3/Y3

AUDIOIN2-

CVBS4/Y4

AUDIOIN3

-

C4

AUDOUT/AMOUT-

CVBS2/Y2

VP2SVO/IFOUT/CVBSI

C2/C3


EH

TO

VD

Dco

mb

VD

DA

1(3.

3V.)

BO

GO

RO

HO

UT

VS

Sco

mb

INS

SW

3

R/P

R-3

BL

KIN

BC

LIN

B/P

B-3

G/Y

-3

YIN

(G/Y

-2/C

VB

S/Y

-X)

VO

UT

(SW

O1

)U

OU

T(I

NS

W-2

)

YO

UT

UIN

VIN

(R/P

R-2

/C-X

)(B

/PB-2

)

YS

YN

C

VP

3G

ND

3-

P1.O/INT1P1.1/T0

VD

Dad

c(1.

8)

VS

Sad

c

REFIN/REFOUT

VG

UA

RD

/SW

IO

P2.5/PWM4

DECV1V8

GN

D1

-

-

P1.5/TX

AVL/SWO/SSIF/P

H2L

F

VD

DA

3(3.

3V)

VD

DC

4V

SS

C4

VS

SP

2

VSSC3

VDDC3

VSSC2

VDDC2

GN

DA

VD

DA

(1.8

V)

VD

DA

2(3.

3V)

VR

EFA

D_N

EG

VR

EFA

D_P

OS

2003 Nov 11 29



CONFIDENTIAL

FUNCTIONAL DESCRIPTION OF THE 80C51The functionality of the micro-controller used on thisdevice is described here with reference to the industrystandard 80C51 micro-controller. A full description of itsfunctionality can be found in the 80C51 based 8-bitmicro-controllers - Philips Semiconductors (ref. IC20).

Features of the 80c51• 80C51 micro-controller core standard instruction set and

timing

• 0.4883µs machine cycle (Xtal frequency 24.576MHz)

• Maximum 256Kx8bit Flash Program ROM

• Maximum of 8Kx8bit Auxiliary RAM

• 12-Level Interrupt Controller for individualenable/disable with two level priority

• Two 16-bit Timer/Counter registers

• Additional 24-bit Timer (16-bit timer with 8-bit pre-scaler)

• WatchDog Timer

• Auxiliary RAM Page Pointer

• 16-bit Data pointer

• Stand-by, IDLE and Power Down (PD) modes

• 24 General I/O via individual addressable controls

• Five 6-bit Pulse Width Modulator (PWM) outputs forcontrol of TV analogue signals

• One 14-bit PWM for Voltage Synthesis tuning control

• 8-bit ADC with 4 multiplexed inputs

• High-speed I2C for ISP (up to 1.2 Mb/s)

• Remote Control Pre-processor (RCP)

• Universal Asynchronous Receiver Transmitter (UART)

Memory OrganisationThe device has the capability of a maximum of 256K Bytesof PROGRAM ROM and 8K Bytes of AUX DATA RAM forinternally.

ROM OrganisationThe 256K is arranged in eight banks of 32K. One of the32K banks is common and is always addressable. Theother banks (Bank0 to Bank6) can be accessed byselecting the right bank via the SFR ROMBK bits 2/1/0.

RAM OrganisationThe Internal Data RAM is organised into two areas, DataMemory and Special Function Registers (SFRs) as shownin Fig.12.

DATA MEMORY

The Data memory is 256 x 8-bits and occupies the addressrange 00 to FF Hex when using Indirect addressing and 00to 7F Hex when using direct addressing. The SFRs occupythe address range 80 Hex to FF Hex and are accessibleusing Direct addressing only. The lower 128 Bytes of Datamemory are mapped as shown in Fig.12. The lowest 32bytes are grouped into 4 banks of 8 registers, the next 16bytes above the register banks form a block of bitaddressable memory space. The upper 128 bytes are notallocated for any special area or functions.

Fig.11 ROM Bank switching memory map

Fig.12 Internal Data Memory

Internal RAM : “I-Data”

• Different addressing method for upper 128 Bytesaccesses RAM or SFR

7FH

Lower 128 Byte RAMDirect & Indirect

addressing

00H

FFH

128B RAMonly Indirect

addressing

80H

128B SFRonly Directaddressing

00..07 H Register-Bank0

08..0F H Register-Bank1

10..17 H Register-Bank2

18..1F H Register-Bank3

Bit-addressablespace

20..2F H

RAM30..7F H

Register-Bankselect bitsin PSW

R7R6R5R4R3R2R1R0

Special Function Registers = extension method for 80c51

R-Bank

2003 Nov 11 30



CONFIDENTIAL

SFR MEMORY

The Special Function Register (SFR) space is used forport latches, counters/timers, peripheral control, datacapture and display control, etc. These registers can onlybe accessed by direct addressing.

Sixteen of the addresses in the SFR space are both bit andbyte addressable. The bit addressable SFRs are thosewhose address ends in 0H or 8H. A summary of the SFRmap in address order is shown in Table 5.

ADD R/W Names BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

80H R/W P0 Reserved Reserved P0<5> P0<4> P0<3> P0<2> P0<1> P0<0>

81H R/W SP SP<7> SP<6> SP<5> SP<4> SP<3> SP<2> SP<1> SP<0>

82H R/W DPL DPL<7> DPL<6> DPL<5> DPL<4> DPL<3> DPL<2> DPL<1> DPL<0>

83H R/W DPH DPH<7> DPH<6> DPH<5> DPH<4> DPH<3> DPH<2> DPH<1> DPH<0>

84H R/W IEN1 - - - EX2 ERDS EUART ET2PR EBUSY

85H R/W IP1 - - - PX2 PRDS PUART PT2PR PBUSY

86H R/W RCP1 DAT<7> DAT<6> DAT<5> DAT<4> DAT<3> DAT<2> DAT<1> DAT<0>

87H R/W PCON SMOD ARD RFI WLE GF1 GF0 PD IDL

88H R/W TCON TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

89H R/W TMOD GATE C/T M1 M0 GATE C/T M1 M0

8AH R/W TL0 TL0<7> TL0<6> TL0<5> TL0<4> TL0<3> TL0<2> TL0<1> TL0<0>

8BH R/W TL1 TL1<7> TL1<6> TL1<5> TL1<4> TL1<3> TL1<2> TL1<1> TL1<0>

8CH R/W TH0 TH0<7> TH0<6> TH0<5> TH0<4> TH0<3> TH0<2> TH0<1> TH0<0>

8DH R/W TH1 TH1<7> TH1<6> TH1<5> TH1<4> TH1<3> TH1<2> TH1<1> TH1<0>

8EH R RCP3 RA<7> RA<6> RA<5> RA<4> RA<3> RA<2> RA<1> RA<0>

8FH R RCP4 RB<11> RB<10> RB<9> RB<8> RA<11> RA<10> RA<9> RA<8>

90H R/W P1 P1<7> P1<6> P1<5> P1<4> P1<3> P1<2> P1<1> P1<0>

91H R/W TP2L TP2L<7> TP2L<6> TP2L<5> TP2L<4> TP2L<3> TP2L<2> TP2L<1> TP2L<0>

92H R/W TP2H TP2H<7> TP2H<6> TP2H<5> TP2H<4> TP2H<3> TP2H<2> TP2H<1> TP2H<0>

93H R/W TP2PR TP2PR<7> TP2PR<6> TP2PR<5> TP2PR<4> TP2PR<3> TP2PR<2> TP2PR<1> TP2PR<0>

94H R/W TP2CRL - - - - - - TP2CRL<1> TP2CRL<0>

95H R/W RCP2 - - - - DAT<11> DAT<10> DAT<9> DAT<8>

96H R/W P0CFGA Reserved Reserved P0CFGA<5> P0CFGA<4> P0CFGA<3> P0CFGA<2> P0CFGA<1> P0CFGA<0>

97H R/W P0CFGB Reserved Reserved P0CFGB<5> P0CFGB<4> P0CFGB<3> P0CFGB<2> P0CFGB<1> P0CFGB<0>

98H R/W SADB SSD_ON - - DC_COMP SAD<3> SAD<2> SAD<1> SAD<0>

99H R/W S0CON SM<0> SM<1> SM<2> REN TB8 RB8 TI RI

9AH R/W S0BUF S0BUF<7> S0BUF<6> S0BUF<5> S0BUF<4> S0BUF<3> S0BUF<2> S0BUF<1> S0BUF<0>

9BH R RCP5 RB<7> RB<6> RB<5> RB<4> RB<3> RB<2> RB<1> RB<0>

9CH R TP2CL TP2CL<7> TP2CL<6> TP2CL<5> TP2CL<4> TP2CL<3> TP2CL<2> TP2CL<1> TP2CL<0>

9DH R TP2CH TP2CH<7> TP2CH<6> TP2CH<5> TP2CH<4> TP2CH<3> TP2CH<2> TP2CH<1> TP2CH<0>

9EH R/W P1CFGA P1CFGA<7> P1CFGA<6> P1CFGA<5> P1CFGA<4> P1CFGA<3> P1CFGA<2> P1CFGA<1> P1CFGA<0>

9FH R/W P1CFGB P1CFGB<7> P1CFGB<6> P1CFGB<5> P1CFGB<4> P1CFGB<3> P1CFGB<2> P1CFGB<1> P1CFGB<0>

2003 Nov 11 31



CONFIDENTIAL

A0H R/W P2 Reserved Reserved P2<5> P2<4> P2<3> P2<2> P2<1> P2<0>

A1H R/W TXT31 0 CC_TXT

B

ACTIVE PAGE 1V8GUARD GPF<11> GPF<10> GPF<9> GPF<8>

A2H R TXT32 GPF<11> 9FF<11> 9FF<10> 9FF<9> 9FF<8> 9FF<7> 9FF<6> 9FF<5>

A3H R TXT33 BFE<7> BFE<6> BFE<5> BFE<4> BFE<3> BFE<2> BFE<1> BFE<0>

A4H R TXT34 BFE<15> BFE<14> BFE<13> BFE<12> BFE<11> BFE<10> BFE<9> BFE<8>

A5H R/W Video_process - - - - - - DW_PA<1> DW_PA<0>

A6H R/W P2CFGA Reserved Reserved P2CFGA<5> P2CFGA<4> P2CFGA<3> P2CFGA<2> P2CFGA<1> P2CFGA<0>

A7H R/W P2CFGB Reserved Reserved P2CFGB<5> P2CFGB<4> P2CFGB<3> P2CFGB<2> P2CFGB<1> P2CFGB<0>

A8H R/W IE EA ES2 ECC EDET ET1 EX1 ET0 EX0

A9H R/W TXT23 NOT B <3> NOT B <2> NOT B <1> NOT B <0> East/West B DRCS B

ENABLE

BS B<1> BS B<0>

AAH R/W TXT24 BKGND OUT

B

BKGND IN B CORB OUT B CORB IN

B

TEXT OUT B TEXT IN

B

PICTURE ONOUT

B

PICTURE ONIN

B

ABH R/W TXT25 BKGND OUT

B

BKGND IN B CORB OUT B CORB IN

B

TEXT OUT B TEXT IN

B

PICTURE ONOUT

B

PICTURE ONIN

B

ACH R/W TXT26 EXTENDEDDRCS

TRANS B 0 0 SHADOWENABLE B

BOX ON

24 B

BOX ON

1-23 B

BOX ON

0 B

ADH R/W TXT28 DISPLAYBANK B<3>

DISPLAYBANK B<2>

DISPLAYBANK B<1>

DISPLAYBANK B<0>

PAGE B<3> PAGE B<2> PAGE B<1> PAGE B<0>

AEH R ADJUST_E0 ADJUSTE0<7>

ADJUSTE0<6>

ADJUSTE0<5>

ADJUSTE0<4>

ADJUST E0<3> ADJUSTE0<2>

ADJUSTE0<1>

ADJUSTE0<0>

AFH R ADJUST_E1 ADJUSTE1<7>

ADJUSTE1<6>

ADJUSTE1<5>

ADJUSTE1<4>


ADJUSTE1<1>

ADJUSTE1<0>

B0H R/W P3 Reserved Reserved Reserved Reserved P3<3> P3<2> P3<1> P3<0>

B1H R/W TXT27 - - - - RDS ON SCR B<2> SCR B<1> SCR B<0>

B2H R/W TXT18 NOT<3> NOT<2> NOT<1> NOT<0> 0 0 BS<1> BS<0>

B3H R/W TXT19 TEN TC<2> TC<1> TC<0> 0 0 TS<1> TS<0>

B4H R/W TXT20 DRCSENABLE

OSD PLANES EXTENDEDSPECIAL

GRAPHICS

CHARSELECTENABLE

OSD LANGENABLE

OSD LAN<2> OSD LAN<1> OSD LAN<0>

B5H R/W TXT21 DISP LINE<1> DISPLINES<0>

CHARSIZE<1>

CHARSIZE<0>

Reserved (0) CC ON I2C PORT EN CC/TXT

B6H R TXT22 GPF<7> GPF<6> GPF<5> GPF<4> GPF<3> GPF<2> GPF<1> GPF<0>

B7H R/W CCLIN 0 0 0 CS<4> CS<3> CS<2> CS<1> CS<0>

B8H R/W IP 0 PES2 PCC PDET PT1 PX1 PT0 PX0

B9H R/W TXT17 0 FORCEACQ<1>

FORCEACQ<0>

FORCEDISP<1>

FORCEDISP<0>

SCREENCOL<2>

SCREENCOL<1>

SCREENCOL<0>

BAH R WSS1 0 0 0 WSS<3:0>ERROR

WSS<3> WSS<2> WSS<1> WSS<0>

BBH R WSS2 0 0 0 WSS<7:4>ERROR

WSS<7> WSS<6> WSS<5> WSS<4>


2003 Nov 11 32



CONFIDENTIAL

BCH R WSS3 WSS<13:11>ERROR

WSS<13> WSS<12> WSS<11> WSS<10:8>ERROR

WSS<10> WSS<9> WSS<8>

BDH R ADJUST_E2 ADJUSTE2<7>

ADJUSTE2<6>

ADJUSTE2<5>

ADJUSTE2<4>


ADJUSTE2<1>

ADJUSTE2<0>

BEH R/W P3CFGA Reserved Reserved Reserved Reserved P3CFGA<3> P3CFGA<2> P3CFGA<1> P3CFGA<0>

BFH R/W P3CFGB Reserved Reserved Reserved Reserved P3CFGB<3> P3CFGB<2> P3CFGB<1> P3CFGB<0>

C0H R/W TXT0 X24 POSN DISPLAY X24 AUTO FRAME DISABLEHEADER

ROLL

DISPLAYSTATUS ROW

ONLY

DISABLEFRAME

VPS ON INV ON

C1H R/W TXT1 EXT PKT OFF 8 BIT ACQ OFF X26 OFF Reserved FIELDPOLARITY

H POLARITY V POLARITY

C2H R/W TXT2 ACQBANK<0>

REQ<3> REQ<2> REQ<1> REQ<0> SC<2> SC<1> SC<0>

C3H R/W TXT3 ACQBANK<3>

ACQBANK<2>

ACQBANK<1>

PRD<4> PRD<3> PRD<2> PRD<1> PRD<0>

C4H R/W TXT4 OSD BANKENABLE

QUADWIDTH

ENABLE

EAST/WEST DISABLEDOUBLEHEIGHT

0 0 TRANSENABLE

SHADOWENABLE

C5H R/W TXT5 BKGND OUT BKGND IN CORB OUT CORB IN TEXT OUT TEXT IN PICTURE ONOUT

PICTURE ONIN

C6H R/W TXT6 BKGND OUT BKGND IN CORB OUT CORB IN TEXT OUT TEXT IN PICTURE ONOUT

PICTURE ONIN

C7H R/W TXT7 STATUS ROWTOP

CURSOR ON REVEAL BOTTOM/TOP DOUBLEHEIGHT

BOX ON 24 BOX ON 1-23 BOX ON 0

C8H R/W TXT8 (Reserved)

0

FLICKERSTOPON

HUNT DISABLESPANISH

PKT 26RECEIVED

WSSRECEIVED

WSS ON (Reserved)

0

C9H R/W TXT9 CURSORFREEZE

CLEARMEMORY

A0 R<4> R<3> R<2> R<1> R<0>

CAH R/W TXT10 CHAR

16/12

- C<5> C<4> C<3> C<2> C<1> C<0>

CBH R/W TXT11 D<7> D<6> D<5> D<4> D<3> D<2> D<1> D<0>

CCH R TXT12 525/625 SYNC ROM VER<4> ROM VER<3> ROM VER<2> ROM VER<1> ROM VER<0> 1 VIDEOSIGNAL

QUALITY

CDH R/W TXT14 DISPLAYBANK<3>

DISPLAYBANK<2>

DISPLAYBANK<1>

DISPLAYBANK<0>

PAGE<3> PAGE<2> PAGE<1> PAGE<0>

CEH R/W TXT15 MICROBANK<3>

MICROBANK<2>

MICROBANK<1>

MICROBANK<0>

BLOCK<3> BLOCK<2> BLOCK<1> BLOCK<0>

CFH R ADJUST_E3 ADJUSTE3<7>

ADJUSTE3<6>

ADJUSTE3<5>

ADJUSTE3<4>


ADJUST E31> ADJUSTE3<0>

D0H R/W PSW C AC F0 RS1 RS0 OV - P

D1H R ADJUST_E4 ADJUSTE4<7>

ADJUSTE4<6>

ADJUSTE4<5>

ADJUSTE4<4>


ADJUSTE4<1>

ADJUSTE4<0>

D2H R/W TDACL TD<7> TD<6> TD<5> TD<4> TD<3> TD<2> TD<1> TD<0>

D3H R/W TDACH TPWE 0 TD<13> TD<12> TD<11> TD<10> TD<9> TD<8>

D4H R/W P3DCXOCTRL

P3DCXOMUX P3DCXOCAPS<6>

P3DCXOCAPS<5>

P3DCXOCAPS<4>

P3DCXOCAPS<3>

P3DCXOCAPS<2>

P3DCXOCAPS<1>

P3DCXOCAPS<0>

D5H R/W PWM0 PW0E Reserved (0) PW0V<5> PW0V<4> PW0V<3> PW0V<2> PW0V<1> PW0V<0>

D6H R/W PWM1 PW1E 0 PW1V<5> PW1V<4> PW1V<3> PW1V<2> PW1V<1> PW1V<0>


2003 Nov 11 33



CONFIDENTIAL

D7H R CCDAT1 CCD1<7> CCD1<6> CCD1<5> CCD1<4> CCD1<3> CCD1<2> CCD1<1> CCD1<0>

D8H R/W S1CON EN_I2CINT ENSI STA STO SI AA 0 0

D9H R S1STA STAT<4> STAT<3> STAT<2> STAT<1> STAT<0> 0 0 0

DAH R/W S1DAT DAT<7> DAT<6> DAT<5> DAT<4> DAT<3> DAT<2> DAT<1> DAT<0>

DBH R/W S1ADR ADR<6> ADR<5> ADR<4> ADR<3> ADR<2> ADR<1> ADR<0> GC

DCH R/W PWM3 PW3E 0 PW3V<5> PW3V<4> PW3V<3> PW3V<2> PW3V<1> PW3V<0>

DDH R/W PWM4 PW4E 0 PW4V<5> PW4V<4> PW4V<3> PW4V<2> PW4V<1> PW4V<0>

DEH R/W HSBIR 0 0 0 HSB<4> HSB<3> HSB<2> HSB<1> HSB<0>

DFH R/W FSBIR F/S FSB<6> FSB<5> FSB<4> FSB<3> FSB<2> FSB<1> FSB<0>

E0H R/W ACC ACC<7> ACC<6> ACC<5> ACC<4> ACC<3> ACC<2> ACC<1> ACC<0>

E1H R/W TXT29 TEN B TS B <1> TS B <0> OSD

PLANES B

OSD LANG

ENABLE B

OSD LAN B

<2>

OSD LAN B

<1>

OSD LAN B

<0>

E2H R/W TXT30 TC B <2> TC B <1> TC B <0> BOTTOM/TOPB

DOUBLEHEIGHT

B

STATUS ROWTOP B

DISPLAY X24B

DISPLAYSTATUS ROW

ONLY B

E3H R/W RDS_F0_F1 F0<3> F0<2> F0<1> F0<0> F1<3> F1<2> F1<1> F1<0>

E4H R/W PWM2 PW2E 0 PW2V<5> PW2V<4> PW2V<3> PW2V<2> PW2V<1> PW2V<0>

E5H R/W RDS_COEF_H

COEF<15> COEF<14> COEF<13> COEF<12> COEF<11> COEF<10> COEF<9> COEF<8>

E6H R/W RDS_COEF_L

COEF<7> COEF<6> COEF<5> COEF<4> COEF<3> COEF<2> COEF<1> COEF<0>

E7H R CCDAT2 CCD2<7> CCD2<6> CCD2<5> CCD2<4> CCD2<3> CCD2<2> CCD2<1> CCD2<0>

E8H R/W SAD VHI CH<1> CH<0> ST SAD<7> SAD<6> SAD<5> SAD<4>

E9H R RDS_STAT SYNC DOFL RSTD LBIN<2> LBIN<1> LBIN<0> ELB<1> ELB<0>

EAH R RDS_LDATH LDAT<15> LDAT<14> LDAT<13> LDAT<12> LDAT<11> LDAT<10> LDAT<9> LDAT<8>

EBH R RDS_LDATL LDAT<7> LDAT<6> LDAT<5> LDAT<4> LDAT<3> LDAT<2> LDAT<1> LDAT<0>

ECH R RDS_PDATH PDAT<15> PDAT<14> PDAT<13> PDAT<12> PDAT<11> PDAT<10> PDAT<9> PDAT<8>

EDH R RDS_PDATL PDAT<7> PDAT<6> PDAT<5> PDAT<4> PDAT<3> PDAT<2> PDAT<1> PDAT<0>

EFH R/W RCP6 RCP ON NFP NGP 0 0 RCPSET<2> RCPSET<1> RCPSET<0>

F0H R/W B B<7> B<6> B<5> B<4> B<3> B<2> B<1> B<0>

F1H R RDS_CNT1 BBC<5> BBC<4> BBC<3> BBC<2> BBC<1> BBC<0> EPB<1> EPB<0>

F2H R RDS_CNT2 GBC<5> GBC<4> GBC<3> GBC<2> GBC<1> PBIN<2> PBIN<1> PBIN<0>

F3H R/W RDS_CTRL1 - RBDS MBBL<5> MBBL<4> MBBL<3> MBBL<2> MBBL<1> MBBL<0>

F4H R/W RDS_CTRL2 SYM<1> SYM<0> MGBL<5> MGBL<4> MGBL<3> MGBL<2> MGBL<1> MGBL<0>

F5H R/W RDS_CTRL3 DAC<1> DAC<0> NWSY MBBG<4> MBBG<3> MBBG<2> MBBG<1> MBBG<0>

F6H R/W I2S I2S_CLK<1> I2S_CLK<0> EN_I2S_DI1 EN_I2SDO1 EN_I2SDO2 EN_I2SCLK EN_I2SWS rds_clkin

F7H R TXT35 9FF<15> 9FF<14> 9FF<13> 9FF<12> GPF<15> GPF<14> GPF<13> GPF<12>

F8H R/W TXT13 VPSRECEIVED

PAGECLEARING

525 DISPLAY 525 TEXT 625 TEXT PKT 8/30 FASTEXT 0


2003 Nov 11 34



CONFIDENTIAL

Table 5 SFR Map

A description of each the SFR bits is shown in Table 6. The SFRs are in alphabetical order.

Table 6 SFR Bit description

F9H R/W SCAVTXT SCAVEM_EN 0 0 PULSE_

WIDTH<1>

PULSE_

WIDTH<0>

EARLY<2> EARLY<1> EARLY<0>

FAH R/W XRAMP XRAMP<7> XRAMP<6> XRAMP<5> XRAMP<4> XRAMP<3> XRAMP<2> XRAMP<1> XRAMP<0>

FBH R/W ROMBK STANDBY SW_RST TEMP_140 TEMP_130 0 ROMBK<2> ROMBK<1> ROMBK<0>

FCH R TXT36 - - - BFF<4> BFF<3> BFF<2> BFF<1> BFF<0>

FDH R TEST TEST<7> TEST<6> TEST<5> TEST<4> TEST<3> TEST<2> TEST<1> TEST<0>

FEH W WDTKEY WKEY<7> WKEY<6> WKEY<5> WKEY<4> WKEY<3> WKEY<2> WKEY<1> WKEY<0>

FFH R/W WDT WDV<7> WDV<6> WDV<5> WDV<4> WDV<3> WDV<2> WDV<1> WDV<0>

Names Add BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 RESET

ACC E0H ACC<7> ACC<6> ACC<5> ACC<4> ACC<3> ACC<2> ACC<1> ACC<0> 00H

ACC<7:0> Accumulator value

ADJUST_E0 AEH ADJUSTE0<7>

ADJUSTE0<6>

ADJUSTE0<5>

ADJUSTE0<4>

ADJUSTE0<3>

ADJUSTE0<2>

ADJUSTE0<1>

ADJUSTE0<0>

XXH

ADJUST E0<7:0> For internal testing purpose.

ADJUST_E1 AFH ADJUSTE1<7>

ADJUSTE1<6>

ADJUSTE1<5>

ADJUSTE1<4>

ADJUSTE1<3>

ADJUSTE1<2>

ADJUSTE1<1>

ADJUSTE1<0>

XXH


ADJUST_E2 BDH ADJUSTE2<7>

ADJUSTE2<6>

ADJUSTE2<5>

ADJUSTE2<4>

ADJUSTE2<3>

ADJUSTE2<2>

ADJUSTE2<1>

ADJUSTE2<0>

XXH


ADJUST_E3 CFH ADJUSTE3<7>

ADJUSTE3<6>

ADJUSTE3<5>

ADJUSTE3<4>

ADJUSTE3<3>

ADJUSTE3<2>

ADJUSTE3<1>

ADJUSTE3<0>

XXH


ADJUST_E4 D1H ADJUSTE4<7>

ADJUSTE4<6>

ADJUSTE4<5>

ADJUSTE4<4>

ADJUSTE4<3>

ADJUSTE4<2>

ADJUSTE4<1>

ADJUSTE4<0>

XXH


P3DCXOCTRL D4H P3DCXOMUX P3DCXOCAPS<6>

P3DCXOCAPS<5>

P3DCXOCAPS<4>

P3DCXOCAPS<3>

P3DCXOCAPS<2>

P3DCXOCAPS<1>

P3DCXOCAPS<0>

XXH

P3DCXOMUX DCXO Cap. Bank Selection:-

0 - P3DCXOCAPS

1 - SSD Nicam

P3DCXOCAPS<6:0> DCXO Cap. Bank tuning for NICAM.

B F0H B<7> B<6> B<5> B<4> B<3> B<2> B<1> B<0> 00H

B<7:0> B Register value

CCDAT1 D7H CCD1<7> CCD1<6> CCD1<5> CCD1<4> CCD1<3> CCD1<2> CCD1<1> CCD1<0> 00H


2003 Nov 11 35



CONFIDENTIAL

CCD1<7:0> Closed Caption first data byte

CCDAT2 E7H CCD2<7> CCD2<6> CCD2<5> CCD2<4> CCD2<3> CCD2<2> CCD2<1> CCD2<0> 00H

CCD2<7:0> Closed Caption second data byte

CCLIN B7H 0 0 0 CS<4> CS<3> CS<2> CS<1> CS<0> 15H

CS<4:0> Closed caption Slice line using 525 line number.

DPH 83H DPH<7> DPH<6> DPH<5> DPH<4> DPH<3> DPH<2> DPH<1> DPH<0> 00H

DPH<7:0> Data Pointer High byte, used with DPL to address auxiliary memory

DPL 82H DPL<7> DPL<6> DPL<5> DPL<4> DPL<3> DPL<2> DPL<1> DPL<0> 00H

DPL<7:0> Data pointer low byte, used with DPH to address auxiliary memory

FSBIR DFH F/S FSB<6> FSB<5> FSB<4> FSB<3> FSB<2> FSB<1> FSB<0> 00H

F/S 0 - the duty cycle of SCLH-out is according the Standard mode requirement.

1 - the duty cycle of SCLH-out is according the Fast mode requirement.

FSB<6:0> Determine the SCLH-out frequency in F/S-mode

HSBIR DEH 0 0 0 HSB<4> HSB<3> HSB<2> HSB<1> HSB<0> 00H

HSBIR<4:0> Determine the SCLH-out frequency in Hs-mode

I2S F6H I2S_CLK<1> I2S_CLK<0> EN_I2SDI1 EN_I2SDO1 EN_I2SDO2 EN_I2SCLK EN_I2SWS rds_clkin 00H

I2S_CLK<1:0> I2S Clock Output Selection:-

00 - 256fs

01 - 128fs

10 - 64fs

11 - invalid

fs = 32kHz

EN_I2SDI1 Enable I2S Data Input 1 alternative function to port pin:-

0 - GPIO function

1 - I2S Data Input 1

EN_I2SDO1 Enable I2S Data Output 1 alternative function to port pin:-

0 - GPIO function

1 - I2S Data Output 1

EN_I2SDO2 Enable I2S Data Output 2 alternative function to port pin:-

0 - GPIO function

1 - I2S Data Output 2

EN_I2SCLK Enable I2S Clock Output alternative function to port pin:-

0 - GPIO function

1 - I2S Clock Output

EN_I2SWS Enable I2S Word Select alternative function to port pin:-

0 - GPIO function

1 - I2S Word Select

rds_clkin For RDS debugging / evaluation only.

IE A8H EA ES2 ECC EDET ET1 EX1 ET0 EX0 00H

EA Disable all interrupts (0), or use individual interrupt enable bits (1)

ES2 Enable I2C interrupt.

ECC Enable Closed Caption interrupt

EDET Enable Supply Dip Monitor Interrupt.

ET1 Enable Timer 1 interrupt


2003 Nov 11 36



CONFIDENTIAL

EX1 Enable External interrupt 1

ET0 Enable Timer 0 interrupt

EX0 Enable External interrupt 0

IEN1 84H - - - EX2 ERDS EUART ET2PR EBUSY 00H

EX2 Enable External Interrupt 2.

ERDS Enable RDS/RBDS Interrupt.

EUART Enable UART Interrupt.

ET2PR Enable Timer 2 interrupt

EBUSY Enable BUSY interrupt

IP B8H 0 PES2 PCC PDET PT1 PX1 PT0 PX0 00H

PES2 Priority I2C interrupt

PCC Priority Closed Caption Interrupt

PDET Priority Supply Dip Monitor Interrupt.

PT1 Priority Timer 1 interrupt

PX1 Priority External Interrupt 1

PT0 Priority Timer 0 interrupt

PX0 Priority External Interrupt 0

IP1 85H - - - PX2 PRDS PUART PT2PR PBUSY 00H

PX2 Priority External Interrupt 2.

PRDS Priority RDS/RBDS Interrupt.

PUART Priority UART Interrupt.

PT2PR Priority Timer 2 interrupt

PBUSY Priority BUSY Interrupt

P0 80H Reserved Reserved P0<5> P0<4> P0<3> P0<2> P0<1> P0<0> 00H

P0<5:0> Port 0 I/O register connected to external pins

P1 90H P1<7> P1<6> P1<5> P1<4> P1<3> P1<2> P1<1> P1<0> C3H


P2 A0H Reserved Reserved P2<5> P2<4> P2<3> P2<2> P2<1> P2<0> 00H


P3 B0H Reserved Reserved Reserved Reserved P3<3> P3<2> P3<1> P3<0> C0H


P0CFGA 96H Reserved Reserved P0CFGA<5> P0CFGA<4> P0CFGA<3> P0CFGA<2> P0CFGA<1> P0CFGA<0> 00H

P0CFGB 97H Reserved Reserved P0CFGB<5> P0CFGB<4> P0CFGB<3> P0CFGB<2> P0CFGB<1> P0CFGB<0> 00H

P0CFGB<x>/P0CFGA<x> = 00 MODE 0 Open Drain

P0CFGB<x>/P0CFGA<x> = 01 MODE 1 Quasi Bi-Directional

P0CFGB<x>/P0CFGA<x> = 10 MODE2 High Impedance


2003 Nov 11 37



CONFIDENTIAL

P0CFGB<x>/P0CFGA<x> = 11 MODE3 Push Pull

P1CFGA 9EH P1CFGA<7> P1CFGA<6> P1CFGA<5> P1CFGA<4> P1CFGA<3> P1CFGA<2> P1CFGA<1> P1CFGA<0> 00H

P1CFGB 9FH P1CFGB<7> P1CFGB<6> P1CFGB<5> P1CFGB<4> P1CFGB<3> P1CFGB<2> P1CFGB<1> P1CFGB<0> 00H





P2CFGA A6H Reserved Reserved P2CFGA<5> P2CFGA<4> P2CFGA<3> P2CFGA<2> P2CFGA<1> P2CFGA<0> 00H

P2CFGB A7H Reserved Reserved P2CFGB<5> P2CFGB<4> P2CFGB<3> P2CFGB<2> P2CFGB<1> P2CFGB<0> 00H





P3CFGA BEH Reserved Reserved Reserved Reserved P3CFGA<3> P3CFGA<2> P3CFGA<1> P3CFGA<0>00H

P3CFGB BFH Reserved Reserved Reserved Reserved P3CFGB<3> P3CFGB<2> P3CFGB<1> P3CFGB<0>00H


P3CFGB<x>/P3CFGA<x> = 01 MODE 1 Quasi Bi-directional



PCON 87H SMOD ARD RFI WLE GF1 GF0 PD IDL 00H

SMOD UART Baud Rate Double Control

ARD Auxiliary RAM Disable, All MOVX instructions access the off-chip data memory.

‘0’: Enable

‘1’: Disable

In application mode, this bit should keep ‘0’.

RFI Disable ALE during internal access to reduce Radio Frequency Interference

’0’: Enable

’1’: Disable

WLE Watch Dog Timer enable

’0’: Disable

’1’: Enable

GF1 General purpose flag

GF0 General purpose flag

PD Power-down activation bit

IDL Idle mode activation bit

PSW D0H C AC F0 RS<1> RS<0> OV - P 00H

C Carry Bit

AC Auxiliary Carry bit

F0 Flag 0, General purpose flag


2003 Nov 11 38



CONFIDENTIAL

RS<1:0> Register Bank selector bits

RS<1:0> = 00, Bank0 (00H - 07H)

RS<1:0> = 01, Bank1 (08H - 0FH)

RS<1:0> = 10, Bank2 (10H - 17H)

RS<1:0> = 11, Bank3 (18H - 1FH)

OV Overflow flag

P Parity bit

PWM0 D5H PW0E Reserved (0) PW0V<5> PW0V<4> PW0V<3> PW0V<2> PW0V<1> PW0V<0> 00H

PW0E 0 - Disable Pulse Width Modulator 0

1 - Enable Pulse Width Modulator 0

PW0V<5:0> Pulse Width Modulator high time

PWM1 D6H PW1E 0 PW1V<5> PW1V<4> PW1V<3> PW1V<2> PW1V<1> PW1V<0> 00H




PWM2 E4H PW2E 0 PW2V<5> PW2V<4> PW2V<3> PW2V<2> PW2V<1> PW2V<0> 00H




PWM3 DCH PW3E 0 PW3V<5> PW3V<4> PW3V<3> PW3V<2> PW3V<1> PW3V<0> 00H




PWM4 DDH PW4E 0 PW4V<5> PW4V<4> PW4V<3> PW4V<2> PW4V<1> PW4V<0> 00H




RCP1 86H DAT<7> DAT<6> DAT<5> DAT<4> DAT<3> DAT<2> DAT<1> DAT<0> 00H

DAT<7:0> Data location shared by CDIV<7:0>, AL<7:0>, AH<7:0>, BL<7:0>, BH<7:0>

Reset value of CDIV<7:0>, AL<7:0>, and BL<7:0> are 00H; reset value of AH<7:0> and BH<7:0> are FFH.

RCP2 95H - - - - DAT<11> DAT<10> DAT<9> DAT<8> X0H

DAT<11:8> Data location shared by CDIV<11:8>, AL<11:8>, AH<11:8>, BL<11:8> and BH<11:8>

Reset value of CDIV<11:8>, AL<11:8>, and BL<11:8> are 0H; reset value of AH<11:8> and BH<11:8> are FH.

RCP3 8EH RA<7> RA<6> RA<5> RA<4> RA<3> RA<2> RA<1> RA<0> 00H

RA<7:0> LOW time Result (bit 7:0) minus AL

RCP4 8FH RB<11> RB<10> RB<9> RB<8> RA<11> RA<10> RA<9> RA<8> 00H

RB<11:8> High time Result (bit 11:8)

RA<11:8> LOW time Result (bit 11:8)

RCP5 9BH RB<7> RB<6> RB<5> RB<4> RB<3> RB<2> RB<1> RB<0> 00H

RB<7:0> High time Result (bit 7:0) minus BL

RCP6 EFH RCP ON NFP NGP 0 0 RCPSET<2> RCPSET<1> RCPSET<0> 00H


2003 Nov 11 39



CONFIDENTIAL

RCP ON 0 - Remote Control Pre-processor disable

1 - Remote Control Pre-processor enable

NFP 0 - First Pulse

1 - Not First Pulse

NGP 0 - Good Pulse

1 - Not Good Pulse

RCPSET<2:0> Define DAT<11:0> value:-

000 - CDIV<11:0> is accessed via DAT<11:0>, default = 000H

001 - AL<11:0> is accessed via DAT<11:0>, default = 000H

010 - AH<11:0> is accessed via DAT<11:0>, default = FFFH

011 - BL<11:0> is accessed via DAT<11:0>, default = 000H

100 - BH<11:0> is accessed via DAT<11:0>, default = FFFH

101 - SPF<11:0> is accessed via DAT<11:0>, default = 003H

RDS_STAT E9H SYNC DOFL RSTD LBIN<2> LBIN<1> LBIN<0> ELB<1> ELB<0> 1CH

SYNC Synchronization found

DOFL Data overflow flag

RSTD Reset detected

LBIN<2:0> Last block identification

LBIN<2:0>=000, block A

LBIN<2:0>=001, block B

LBIN<2:0>=010, block C

LBIN<2:0>=011, block D

LBIN<2:0>=100, block C’

LBIN<2:0>=101, block E (RBDS mode)

LBIN<2:0>=110, invalid block E (RDS mode)

LBIN<2:0>=111, invalid block

ELB<1:0> Error status last block

ELB<1:0>=00, no errors detect

ELB<1:0>=01, max. 2 bits

ELB<1:0>=10, max. 5 bits

ELB<1:0>=11, uncorrectable block

RDS_LDATH EAH LDAT<15> LDAT<14> LDAT<13> LDAT<12> LDAT<11> LDAT<10> LDAT<9> LDAT<8> 00H

LDAT<15:8> Last processed block data high byte

RDS_LDATL EBH LDAT<7> LDAT<6> LDAT<5> LDAT<4> LDAT<3> LDAT<2> LDAT<1> LDAT<0> 00H

LDAT<7:0> Last processed block data low byte

RDS_PDATH ECH PDAT<15> PDAT<14> PDAT<13> PDAT<12> PDAT<11> PDAT<10> PDAT<9> PDAT<8> 00H

PDAT<15:8> Previous processed block data high byte

RDS_PDATL EDH PDAT<7> PDAT<6> PDAT<5> PDAT<4> PDAT<3> PDAT<2> PDAT<1> PDAT<0> 00H

PDAT<7:0> Previous processed block data low byte

RDS_CNT1 F1H BBC<5> BBC<4> BBC<3> BBC<2> BBC<1> BBC<0> EPB<1> EPB<0> 00H

BBC<5:0> Bad Blocks Counter

EPB<1:0> Error Status Previous Block

EPB<1:0>=00 - no errors detected

EPB<1:0>=01 - burst error of maximum 2 bits corrected

EPB<1:0>=10 - burst error of maximum 5 bits corrected

EPB<1:0>=11 - uncorrectable block

RDS_CNT2 F2H GBC<5> GBC<4> GBC<3> GBC<2> GBC<1> PBIN<2> PBIN<1> PBIN<0> 07H

GBC<5:1> Good Blocks Counter (Only 5 MSBs are available)


2003 Nov 11 40



CONFIDENTIAL

PBIN<2:0> Previous Block Identification

PBIN<2:0>=000 - block A

PBIN<2:0>=001 - block B

PBIN<2:0>=010 - block C

PBIN<2:0>=011 - block D

PBIN<2:0>=100 - block C’

PBIN<2:0>=101 - block E (RBDS mode)

PBIN<2:0>=110 - invalid block E (RDS mode)

PBIN<2:0>=111 - invalid block

RDS_CTRL1 F3H - RBDS MBBL<5> MBBL<4> MBBL<3> MBBL<2> MBBL<1> MBBL<0> 20H

RBDS Allow RBDS ‘E’ Block

‘0’ - RDS mode

‘1’ - RBDS mode

MBBL<5:0> Max Bad Block Lose

RDS_CTRL2 F4H SYM<1> SYM<0> MGBL<5> MGBL<4> MGBL<3> MGBL<2> MGBL<1> MGBL<0> 20H

SYM<1:0> Synchronization Mode

SYM<1:0>=00 - no error correction

SYM<1:0>=01 - error correction of a burst error maximum 2 bits

SYM<1:0>=10 - error correction of a burst error maximum 5 bits

SYM<1:0>=11 - no error correction

MGBL<5:0> Max Good Block Lose

RDS_CTRL3 F5H DAC<1> DAC<0> NWSY MBBG<4> MBBG<3> MBBG<2> MBBG<1> MBBG<0> 00H

DAC<1:0> Data output control

DAC<1:0>=00, standard mode

DAC<1:0>=01, fast PI search mode

DAC<1:0>=10, reduced data request

DAC<1:0>=11, decoder bypass

NWSY Start new synchronization

MBBG<4:0> Max bad blocks gain

RDS_F0_F1 E3H F0<3> F0<2> F0<1> F0<0> F1<3> F1<2> F1<1> F1<0> 32H

F0<3:0> Coarse Division Factor F0

F1<3:0> Coarse Division Factor F1

RDS_COEF_H E5H COEF<15> COEF<14> COEF<13> COEF<12> COEF<11> COEF<10> COEF<9> COEF<8> 4BH

COEF<15:8> DCS Coefficient High Byte

RDS_COEF_L E6H COEF<7> COEF<6> COEF<5> COEF<4> COEF<3> COEF<2> COEF<1> COEF<0> CAH

COEF<7:0> DCS Coefficient Low Byte

ROMBK FBH STANDBY SW_RST TEMP_140 TEMP_130 0 ROMBK<2> ROMBK<1> ROMBK<0> 00H

STANDBY 0 - Disable Stand-by Mode

1 - Enable Stand-by Mode

SW_RST 0 - Disable Software Reset

1 - Enable Software Reset

TEMP_140 0 - Temperature of the device below 140C

1 - Temperature of the device above 140C

TEMP_130 0 - Temperature of the device below 130C

1 - Temperature of the device above 130C


2003 Nov 11 41



CONFIDENTIAL

ROMBK<2:0> ROM Bank selection

ROMBK<2:0> = 000, Bank0

ROMBK<2:0> = 001, Bank1

ROMBK<2:0> = 010, Bank2

ROMBK<2:0> = 011, Bank3

ROMBK<2:0> = 100, Bank4

ROMBK<2:0> = 101, Bank5

ROMBK<2:0> = 110, Bank6

ROMBK<2:0> = 111, Reserved

S0BUF 9AH S0BUF<7> S0BUF<6> S0BUF<5> S0BUF<4> S0BUF<3> S0BUF<2> S0BUF<1> S0BUF<0> 00H

S0BUF<7:0> UART data buffer

S0CON 99H SM<0> SM<1> SM<2> REN TB8 RB8 TI RI 00H

SM<0:1> UART Mode selection bits

SM<0:1> = 00, Shift Register

SM<0:1> = 01, 8-bit UART (variable baud rate)

SM<0:1> = 10, 9-bit UART

SM<0:1> = 11, 9-bit UART (variable baud rate)

SM<2> Enables the multi processor communication feature in modes 2 and 3. In mode 2 or 3, if SM2 is set, then RI will not be activated, RB8 and S0BUF will notbe loaded if thereceived 9th data bit is ’0’. In mode 1, if SM2 is set, then RI will not be activated, RB8 and S0BUF will not be loaded if no valid stop bit was received. In mode 0, SM2 has noinfluence.

REN Enables serial reception. Set by software to enable reception. Cleared by software to disable reception.

TB8 Is the 9th data bit that will be transmitted in modes 2 and 3. Set or cleared by software as desired.

RB8 In modes 2 and 3, RB8 is the 9th data bit that was received. In mode 1, if SM2 is ’0’, RB8 is the stop bit that was received. In mode 0, RB8 is not used. Loading of RB8 in modes1, 2 and 3 depends on SM2.

TI Is the transmit interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the other modes. Must be cleared by software.

RI Is the receive interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except seeSM2). Must be cleared by software.

S1ADR DBH ADR<6> ADR<5> ADR<4> ADR<3> ADR<2> ADR<1> ADR<0> GC 00H

ADR<6:0> I2C Slave Address

GC 0 - Disable I2C general call address

1 - Enable I2C general call address

S1CON D8H EN_I2CINT ENSI STA STO SI AA 0 0 00H

EN_I2CINT Setting by software

0- the I2C interrupt signal is always non-active

1- the I2C interrupt signal is activated when if the SI is set

ENSI 0 - Disable I2C interface

1 - Enable I2C interface

STA START flag. When this bit is set in slave mode, the hardware checks the I2C bus and generates a START condition if the bus is free or after the bus becomes free. If the deviceoperates in master mode it will generate a repeated START condition.

STO STOP flag. If this bit is set in a master mode a STOP condition is generated. A STOP condition detected on the I2C bus clears this bit. This bit may also be set in slave mode inorder to recover from an error condition. In this case no STOP condition is generated to the I2C bus, but the hardware releases the SDA and SCL lines and switches to the notselected receiver mode. The STOP flag is cleared by the hardware

SI Serial Interrupt flag. This flag is set and an interrupt request is generated, after any of the following events occur:

-A START condition is generated in master mode.

-The own slave address has been received during AA=1

-The general call address has been received while S1ADR.GC and AA=1

-A data byte has been received or transmitted in master mode (even if arbitration is lost)

-A data byte has been received or transmitted as selected slave

A STOP or START condition is received as selected slave receiver or transmitter

While the SI flag is set, SCL remains LOW and the serial transfer is suspened.SI must be reset by software.


2003 Nov 11 42



CONFIDENTIAL

AA Assert Acknowledge flag. When this bit is set, an acknowledge is returned after any one of the following conditions

-Own slave address is received.

-General call address is received(S1ADR.GC=1)

-A data byte is received, while the device is programmed to be a master receiver

-A data byte is received, while the device is selected slave receiver

When the bit is reset, no acknowledge is returned. Consequently, no interrupt is requested when the own address or general call address is received.

S1DAT DAH DAT<7> DAT<6> DAT<5> DAT<4> DAT<3> DAT<2> DAT<1> DAT<0> 00H

DAT<7:0> I2C Data

S1STA D9H STAT<4> STAT<3> STAT<2> STAT<1> STAT<0> 0 0 0 F8H

STAT<4:0> I2C Interface Status

SAD E8H VHI CH<1> CH<0> ST SAD<7> SAD<6> SAD<5> SAD<4> 00H

VHI 0 - Analogue input voltage less than or equal to DAC voltage

1 - Analogue input voltage greater then DAC voltage

CH<1:0> ADC Input channel select

CH<1:0> = 00,ADC3

CH<1:0> = 01,ADC0

CH<1:0> = 10,ADC1

CH<1:0> = 11,ADC2

ST Initiate voltage comparison between ADC input Channel and SAD<7:0> value

Note: Set by Software and reset by Hardware

SAD<7:4> Most Significant nibble of DAC input word

SADB 98H SSD_ON - - DC_COMP SAD<3> SAD<2> SAD<1> SAD<0> 80H

SSD_ON 0 - Disable SSD Function

1 - Enable SSD Function

DC_COMP 0 - Disable DC Comparator mode

1 - Enable DC Comparator mode

SAD<3:0> Least Significant nibble of 8 bit SAD value

SCAVTXT F9H SCAVEM_

EN

0 0 PULSE_

WIDTH<1>

PULSE_

WIDTH<0>

EARLY<2> EARLY<1> EARLY<0> 00H

SCAVEM_EN 0 - Disable scavem text output for R, G, and B signals1 - Enable scavem text output for R, G, and B signals

PULSE_WIDTH<1:0> SCAVEM Text signal pulse widthPULSE_WIDTH<1:0>=00, 37nsPULSE_WIDTH<1:0>=01, 74nsPULSE_WIDTH<1:0>=10, 111nsPULSE_WIDTH<1:0>=11, 148ns

EARLY<2:0> SCAVEM Text output to Video Signal Processor earlier than R,G, and B signalsEARLY<2:0>=000, 0 nsEARLY<2:0>=001, 74 nsEARLY<2:0>=010, 111 nsEARLY<2:0>=011, 148 nsEARLY<2:0>=100, 185 nsEARLY<2:0>=101, 212 nsEARLY<2:0>=110, 259 nsEARLY<2:0>=111, 296 ns

SP 81H SP<7> SP<6> SP<5> SP<4> SP<3> SP<2> SP<1> SP<0> 07H

SP<7> Stack Pointer

TCON 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00H

TF1 Timer 1 overflow Flag. Set by hardware on Timer/Counter overflow.Cleared by hardware when processor vectors to interrupt routine

TR1 Timer 1 Run control bit. Set/Cleared by software to turn Timer/Counter on/off

TF0 Timer 0 overflow Flag. Set by hardware on Timer/Counter overflow.Cleared by hardware when processor vectors to interrupt routine


2003 Nov 11 43



CONFIDENTIAL

TR0 Timer 0 Run control bit. Set/Cleared by software to turn Timer/Counter on/off

IE1 Interrupt 1 Edge flag (both edges generate flag). Set by hardware when external interrupt edge detected.Cleared by hardware when interrupt processed.

IT1 Interrupt 1 Type control bit. Set/Cleared by Software to specify edge/low level triggered external interrupts.

IE0 Interrupt 0 Edge l flag. Set by hardware when external interrupt edge detected.Cleared by hardware when interrupt processed.

IT0 Interrupt 0 Type flag.Set/Cleared by Software to specify falling edge/low level triggered external interrupts

TDACH D3H TPWE 0 TD<13> TD<12> TD<11> TD<10> TD<9> TD<8> 00H

TPWE 0 - Disable Tuning Pulse Width Modulator

1 - Enable Tuning Pulse Width Modulator

TD<13:8> Tuning Pulse Width Modulator High Byte

TDACL D2H TD<7> TD<6> TD<5> TD<4> TD<3> TD<2> TD<1> TD<0> 00H

TD<7:0> Tuning Pulse Width Modulator Low Byte

TH0 8CH TH0<7> TH0<6> TH0<5> TH0<4> TH0<3> TH0<2> TH0<1> TH0<0> 00H

TH0<7:0> Timer 0 high byte

TH1 8DH TH1<7> TH1<6> TH1<5> TH1<4> TH1<3> TH1<2> TH1<1> TH1<0> 00H

TH1<7:0> Timer 1 high byte

TL0 8AH TL0<7> TL0<6> TL0<5> TL0<4> TL0<3> TL0<2> TL0<1> TL0<0> 00H

TL0<7:0> Timer 0 low byte

TL1 8BH TL1<7> TL1<6> TL1<5> TL1<4> TL1<3> TL1<2> TL1<1> TL1<0> 00H

TL1<7:0> Timer 1 low byte

TMOD 89H GATE C/T M1 M0 GATE C/T M1 M0 00H

Timer / Counter 1 Timer / Counter 0

GATE Gating Control Timer /Counter 1

C/T Counter/Timer 1 selector

M1,M0 Mode control bits Timer/Counter 1

M1,M0 = 00, 8 bit timer or 8 bit counter with divide by 32 pre-scaler

M1,M0 = 01, 16 bit time interval or event counter

M1,M0 = 10, 8 bit time interval or event counter with automatic reload upon overflow. Reload value stored in TH1

M1,M0 = 11, stopped

GATE Gating control Timer/Counter 0

C/T Counter/Timer 0 selector

M1,M0 Mode Control bits Timer/Counter 0

M1,M0 = 00, 8 bit timer or 8 bit counter with divide by 32 pre-scaler

M1,M0 = 01, 16 bit time interval or event counter

M1,M0 = 10, 8 bit time interval or event counter with automatic reload upon overflow. Reload value stored in TH0

M1,M0 = 11, one 8 bit time interval or event counter and one 8 bit time interval counter

TP2CL 9CH TP2CL<7> TP2CL<6> TP2CL<5> TP2CL<4> TP2CL<3> TP2CL<2> TP2CL<1> TP2CL<0> 00H

TP2CL<7:0> Indicate the low byte of the Time 2 current value.

TP2CH 9DH TP2CH<7> TP2CH<6> TP2CH<5> TP2CH<4> TP2CH<3> TP2CH<2> TP2CH<1> TP2CH<0> 00H

TP2CH<7:0> Indicate the high byte of the Time 2 current value.


2003 Nov 11 44



CONFIDENTIAL

TP2H 92H TP2H<7> TP2H<6> TP2H<5> TP2H<4> TP2H<3> TP2H<2> TP2H<1> TP2H<0> 00H

TP2H<7:0> Timer 2 high byte, never change unless updated by the software.

TP2L 91H TP2L<7> TP2L<6> TP2L<5> TP2L<4> TP2L<3> TP2L<2> TP2L<1> TP2L<0> 00H

TP2L<7:0> Timer 2 low byte, never change unless updated by the software.

TP2PR 93H TP2PR<7> TP2PR<6> TP2PR<5> TP2PR<4> TP2PR<3> TP2PR<2> TP2PR<1> TP2PR<0> 00H

TP2PR<7:0> Timer 2 Pre-scaler, never change unless updated by the software

TP2CRL 94H - - - - - - TP2CRL<1> TP2CRL<0> 00H

TP2CRL<0> Timer 2 Control.

0 - Timer 2 disabled.

1 - Timer 2 enabled.

TP2CRL<1> Timer 2 Status.

0 - No Overflow.

1 - Overflow.

TEST FDH TEST<7> TEST<6> TEST<5> TEST<4> TEST<3> TEST<2> TEST<1> TEST<0> A0H

TEST<7:0> For internal testing use.

TXT0 C0H X24 POSN DISPLAY X24 AUTOFRAME

DISABLEHEADER

ROLL

DISPLAYSTATUS ROW

ONLY

DISABLEFRAME

VPS ON INV ON 00H

X24 POSN 0 - Store X/24 in extension memory

1 - Store X/24 in basic page memory with packets 0 to 23

DISLAY X24 0 - Display row 24 from basic page memory

1 - Display row 24 from appropriate location in extension memory

AUTO FRAME 0 - Normal Frame output

1 - Frame output is switched off automatically if any video displayed

DISABLE HEADER ROLL 0 - Write rolling headers and time to current display page

1 - Disable writing of rolling headers and time to into memory

DISPLAY STATUS ROWONLY

0 - Display normal page rows 0 to 24

1- Display only row 24

DISABLE FRAME 0 - Normal Frame output

1 - Force Frame output to be low (0)

VPS ON 0 - VPS acquisition off

1 - VPS acquisition on

INV ON 0 - Inventory page off

1 - Inventory page on

TXT1 C1H EXT PKT OFF 8 BIT ACQ OFF X26 OFF full-field FIELDPOLARITY

H POLARITY V POLARITY 00H

EXT PKT OFF 0 - Acquire extension packets X/24,X/27,8/30/X

1 - Disable acquisition of extension packets

8 BIT 0 - Error check and/or correct packets 0 to 24

1 - Disable checking of packets 0 to 24 written into memory

ACQ OFF 0 - Write requested data into display memory

1 - Disable writing of data into Display memory

X26 OFF 0 - Enable automatic processing of X/26 data

1 - Disable automatic processing of X/26 data

full-field unused, must keep reset value -> ‘0’


2003 Nov 11 45



CONFIDENTIAL

FIELD POLARIY 0 - Vsync pulse in first half of line during even field

1 - Vsync pulse in second half of line during even field

For MCM package, this bit should be set to ‘1’

H POLARITY 0 - Hsync reference edge is positive going

1 - Hsync reference edge is negative going

V POLARITY 0 - Vsync reference edge is positive going

1 - Vsync reference edge is negative going

TXT2 C2H ACQBANK<0>

REQ<3> REQ<2> REQ<1> REQ<0> SC<2> SC<1> SC<0> 00H

ACQ_BANK<0> Should combine TXT3 ACQ_BANK<3:1>

REQ<3:0> Page request

SC<2:0> Start column of page request

TXT3 C3H ACQBANK<3>

ACQBANK<2>

ACQBANK<1>

PRD<4> PRD<3> PRD<2> PRD<1> PRD<0> 00H

ACQ_BANK

<3:1>

Combine with TXT2 ACQ_BANK<0>

0000 - Select BLOCK 0 ~ 9 for acquisition storage

0001 - Reserved

0010 - Reserved

0011 - Reserved

0100 - Reserved

0101 - Reserved

0110 - Reserved

0111 - Reserved

1000 - Reserved

1001 - Reserved

1010 - Reserved

1011 - Reserved

1100 - Reserved

1101 - Reserved

1110 - Reserved

1111 - Reserved

PRD<4:0> Page Request data

TXT4 C4H OSD BANKENABLE

QUADWIDTH

ENABLE

EAST/WEST DISABLEDBL HEIGHT

0 0 TRANSENABLE

SHADOWENABLE

00H

OSD BANK ENABLE 0 - Only alpha numeric OSD characters available, 32 locations

1 - Alternate OSD location available via graphic attribute, additional 32 location

QUAD WIDTH ENABLE 0 - Disable display of Quadruple width characters

1 - Enable display of Quadruple width characters

EAST/WEST 0 - Western language selection of character codes A0 to FF

1 - Eastern character selection of character codes A0 to FF

DISABLE DOUBLEHEIGHT

0 - Allow normal decoding of double height characters

1 - Disable normal decoding of double height characters

TRANS ENABLE 0 - Display black background as normal

1 - Display black background as video

SHADOW ENABLE 0 - Disable display of shadow/fringing

1 - Display shadow/ fringe (default SE black)

TXT5 C5H BKGND OUT BKGND IN COR OUT COR IN TEXT OUT TEXT IN PICTURE ONOUT

PICTURE ONIN

03H

BKGND OUT 0 - Background colour not displayed outside teletext boxes(teletext page)

1 - Background colour displayed outside teletext boxes(teletext page)

BKGND IN 0 - Background colour not displayed inside teletext boxes(teletext page)

1 - Background colour displayed inside teletext boxes(teletext page)


2003 Nov 11 46



CONFIDENTIAL

COR OUT 0 - COR not active outside teletext and OSD boxes(teletext page)

1 - COR active outside teletext and OSD boxes(teletext page)

COR IN 0 - COR not active inside teletext and OSD boxes(teletext page)

1 - COR active inside teletext and OSD boxes(teletext page)

TEXT OUT 0 - TEXT not displayed outside teletext boxes(teletext page)

1 - TEXT displayed outside teletext boxes(teletext page)

TEXT IN 0 - TEXT not displayed inside teletext boxes(teletext page)

1 - TEXT displayed inside teletext boxes(teletext page)

PICTURE ON OUT 0 - VIDEO not displayed outside teletext boxes(teletext page)

1 - VIDEO displayed outside teletext boxes(teletext page)

PICTURE ON IN 0 - VIDEO not displayed inside teletext boxes(teletext page)

1 - VIDEO displayed inside teletext boxes(teletext page)

TXT6 C6H BKGND OUT BKGND IN COR OUT COR IN TEXT OUT TEXT IN PICTURE ONOUT

PICTURE ONIN

03H

BKGND OUT 0 - Background colour not displayed outside teletext boxes(newsflash/subtitle)

1 - Background colour displayed outside teletext boxes(newsflash/subtitle)

BKGND IN 0 - Background colour not displayed inside teletext boxes(newsflash/subtitle)

1 - Background colour displayed inside teletext boxes(newsflash/subtitle)

COR OUT 0 - COR not active outside teletext and OSD boxes(newsflash/subtitle)

1 - COR active outside teletext and OSD boxes(newsflash/subtitle)

COR IN 0 - COR not active inside teletext and OSD boxes(newsflash/subtitle)

1 - COR active inside teletext and OSD boxes(newsflash/subtitle)

TEXT OUT 0 - TEXT not displayed outside teletext boxes(newsflash/subtitle)

1 - TEXT displayed outside teletext boxes(newsflash/subtitle)

TEXT IN 0 - TEXT not displayed inside teletext boxes(newsflash/subtitle)

1 - TEXT displayed inside teletext boxes(newsflash/subtitle)

PICTURE ON OUT 0 - VIDEO not displayed outside teletext boxes(newsflash/subtitle)

1 - VIDEO displayed outside teletext boxes(newsflash/subtitle)

PICTURE ON IN 0 - VIDEO not displayed inside teletext boxes(newsflash/subtitle)

1 - VIDEO displayed inside teletext boxes(newsflash/subtitle)

TXT7 C7H STATUS ROWTOP

CURSOR ON REVEAL BOTTOM/TOP

DOUBLEHEIGHT

BOX ON 24 BOX ON 1-23 BOX ON 0 00H

STATUS ROW TOP 0 - Display memory row 24 information below teletext page (on display row 24)

1 - Display memory row 24 information above teletext page (on display row 0)

CURSOR ON 0 - Disable display of cursor

1 - Display cursor at position given by TXT9 and TXT10

REVEAL 0 - Display as spaces characters in area with conceal attribute set

1 - Display characters in area with conceal attribute set

BOTTOM/TOP 0 - Display memory rows 0 to 11 when double height bit is set

1 - Display memory rows 12 to 23 when double height bit is set

DOUBLE HEIGHT 0 - Display each characters with normal height

1 - Display each character as twice normal height.

BOX ON 24 0 - Disable display of teletext boxes in memory row 24

1 - Enable display of teletext boxes in memory row 24

BOX ON 1-23 0 - Disable display of teletext boxes in memory row 1 to 23

1 - Enable display of teletext boxes in memory row 1 to 23

BOX ON 0 0 - Disable display of teletext boxes in memory row 0

1 - Enable display of teletext boxes in memory row 0


2003 Nov 11 47



CONFIDENTIAL

TXT8 C8H (Reserved)

0

FLICKERSTOPON

HUNT DISABLESPANISH

PKT 26RECEIVED

WSSRECEIVED

WSS ON (Reserved)

0

00H

FLICKER STOPON 0 - Enable ‘Flicker Stopper’ circuitry

1 - Disable ‘Flicker Stopper’ circuitry

HUNT 0 - Allow automatic hunting for amplitude of data to be acquired

1 - Disable automatic hunting for amplitude

DISABLE SPANISH 0 - Enable special treatment of Spanish packet 26 characters

1 - Disable special treatment of Spanish packet 26 characters

PKT 26 RECEIVED 0 - No packet 26 data has been processed

1 - Packet 26 data has been processed.

Note: This flag is set by Hardware and must be reset by Software

WSS RECEIVED 0 - No Wide Screen Signalling data has been processed

1 - Wide Screen signalling data has been processed

Note: This flag is set by Hardware and must be reset by Software.

WSS ON 0 - Disable acquisition of WSS data.

1 - Enable acquisition of WSS data.

TXT9 C9H CURSORFREEZE

CLEARMEMORY

A0 R<4> R<3> R<2> R<1> R<0> 00H

CURSOR FREEZE 0 - Use current TXT9 and TXT10 values for cursor position.

1 - Lock cursor at current position

CLEAR MEMORY 0 - Clear memory action is finished

1 - Clear memory block pointed to by TXT15

Note: This flag is set by Software and reset by Hardware

A0 0 - Access memory block pointed to by TXT15

1 - Access extension packet memory

R<4:0> Current memory ROW value.

Note: Valid range TXT mode 0 to 24, CC mode 0 to 15

TXT10 CAH CHAR

16/12

- C<5> C<4> C<3> C<2> C<1> C<0> 00H

CHAR A 16/12 Character Matrix width on Display Page A and B

0 - 12 pixel width

1 - 16 pixel width

C<5:0> Current memory COLUMN value.

Note: Valid range TXT mode 0 to 39, CC mode 0 to 47

TXT11 CBH D<7> D<6> D<5> D<4> D<3> D<2> D<1> D<0> 00H

D<7:0> Data value written or read from memory location defined by TXT9, TXT10 and TXT15

TXT12 CCH 625/525 SYNC ROM VER<4> ROM VER<3> ROM VER<2> ROM VER<1> ROM VER<0> 1 VIDEOSIGNAL

QUALITY

xxxxxx1xB

625/525 SYNC 0 - 625 line CVBS signal is being received

1 - 525 line CVBS signal is being received

ROM VER<4> Mask programmable identification for character set

ROM Version <4>:

0 - Spanish Flicker Stopper Disabled.

1 - Spanish Flicker Stopper Enabled (Controlled by TXT8 Bit-6).

ROM VER<3:0> General purpose register, bits defined by mask programmable bits

1 Reserved

VIDEO SIGNALQUALITY

0 - Acquisition can not be synchronised to CVBS input.

1 - Acquisition can be synchronised to CVBS


2003 Nov 11 48



CONFIDENTIAL

TXT13 F8H VPSRECEIVED

PAGECLEARING

525 DISPLAY 525 TEXT 625 TEXT PKT 8/30 FASTEXT 0 xxxxxxx0B

VPS RECEIVED 0 - VPS data not being received

1 - VPS data being received

PAGE CLEARING 0 - No page clearing active

1 - Software or Power On page clear in progress

525 DISPLAY 0 - 625 Line synchronisation for Display

1 - 525 Line synchronisation for Display

525 TEXT 0 - 525 Line WST not being received

1 - 525 line WST being received

625 TEXT 0 - 625 Line WST not being received

1 - 625 line WST being received

PKT 8/30 0 - No Packet 8/30/x(625) or Packet 4/30/x(525) data detected

1 - Packet 8/30/x(625) or Packet 4/30/x(525) data detected

FASTEXT 0 - No Packet x/27 data detected

1 - Packet x/27 data detected

0 Reserved

TXT14 CDH DISPLAYBANK<3>

DISPLAYBANK<2>

DISPLAYBANK<1>

DISPLAYBANK<0>

PAGE<3> PAGE<2> PAGE<1> PAGE<0> 00H

DISPLAY

BANK <3:0>

0000 - Select Page 0 ~ 9 for Display

0001 - Reserved

0010 - Reserved

0011 - Reserved

0100 - Reserved

0101 - Reserved

0110 - Reserved

0111 - Reserved

1000 - Reserved

1001 - Reserved

1010 - Reserved

1011 - Reserved

1100 - Reserved

1101 - Reserved

1110 - Reserved

1111 - Reserved

PAGE<3:0> Current Display page

TXT15 CEH MICROBANK<3>

MICROBANK<2>

MICROBANK<1>

MICROBANK<0>

BLOCK<3> BLOCK<2> BLOCK<1> BLOCK<0> 00H

MICRO

BANK<3:0>

0000 - Select BLOCK 0 ~ 9 for Micro

0001 - Reserved

0010 - Reserved

0011 - Reserved

0100 - Reserved

0101 - Reserved

0110 - Reserved

0111 - Reserved

1000 - Reserved

1001 - Reserved

1010 - Reserved

1011 - Reserved

1100 - Reserved

1101 - Reserved

1110 - Reserved

1111 - Reserved

BLOCK<3:0> Current Micro block to be accessed by TXT9, TXT10 and TXT11

TXT17 B9H 0 FORCEACQ<1>

FORCEACQ<0>

FORCEDISP<1>

FORCEDISP<0>

SCREENCOL2

SCREENCOL1

SCREENCOL0

00H


2003 Nov 11 49



CONFIDENTIAL

FORCE ACQ<1:0> 00 - Automatic Selection

01 - Force 525 timing, Force 525 Teletext Standard



FORCE DISP<1:0> 00 - Automatic Selection

01 - Force Display to 525 mode (9 lines per row)

10 - Force Display to 625 mode (10 lines per row)

11 - Not Valid (default to 625)

SCREEN COL<2:0> Defines colour to be displayed instead of TV picture and black background. The bits <2:0> are equivalent to the RGB components

000 - Transparent

001 - CLUT entry 9

010 - CLUT entry 10

011- CLUT entry 11

100 - CLUT entry 12

101 - CLUT entry 13

110- CLUT entry 14

111 - CLUT entry 15

TXT18 B2H NOT<3> NOT<2> NOT<1> NOT<0> 0 field_indent BS<1> BS<0> 00H

NOT<3:0> National Option table selection, maximum of 32 when used with East/West bit

field_indent unused, must keep reset value -> ‘0’

BS<1:0> Basic Character set selection

TXT19 B3H TEN TC<2> TC<1> TC<0> 0 0 TS<1> TS<0> 00H

TEN 0 - Disable Twist function

1- Enable Twist character set

TC<2:0> Language control bits (C12/C13/C14) that has Twisted character set

TS<1:0> Twist Character set selection

TXT20 B4H DRCSENABLE

OSD PLANES EXTENDEDSPECIAL

GRAPHICS

CHARSELECTENABLE

OSD LANGENABLE

OSD LAN<2> OSD LAN<1> OSD LAN<0> 00H

DRCS ENABLE 0 - Normal OSD characters used

1 - Re-map column 9 to DRCS (TXT and CC modes),

OSD PLANES 0 - Character code columns 8 and 9 defined as single plane characters

1- Character code columns 8 and 9 defined as double plane characters

EXTENDED SPECIALGRAPHICS

0 - Extended Special Graphics disabled (columns 8 & 9 only used for special graphics characters)

1 - Extended Special Graphics enabled (user definable range for special graphics characters)

CHAR SELECT ENABLE 0 - Disables character set selection in CC display mode

1 - Enables character set selection in CC display mode

OSD LANG ENABLE Enable use of OSD LAN<2:0> to define language option for display, instead of C12/C13/C14

OSD LAN<2:0> Alternative C12/C13/C14 bits for use with OSD menus

TXT21 B5H DISPLINES<1>

DISPLINES<0>

CHARSIZE<1>

CHARSIZE<0>

Reserved 0) CC ON I2C PORT EN CC/TXT 02H

DISP LINES<1:0> The number of display lines per character row.

00 - 10 lines per character (defaults to 9 lines in 525 mode)

01 - 13 lines per character



CHAR SIZE<1:0> Character matrix size.

01 - 13 lines per character (matrix 12x13)




2003 Nov 11 50



CONFIDENTIAL

CCON 0 - Closed Caption acquisition off

1 - Closed Caption acquisition on

I2C PORT EN 0 - Disable I2C PORT EN

1 - Enable I2C PORT EN selection (P1.7/SDA0, P1.6/SCL0)

CC/TXT 0 - Display configured for TXT mode

1 - Display configured for CC mode

TXT22 B6H GPF<7> GPF<6> GPF<5> GPF<4> GPF<3> GPF<2> GPF<1> GPF<0> XXH

GPF<7:0> General purpose register, bits defined by mask programmable bits

TXT23 A9H NOT B<3> NOT B<2> NOT B<1> NOT B<0> EAST/WEST

B

DRCS BENABLE

BS B<1> BS B<0> 00H

NOT B<3:0> National Option table selection for Page B, maximum of 32 when used with East/West bit

EAST/WEST B 0 - Western language selection of character codes A0 to FF on Page B

1 - Eastern language selection of character codes A0 to FF on Page B

DRCS B ENABLE 0 - Normal OSD characters used on Page B

1 - Re-map column 8/9 to DRCS (TXT and CC modes) on Page B

BS B<1:0> Basic Character set selection for Page B

TXT24 AAH BKGND OUTB

BKGND IN B COR OUT B COR IN B TEXT OUT B TEXT IN B PICTURE ONOUT B

PICTURE ONIN B

03H

BKGND OUT B 0 - Background colour not displayed outside teletext boxes (Teletext page)

1 - Background colour displayed outside teletext boxes (Teletext page)

BKGND IN B 0 - Background colour not displayed inside teletext boxes (Teletext page)

1 - Background colour displayed inside teletext boxes (Teletext page)

COR OUT B 0 - COR not active outside teletext and OSD boxes (Teletext page)

1 - COR active outside teletext and OSD boxes (Teletext page)

COR IN B 0 - COR not active inside teletext and OSD boxes (Teletext page)

1 - COR active inside teletext and OSD boxes (Teletext page)

TEXT OUT B 0 - TEXT not displayed outside teletext boxes (Teletext page)

1 - TEXT displayed outside teletext boxes (Teletext page)

TEXT IN B 0 - TEXT not displayed inside teletext boxes (Teletext page)

1 - TEXT displayed inside teletext boxes (Teletext page)

PICTURE ON OUT B 0 - VIDEO not displayed outside teletext boxes (Teletext page)

1 - VIDEO displayed outside teletext boxes (Teletext page)

PICTURE ON

IN B

0 - VIDEO not displayed inside teletext boxes (Teletext page)

1 - VIDEO displayed inside teletext boxes (Teletext page)

TXT25 ABH BKGND OUTB

BKGND IN B COR OUT B COR IN B TEXT OUT B TEXT IN B PICTURE ONOUT B

PICTURE ONIN B

03H

BKGND OUT B 0 - Background colour not displayed outside teletext boxes (Sub-Title / Newsflash page)

1 - Background colour displayed outside teletext boxes (Sub-Title / Newsflash page)

BKGND IN B 0 - Background colour not displayed inside teletext boxes (Sub-Title / Newsflash page)

1 - Background colour displayed inside teletext boxes (Sub-Title / Newsflash page)

COR OUT B 0 - COR not active outside teletext and OSD boxes (Sub-Title / Newsflash page)

1 - COR active outside teletext and OSD boxes (Sub-Title / Newsflash page)

COR IN B 0 - COR not active inside teletext and OSD boxes (Sub-Title / Newsflash page)

1 - COR active inside teletext and OSD boxes (Sub-Title / Newsflash page)

TEXT OUT B 0 - TEXT not displayed outside teletext boxes (Sub-Title / Newsflash page)

1 - TEXT displayed outside teletext boxes (Sub-Title / Newsflash page)


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CONFIDENTIAL

TEXT IN B 0 - TEXT not displayed inside teletext boxes (Sub-Title / Newsflash page)

1 - TEXT displayed inside teletext boxes (Sub-Title / Newsflash page)

PICTURE ON OUT B 0 - VIDEO not displayed outside teletext boxes (Sub-Title / Newsflash page)

1 - VIDEO displayed outside teletext boxes (Sub-Title / Newsflash page)

PICTURE ON IN B 0 - VIDEO not displayed inside teletext boxes (Sub-Title / Newsflash page)

1 - VIDEO displayed inside teletext boxes (Sub-Title / Newsflash page)

TXT26 ACH EXTENDEDDRCS

TRANS B 0 0 SHADOWENABLE B

BOX ON 24 B BOX ON 1-23B

BOX ON 0 B 03H

EXTENDED DRCS 0 - Columns 8/9 mapped to DRCS when DRCS characters enabled (32 DRCS characters)

1 - Columns 8/9/A/C mapped to DRCS when DRCS characters enabled (64 DRCS characters)

TRANS ENABLE B 0 - Display black background as normal on Page B

1 - Display black background as video on Page B

SHADOW ENABLE B 0 - Disable display of shadow/fringing on Page B

1 - Display shadow/ fringe (default SE black) on Page B

BOX ON 24 B 0 - Disable display of teletext boxes in memory row 24 of Page B

1 - Enable display of teletext boxes in memory row 24 of Page B

BOX ON 1-23 B 0 - Disable display of teletext boxes in memory row 1 to 23 of Page B

1 - Enable display of teletext boxes in memory row 1 to 23 of Page B

BOX ON 0 B 0 - Disable display of teletext boxes in memory row 0 of Page B

1 - Enable display of teletext boxes in memory row 0 of Page B

TXT27 B1H - - - - RDS ON SCR B<2> SCR B<1> SCR B<0> 00H

RDS ON 0 - RDS/RBDS disable

1 - RDS/RBDS enable

SCR B<2:0> Defines colour to be displayed instead of TV picture and black background for Page B. The bits <2:0> are equivalent to the RGB components

000 - Transparent

001 - CLUT entry 9

010 - CLUT entry 10

011 - CLUT entry 11

100 - CLUT entry 12

101 - CLUT entry 13

110 - CLUT entry 14

111 - CLUT entry 15

TXT28 ADH DISPLAYBANK B<3>

DISPLAYBANK B<2>

DISPLAYBANK B<1>

DISPLAYBANK B<0>

PAGE B<3> PAGE B<2> PAGE B<1> PAGE B<0> 00H

DISPLAY BANK

B<3:0>

0000 - Select Page 0 ~ 9 for Display Page B

0001 - Reserved

0010 - Reserved

0011 - Reserved

0100 - Reserved

0101 - Reserved

0110 - Reserved

0111 - Reserved

1000 - Reserved

1001 - Reserved

1010 - Reserved

1011 - Reserved

1100 - Reserved

1101 - Reserved

1110 - Reserved

1111 - Reserved

PAGE B<3:0> Current Display page for Page B

TXT29 E1H TEN B TS B <1> TS B <0> OSD PLANESB

OSD LANGENABLE B

OSD LAN B<2>

OSD LAN B<1>

OSD LAN B<0>

00H


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CONFIDENTIAL

TEN B 0 - Disable Twist function for Page B

1 - Enable Twist character set for Page B

TS B<1:0> Twist Character set selection for Page B

OSD PLANES B 0 - Character code columns 8 and 9 defined as single plane characters for Display Page B

1 - Character code columns 8 and 9 defined as double plane characters (special graphics characters) for Display Page B

OSD LANG ENABLE B Enable use of OSD LAN<2:0> to define language option for display, instead of C12/C13/C14 for Display Page B

OSD LAN B <2:0> Alternative C12/C13/C14 bits for use with OSD menus for Display Page B

TXT30 E2H TC B <2> TC B <1> TC B <0> BOTTOM/TOP B

DOUBLEHEIGHT

B

STATUS ROWTOP B

DISPLAY X24B

DISPLAYSTATUSROW

ONLY B

00H

TC B<2:0> Language control bits (C12/C13/C14) that has Twisted character set for Page B

BOTTOM/TOP

B

0 - Display memory rows 0 to 11 when double height bit is set on Display Page B

1 - Display memory rows 12 to 23 when double height bit is set on Display Page B

DOUBLE HEIGHT B 0 - Display each characters with normal height on Display Page B

1 - Display each character as twice normal height on Display Page B

STATUS ROW TOP B 0 - Display memory row 24 information below teletext page (on display row 24) on Display Page B

1 - Display memory row 24 information above teletext page (on display row 0) on Display Page B

DISLAY X24 B 0 - Display row 24 from basic page memory on Display Page B

1 - Display row 24 from appropriate location in extension memory on Display Page B

DISPLAY STATUS ROWONLY B

0 - Display normal page rows 0 to 24 on Display Page B

1 - Display only row 24 on Display Page B

TXT31 A1H 0 CC_TXT B ACTIVEPAGE

1V8GUARD GPF<11> GPF<10> GPF<9> GPF<8> 0XH

CC/TXT B 0 - Display Page B configured for TXT mode

1 - Display Page B configured for CC mode

ACTIVE PAGE 0 - Display Page A active during two page mode

1 - Display Page B active during two page mode

1V8GUARD 0 - 1.8V supply is normal

1 - 1.8Vsupply is abnormal (1.44V)

GPF<11:8> General purpose register, bits defined by mask programmable bits

TXT32 A2H GPF<11> 9FF<11> 9FF<10> 9FF<9> 9FF<8> 9FF<7> 9FF<6> 9FF<5> XXH

GPF<11>,9FF<11:5> General purpose register, bits defined by mask programmable bits

TXT33 A3H BFE<7> BFE<6> BFE<5> BFE<4> BFE<3> BFE<2> BFE<1> BFE<0> XXH

BFE<7:0> General purpose register, bits defined by mask programmable bits

TXT34 A4H BFE<15> BFE<14> BFE<13> BFE<12> BFE<11> BFE<10> BFE<9> BFE<8> XXH

BFE<15:8> General purpose register, bits defined by mask programmable bits

TXT35 F7H 9FF<15> 9FF<14> 9FF<13> 9FF<12> GPF<15> GPF<14> GPF<13> GPF<12> XXH

9FF<15:12>, GPF<15:12> General purpose register, bits defined by mask programmable bits

TXT36 FCH - - - BFF<4> BFF<3> BFF<2> BFF<1> BFF<0> XXH

BFF<4:0> General purpose register, bits defined by mask programmable bits

Video_process A5H - - - - - - DW_PA<1> DW_PA<0> 00H


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CONFIDENTIAL

DW_PA<1:0> Double Window and Panorama feature selection:-00- normal mode (both Double Window and Panorama are disable)01 - Double Window mode enable; the others are disable10 - Linear scaling mode enable, the others are disable11 - non-Linear scaling mode enable, the others are disable

WDT FFH WDV<7> WDV<6> WDV<5> WDV<4> WDV<3> WDV<2> WDV<1> WDV<0> 00H

WDV<7:0> Watch Dog Timer period

WDTKEY FEH WKEY<7> WKEY<6> WKEY<5> WKEY<4> WKEY<3> WKEY<2> WKEY<1> WKEY<0> 00H

WKEY<7:0> Watch Dog Timer Key

Note: Must be set to 55H to disable Watch dog timer when active

WSS1 BAH 0 0 0 WSS<3:0>ERROR

WSS<3> WSS<2> WSS<1> WSS<0> 00H

WSS<3:0> ERROR 0 - No error in WSS<3:0>

1 - Error in WSS<3:0>

WSS<3:0> Signalling bits to define aspect ratio (group 1)

WSS2 BBH 0 0 0 WSS<7:4>ERROR

WSS<7> WSS<6> WSS<5> WSS<4> 00H

WSS<7:4> ERROR 0 - No errors in WSS<7:4>


WSS<7:4> Signalling bits to define enhanced services (group 2)

WSS3 BCH WSS<13:11>ERROR

WSS<13> WSS<12> WSS<11> WSS<10:8>ERROR

WSS<10> WSS<9> WSS<8> 00H



WSS<13:11> Signalling bits to define reserved elements (group 4)


1 - Error in WS<10:8>

WSS<10:8> Signalling bits to define subtitles (group 3)

XRAMP FAH XRAMP<7> XRAMP<6> XRAMP<5> XRAMP<4> XRAMP<3> XRAMP<2> XRAMP<1> XRAMP<0> 00H

XRAMP<7:0> Internal RAM access upper byte address


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CONFIDENTIAL

External (MOVX) MemoryThe normal 80C51 external memory area has beenmapped internally to the device, this means that the MOVXinstruction accesses data memory internal to the device.The movx memory map is shown in Fig.13.

Auxiliary RAM Page SelectionThe Auxiliary RAM page pointer is used to select one ofthe 256 pages within the auxiliary RAM, not all pages areallocated, refer to Fig. 14. A page consists of 256consecutive bytes. XRAMP only works on internal MOVXmemory.

Power-on ResetPower on reset is generated internally to the UOCIII

device, hence no external reset circuitry is required.

Software ResetThe UOCIII features a software reset (ROMBK SFR, bit 6),which can be used by the micro-controller to reset thefollowing functions/blocks: stereo sound decoder, RDS,ISP, acquisition, display, display RAM and doublewindow/panorama. The software reset is executed byinitially setting the corresponding bit to ‘1’ followed byclearing the bit to ‘0’. It takes approximately 200 µs tocomplete the internal reset sequence.Please note themicro-controller, its peripherals (e.g. timers) and programflash are not reset.

Power Saving modes of OperationThere are three Power Saving modes, Stand-by, Idle andPower Down, incorporated into the TCG micro-controller(Text/Control/Graphic micro-controller) die. When utilizingeither mode, the 3.3V power to the device (Vddp & Vdda)should be maintained. The analogue blocks arepowered-down and the clocks to various digital blocks aredisabled to minimize the power consumption. The +1.8 Vanalogue supplies can be switched off.The internallygenerated 1.8V will be maintained to supply the power of80c51 and pads.

Stand-by ModeDuring Stand-by mode, the Acquisition, Display, RDS, andSSD sections of the device are disabled. This includesanalog modules, such A/D and D/A converter. Before

Data RAM0000H

0FFFH

7FFFH

8000H

84FFHDisplay RAM

forClosed Caption(1)

8700H

871FHCLUT

87E0H

87FFHDisplay Registers

8800H

90FFH

DynamicallyRe-definableCharacters

Lower 32K bytes Upper 32K bytes

9100H

FFFFH

Fig.13 Movx Address Map

2000H

6FFFH

7000H

Display RAMfor

TEXT PAGES

(1) Display RAM for Closed Caption, Text, RDS/RBDS is shared

74FFH7500H

RDS/RBDS Display Data

(XRAMP)=00H

0000H

00FFH0100H

01FFH

00H

FFH00H

FFH

(XRAMP)=01H

(XRAMP)=FEH

FE00H

FEFFHFF00H

FFFFH

00H

FFH00H

FFH

(XRAMP)=FFH

MOVX @DPTR,AMOVX @Ri, AMOVX A, @Ri

MOVX A,@DPTR

Fig.14 Indirect addressing(Movx address space)

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CONFIDENTIAL

entering standby-mode, the SSD will be allowed tosoft-mute the audio outputs. After the required 32 ms, thevideo processor is powered-down and the followingfunctions remain active:-

• 80c51 CPU Core

• I2C

• RCP (Remote Control Pre-processor)

• Timer/Counters

• WatchDog Timer

• UART, SAD and PWMs

To enter Stand-by mode, the STANDBY bit in theROMBANK register must be set. The contents of theDisplay memory are lost. Since the output values on RGBand VDS are maintained the display output must bedisabled before entering this mode.This mode should be used in conjunction with both Idleand Power-Down modes. Hence, prior to entering eitherIdle or Power-Down, the STANDBY bit should be set.

Idle ModeDuring Idle mode, Acquisition, Display, RDS, SSD and theCPU sections of the device are disabled. The followingfunctions remain active:-

• I2C

• RCP

• Timer/Counters

• WatchDog Timer

• UART, SAD and PWMs

To enter Idle mode the IDL bit in the PCON register mustbe set. The WatchDog timer must be disabled prior toentering Idle to prevent the device being reset. It is adviceto use the RCP (Remote Control Pre-processor) during theIdle mode to reduce the false interrupt wake-up of 80c51 inorder to achieve the low power saving mode. The CPUstate is frozen along with the status of all SFRs, internalRAM contents are maintained, as are the device output pinvalues.

There are three methods available to recover from Idle:-• Assertion of an enabled interrupt will cause the IDL bit to

be cleared by hardware, thus terminating Idle mode.The interrupt is serviced, and following the instructionRETI, the next instruction to be executed will be the oneafter the instruction that put the device into Idle mode.

• A second method of exiting Idle is via an Interruptgenerated by the SAD DC Compare circuit. When TCGmicro-controller is configured in this mode, detection ofan analogue threshold at the input to the SAD may beused to trigger wake-up of the device i.e. TV Front PanelKey-press. As above, the interrupt is serviced, andfollowing the instruction RETI, the next instruction to beexecuted will be the one following the instruction that putthe device into Idle.

• The third method of terminating Idle mode is with aPower On reset. Reset defines all SFRs and Displaymemory to a pre-defined state, but maintains all otherRAM values. Code execution commences with theProgram Counter set to ’0000’.

Power Down ModeIn Power Down mode the XTAL oscillator is still running.The contents of all SFRs and Data memory aremaintained. The port pins maintain the values defined bytheir associated SFRs.The power down mode is activated by setting the PD bit inthe PCON register. It is advised to disable the WatchDogtimer prior to entering Power down. Recovery fromPower-Down takes several milli-seconds as the oscillatormust be given time to stabilize.

There are three methods of exiting power down:-

• An External interrupt provides the first mechanism forwaking from Power-Down. Since the clock is stopped,external interrupts needs to be set level sensitive prior toentering Power-Down. The interrupt is serviced, andfollowing the instruction RETI, the next instruction to beexecuted will be the one after the instruction that put thedevice into Power-Down mode.

• A second method of exiting Power-Down is via anInterrupt generated by the SAD DC Compare circuit.When TCG micro-controller is configured in this mode,detection of a certain analogue threshold at the input tothe SAD may be used to trigger wake-up of the devicei.e. TV Front Panel Key-press. As above, the interrupt isserviced, and following the instruction RETI, the nextinstruction to be executed will be the one following theinstruction that put the device into Power-Down.

• The third method of terminating the Power-Down modeis with a Power On reset. Reset defines all SFRs andDisplay memory, but maintains all other RAM values.Code execution commences with the Program Counterset to ’0000’.

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CONFIDENTIAL

I/O Facility

I/O PORTS

The IC has 24 I/O lines, each is individually addressable,or form part of 4 parallel addressable ports which areport0, port1, port2 and port3.The I/O cells are designed to transfer 3.3V external (Padside) signals to 1.8V internal (core side) signals, viceversa. And the I/O pads for the bond-out as well as GPIOhave 5V tolerant except the I2C clock pad in High-speedmode.

PORT TYPE

All individual ports can be programmed to function in oneof four modes, the mode is defined by two PortConfiguration SFRs. The modes available are Open Drain,Quasi-bidirectional, High Impedance and Push-Pull.

Open DrainThe Open drain mode can be used for bi-directionaloperation of a port. It requires an external pull-up resistor,the pull-up voltage has a maximum value of 5.5V, to allowconnection of the device into a 5V environment.

Quasi bi-directionalThe quasi-bidirectional mode is a combination of opendrain and push pull. It requires an external pull-up resistorto VDDp (nominally 3.3V). When a signal transition from0->1 is output from the device, the pad is put into push-pullmode for one clock cycle (81.38ns) after which the padgoes into open drain mode. This mode is used to speed upthe edges of signal transitions. This is the default mode ofoperation of the pads after reset.

High ImpedanceThe high impedance mode can be used for Input onlyoperation of the port. When using this configuration the twooutput transistors are turned off.

Push-PullThe push pull mode can be used for output only. In thismode the signal is driven to either 0V or VDDp, which isnominally 3.3V.

Interrupt SystemThe device has 12 interrupt sources, each of which can beenabled or disabled. When enabled, each interrupt can beassigned one of two priority levels. There are fourinterrupts that are common to the 80C51, two of these areexternal interrupts (EX0 and EX1) and the other two aretimer interrupts (ET0 and ET1).The TCG micro-controller family of devices have anadditional 24-bit Timer (16-bit timer with 8-bit pre-scaler).

To accommodate this, another interrupt ET2PR has beenadded to indicate timer overflow.In addition to the conventional 80c51, four applicationspecific interrupts are incorporated internally to the devicewhich have the following functionality:-RDS (Radio Data System Interrupt) - This interrupt isgenerated when the RDS/RBDS is decoded and available.The interrupt is activated when DAVN (data available) isactive which is generated by RDS/RBDS subblock.DET (Supply Dip Monitor Interrupt) - This interrupt isgenerated when the supply dip monitor detects at dip of1.44V on one of the 1.8V supply pins.CC (Closed Caption Data Ready Interrupt) - Thisinterrupt is generated when the device is configured forClosed Caption acquisition. The interrupt is activated atthe end of the currently selected Slice Line as defined inthe CCLIN SFR.BUSY (Display Busy Interrupt) - An interrupt isgenerated when the Display enters either a Horizontal orVertical Blanking Period. i.e. Indicates when themicro-controller can update the Display RAM withoutcausing undesired effects on the screen. This interrupt canbe configured in one of two modes using the MMRConfiguration Register (Address 87FF, Bit-3 [TXT/V]):-• TeXT Display Busy: An interrupt is generated on each

active horizontal display line when the HorizontalBlanking Period is entered.

• Vertical Display Busy: An interrupt is generated on eachvertical display field when the Vertical Blanking Period isentered.

There are two interrupts connected to the 80c51micro-controller peripherals as follows: -

ES2 - I2C Transmit/Receive interrupt.EUART - UART Receive/Transmit interrupt.

One additional general purpose external interrupt (EX2) isincorporated into TCG micro-controller and is onlyavailable in QFP128 package.

INTERRUPT ENABLE STRUCTURE

Each of the individual interrupts can be enabled ordisabled by setting or clearing the relevant bit in theinterrupt enable SFRs (IE and IEN1). All interrupt sourcescan also be globally disabled by clearing the EA bit (IE.7).The EDET interrupt can only be cleared by setting thecorresponding status bits in bit 4 and 7 of TXT31 or bit4and 5 of ROMBK to ’0’.

2003 Nov 11 57



CONFIDENTIAL

INTERRUPT ENABLE PRIORITY

Each interrupt source can be assigned one of two prioritylevels (High/Low). The interrupt priorities are defined bythe interrupt priority SFRs (IP and IP1). A low priorityinterrupt can be interrupted by a high priority interrupt, butnot by another low priority interrupt. A high priority interruptcan not be interrupted by any other interrupt source. If tworequests of different priority level are receivedsimultaneously, the request with the highest priority level isserviced. If requests of the same priority level are receivedsimultaneously, an internal polling sequence determineswhich request is serviced. Thus, within each priority levelthere is a second priority structure determined by thepolling sequence as defined in Table 7.

INTERRUPT VECTOR ADDRESS

The processor acknowledges an interrupt request byexecuting a hardware generated LCALL to the appropriateservicing routine. The interrupt vector addresses areshown in Table 7.

LEVEL/EDGE INTERRUPT

The external interrupt (EX0 and EX1) can be programmedto be either level-activated or transition activated by settingor clearing the IT0/1 bits in the Timer Control SFR(TCON).

Timer/CounterTwo 16 bit timers/counters are incorporated Timer0 andTimer1. Both can be configured to operate as either timersor event counters.In Timer mode, the register is incremented on everymachine cycle. It is therefore counting machine cycles.Since the machine cycle consists of 6 oscillator periods,the count rate is 1/6 micro-controller clock(12.288MHz) =2.048MHz.In Counter mode, the register is incremented in responseto a negative transition at its corresponding external pinT0/1. Since the pins T0/1 are sampled once per machinecycle it takes two machine cycles to recognise a transition,this gives a maximum count rate of 1/12 micro-controllerclock(12.288MHz)= 1.024MHz.There are six special function registers used to control thetimers/counters as defined in Table 9.

Source Priority within level Trigger Condition Interrupt Vector

EX0 Highest low-level or falling-edge 0003H

ET0 Timer0 000BH

EX1 low-level or falling-edge 0013H

ET1 Timer1 001BH

EDET 1v8guard 0023H

ECC high-level 002BH

ES2 low-level 0033H

Table 7 Interrupt Priority (within same level)

EX0

ET0

EX1

ET1

ECC

ES2

EBUSY

H1

H2

H3

H4

H5

H6

H7

L1

L2

L3

L4

L5

L6

L7

Highest Priority Level1

Highest Priority Level0

EDET

Lowest Priority Level1

Lowest Priority Level0

SourceEnable

GlobalEnable

PriorityControl

InterruptSource

H8

L8

Fig.15 Interrupt Structure

ET2PRH9

L9

EUARTH10

L10

ERDSH11

L11

EX2H12

L12

IE.0:6IEN1.0:4

IE.7 IP.0:6IP1.0:4

EBUSY falling-edge 003BH

ET2PR Timer2 0043H

EUART UART 004BH

ERDS falling-edge 0053H

EX2 Lowest low-level 005BH

ITx Interrupt Type

0 Level, Active Low

1 Edge, Negative Edge

Table 8 External Interrupt Activation

SFR Address

TCON 88H

TMOD 89H

TL0 8AH

TH0 8BH

Table 9 Timer/Counter Registers

Source Priority within level Trigger Condition Interrupt Vector

Table 7 Interrupt Priority (within same level)

2003 Nov 11 58



CONFIDENTIAL

The Timer/Counter function is selected by control bits C/Tin the Timer Mode SFR (TMOD). These twoTimer/Counter have four operating modes, which areselected by bit-pairs (M1.M0) in the TMOD. Refer to the

80C51 based 8-bit micro-controllers - PhilipsSemiconductors (ref. IC20) for detail of the modes andoperation.TL0/TL1 and TH0/TH1 are the actual timer/counterregisters for timer0 / timer1. TL0/TL1 is the low byte andTH0/TH1 is the high byte.

TIMER2 WITH PRE-SCALER

An additional 24-bit Timer (16-bit timer with 8-bitpre-scaler) is provided to allow timer periods up to 8.192seconds. This timer remains active during IDLE mode.TP2L sets the lower value of the period for timer 2 andTP2H is the upper timer value. TP2PR provides an 8-bitpre-scaler for timer 2. The value on TP2PR, TP2H andTP2L shall never change unless updated by the software.If the micro reads TP2R, TP2H orTP2L at any stage, thisshould return the value written and not the current timer 2value. The timer 2 should continue after overflow byre-loading (hardware) the timer with the values of SFRsTP2PR, TP2H and TP2L.TP2CL and TP2CH indicate the current timer 2 value.These should be readable both when the timer 2 is activeand inactive. Once the timer 2 is disable, the timer 2 valueat the time of disabling should be maintained on the SFRsTP2CL and TP2CH. At a count of zero (on TP2CL andTP2CH), the overflow flag should be set:- TP2CRL<1> - ’0’= no timer 2 overflow, ’1’= timer 2 overflow.TP2CRL is the control and status for timer 2. TP2CRL.0 isthe timer enable and TP2CRL.1 is the timer overflowstatus. The overflow flag will need to be reset by software.Hence, if required, software may poll flag rather than useinterrupt. Upon overflow an interrupt should also begenerated.Reset values of all registers should be 00 hex.Timer2 interval = (TP2H * 256 + TP2L) * (TP2PR + 1) * 0.4883us

WatchDog TimerThe WatchDog timer is a counter that once in an overflowstate forces the micro-controller in to a reset condition. Thepurpose of the WatchDog timer is to reset themicro-controller if it enters an erroneous processor state(possibly caused by electrical noise or RFI) within areasonable period of time. When enabled, the WatchDogcircuitry will generate a system reset if the user programfails to reload the WatchDog timer within a specified lengthof time known as the WatchDog interval.The WatchDog timer consists of an 8-bit counter with an16-bit pre-scaler. The pre-scaler is fed with a signal whosefrequency is 1/6 * 12.288MHz = 2.048MHz. The 8 bit timeris incremented every ‘t’ seconds where:t=6x65536x1/12.288x106 = 32ms

TL1 8CH

TH1 8DH

SFR Address

Table 9 Timer/Counter Registers

TF1 TR TF0 TR IE1 IT1 IE0 IT0Symbol Position Name and Significance

TF1 TCON.7 Timer 1 overflow flag. Set by hard-ware on timer/counter overflow.Cleared by hardware when processorvectors to interrupt routine.

TR1 TCON.6 Timer 1 Run control bit. Set/clearedby software to turn timer.counteron/off.

TF0 TCON.5 Timer 0 overflow flag. Set by hard-ware on timer/counter overflow.Cleared by hardware when processorvectors to interrupt routine.

TR0 TCON.4 Timer 0 Run control bit. Set/clearedby software to turn timer.counteron/off.

Symbol Position Name and Significance

IE1 TCON.3 Interrupt 1 Edge flag. Set by hardwarewhen external interrupt edgedetected. Cleared when interruptprocessed.

IT1 TCON.2 Interrupt 1 Type control bit.Set/cleared by software to specify fall-ing edge/low level triggered externalinterrupts.

IE0 TCON.1 Interrupt 0 Edge flag. Set by hardwarewhen external interrupt edgedetected. Cleared when interruptprocessed.

IT0 TCON.0 Interrupt 0 Type control bit.Set/cleared by software to specify fall-ing edge/low level triggered externalinterrupts.

Fig.16 Timer/Counter Control (TCON) register

Gat C/T M1 M0 Gat C/T M1 M0

Timer 1 Timer 0

Gate Gating control when set. Timer/counter is enabled onlywhile external interrupt 0/1 is high and TR control bit isset. When cleared timer/counter is enabled whenever TRcontrol bit is set.

C/T Timer or Counter selector. Cleared for timer operation(input from system clock). Set for counter operation (inputfrom T input pin.

M1 M0 Operating

0 0 8048 Timer, TL serves as 5-bit prescaler.0 1 16-bit Timer/Counter, TL and TH are cascaded.1 0 8-bit auto-reload Timer/Counter, TH holds a value

which is to be loaded into TL.1 1 timer 0: two 8-bit Timers/Counters. TL0 is controlled by

timer 0 control bits. TH0 is controlled by timer 1 controlbits. timer 1: stopped.

Fig.17 Timer/Counter Mode control (TMOD)

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CONFIDENTIAL

WATCHDOG TIMER OPERATION

The WatchDog operation is activated when the WLE bit inthe Power Control SFR (PCON) is set. The WatchDog canbe disabled by Software by loading the value 55H into theWatchDog Key SFR (WDTKEY). This must be performedbefore entering Idle/Power Down mode to prevent exitingthe mode prematurely.Once activated the WatchDog timer SFR (WDT) must bereloaded before the timer overflows. The WLE bit must beset to enable loading of the WDT SFR, once loaded theWLE bit is reset by hardware, this is to prevent erroneousSoftware from loading the WDT SFR.The value loaded into the WDT defines the WatchDoginterval.

WatchDog interval = (256 - WDT) * t = (256 -WDT) * 32ms.

The range of intervals is from WDT=00H which gives8.192s to WDT=FFH which gives 32ms.

PORT Alternate FunctionsThe Ports 0, 1,2 and 3 are shared with alternate functionsto enable control of external devices and circuitry. Thealternate functions are enabled by setting the appropriateSFR and also writing a ‘1’ to the Port bit that the functionoccupies.

PWM PULSE WIDTH MODULATORS

The device has five 6-bit Pulse Width Modulated (PWM)outputs for analogue control. The PWM outputs generatepulse patterns with a repetition rate of 10.4166us, with thehigh time equal to the PWM SFR value multiplied by0.1628us. The analogue value is determined by the ratioof the high time to the repetition time, a D.C. voltageproportional to the PWM setting is obtained by means ofan external integration network (low pass filter).

PWM ControlThe relevant PWM is enabled by setting the PWM enablebit PWxE in the PWMx Control register. The high time isdefined by the value PWxV<5:0>

TPWM TUNING PULSE WIDTH MODULATOR

The device has a single 14-bit PWM that can be used forVoltage Synthesis Tuning. The method of operation issimilar to the normal PWM except the repetition period is20.833us.

TPWM ControlTwo SFRs are used to control the TPWM, they are TDACLand TDACH. The TPWM is enabled by setting the TPWEbit in the TDACH SFR. The most significant bits TD<13:7>alter the high period between 0 and 20.833us. The 7 leastsignificant bits TD<6:0> extend certain pulses by a further

0.1628us. e.g. if TD<6:0> = 01H then 1 in 128 periods willbe extended by 0.1628us, if TD<6:0>=02H then 2 in 128periods will be extended.The TPWM will not start to output a new value until TDACHhas been written to. Therefore, if the value is to bechanged, TDACL should be written before TDACH.

SAD SOFTWARE A/DFour successive approximation Analogue to DigitalConverters can be implemented in software by making useof the on board 8-bit Digital to Analogue Converter andAnalogue Comparator.

SAD ControlThe control of the required analogue input is done usingthe channel select bits CH<1:0> in the SAD SFR, thisselects the required analogue input to be passed to one ofthe inputs of the comparator. The second comparator inputis generated by the DAC whose value is set by the bitsSAD<7:0> in the SAD and SADB SFRs. A comparisonbetween the two inputs is made when the start compare bitST in the SAD SFR is set, this must be at least oneinstruction cycle after the SAD<7:0> value has been set.The result of the comparison is given on VHI oneinstruction cycle after the setting of ST.

SAD Input VoltageThe external analogue voltage that is used for comparisonwith the internally generated DAC voltage does not havethe same voltage range. The DAC has a lower referencelevel of VSSA and an upper reference level of VDDA. Theresolution of the DAC voltage with a nominal value is3.3/256 ~= 13mV. The external analogue voltage has alower value equivalent to VSSA and an upper valueequivalent to VDDP - Vtn, were Vtn is the threshold voltagefor an NMOS transistor. The reason for this is that the input

+

-

VHI

MUX

4-1

8-bitDAC

SAD<7:0>

ADC0

ADC1

ADC2

ADC3

CH<1:0>

VDDP

Fig.18 SAD Block Diagram

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pins for the analogue signals (P3.0 to P3.3) are 5V tolerantfor normal port operations, i.e. when not used as analogueinput. To protect the analogue multiplexer and comparatorcircuitry from the 5V, a series transistor is used to limit thevoltage. This limiting introduces a voltage drop equivalentto Vtn (~0.6V) on the input voltage. Therefore, for an inputvoltage in the range VDDp to VDDp-Vtn the SAD returns thesame comparison value.

SAD DC Comparator ModeThe SAD module incorporates a DC Comparator modewhich is selected using the ’DC_COMP’ control bit in theSADB SFR. This mode enables the micro-controller todetect a threshold crossing at the input to the selectedanalogue input pin (P3.0, P3.1, P3.2 or P3.3) of theSoftware A/D Converter. A level sensitive interrupt isgenerated when the analogue input voltage level at the pinfalls below the analogue output level of the SAD D/Aconverter.This mode is intended to provide the device with awake-up mechanism from Power-Down or Idle when akey-press on the front panel of the TV is detected.The following software sequence should be used whenutilizing this mode for Power-Down or Idle:-1. Disable INT1 using the IE SFR.

2. Set INT1 to level sensitive using the TCON SFR.

3. Set the D/A Converter digital input level to the desiredthreshold level using the SAD/SADB SFRs and selectthe required input pin (P3.0, P3.1, P3.2 or P3,3) usingCH1, CH0 in the SAD SFR.

4. Enter DC Compare mode by setting the ’DC_COMP’enable bit in the SADB SFR.

5. Enable INT1 using the IE SFR.

6. Enter Power-Down/Idle. Upon wake-up the SADshould be restored to its conventional operating modeby disabling the ’DC_COMP’ control bit.

I2C Serial I/O BusThe I2C bus consists of a serial data line (SDA) and a serialclock line (SCL). The definition of the I2C protocol can befound in The I2C-bus Specification v2.1, January 2000,Philips Semiconductor.The device operates in four modes: -• Master Transmitter

• Master Receiver

• Slave Transmitter

• Slave Receiver

Each of the 4 modes above can operate at the next speedmodes:• Hs-mode (High speed: 128kHz~2.048MHz) or

• F/S-mode (Fast/Standard: 12kHz~384kHz)

Hs-mode can operate up to 2.048 Mbit/s.Fast-mode can operate up to 384kbit/s, which also coversStandard-mode (up to 100kHz).The SCLH-out (Serial CLock line/signal in Hs-modesystem) frequency in Hs-mode is specified in SFR,HSBIR<4:0>, and in F/S-mode is specified in SFR,FSBIR<6:0>.The micro-controller peripheral is controlled by the SerialControl SFR (S1CON) and its Status is indicated by thestatus SFR (S1STA). Information is transmitted/receivedto/from the I2C bus using the Data SFR (S1DAT) and theSlave Address SFR (S1ADR) is used to configure theslave address of the peripheral.

Hs-modeThe various serial rates are shown below: -

Table 10 I2C Serial Rates ‘Hs-mode’

Reload-value inHSBIR<4:0>

MOD_CLK divided by MOD_CLK=12.288MHz

0 3 not allowed

1 6 2.048MHz

2 9 1.365MHz

3 12 1.024MHz

4 15 0.819MHz

5 18 0.6875MHz

6 21 0.585MHz

7 24 0.512MHz

| | |

| | |

31 96 0.128MHz

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F/S mode

Table 11 I2C Serial Rates ‘F/S mode’1

1. F/S-SCL frequencies between 0 and 100 kHz are allowed if the F/S bit in FSBIR is’0’ (Standard mode); F/S-SCL frequencies between 0 and 400kHz are allowed if theF/S-bit in FSBIR is ’1’ (Fast mode).

I2C Port EnableOne external I2C port is available. This port is enabledusing TXT21.I2C PORT EN. Any information transmitted tothe device can only be acted upon if the port is enabled.Internal communication between the 80c51micro-controller and the TV Signal Processor will continueregardless of the value written to TXT21.I2C PORT EN.

I2S Port EnableFive external I2S port are available. Each port is enabledusing I2S.EN_I2SDI1, I2S.EN_I2SDO1, I2S.EN_I2SDO2,I2S.EN_I2SCLK, and I2S.EN_I2SWS. Any informationtransmitted/received to/from the device can only beactivated upon if the port is enabled.

UART Peripheral

The 80c51 Micro-controller incorporates a full duplexUART with a single byte receive buffer, meaning that itcommence reception of a second byte before the first isread form the receive buffer. The UART’s RX and TX pinsconnect to P1.4 & P1.5 respectively.Two registers (S0CON, S0BUF) control the UART alongwith SMOD bit of PCON register: -

S0CONThe serial port control and status register is the SpecialFunction Register S0CON. This register contains not onlythe mode selection bits, but also the 9th data bit fortransmit and receive (TB8 and RB8), and the serial portinterrupt bits (TI and RI).

Reload-value inFSBIR<6:0>

MOD_CLK divided by MOD_CLK=12.288MHz

0 8 not allowed

1 16 not allowed

2 24 not allowed

3 32 384kHz

4 40 307kHz

5 48 256kHz

6 56 219kHz

7 64 192kHz

8 72 170.65kHz

9 80 168.75kHz

| | |

12 104 118.15kHz

| |

14 120 102.4kHz

15 128 96kHz

| | |

24 200 61.45kHz

| | |

33 272 45.2kHz

| | |

37 304 40.4kHz

| | |

49 400 30.7kHz

| | |

127 1024 12kHz

SFR Address

PCON 87H

S0CON 99H

S0BUF 9AH

Table 12 UART Special Function Registers

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S0BUFThis register is implemented twice. Writing to S0BUFwrites to the transmit buffer. Reading from S0BUF readsfrom the receive buffer. Only hardware can read from thetransmit buffer and write to the receive buffer.

SMOD bit of PCONSMOD is the double baud rate bit. If SMOD=’1’ the baudrate in mode 1, 2 and 3 is doubled. In mode 0 SMOD is notused.

UART ModesThe serial port can operate in 4 modes: -

Mode 0: Serial data enters and exits through RxD. TxDoutputs the shift clock. 8 bits are transmitted/received(LSB first). The baud rate is fixed at 1/6 the frequency ofclk.Mode 1: 10 bits are transmitted (through TxD) or received(through RxD): a start bit (’0’), 8 data bits (LSB first), and astop bit (’1’). On receive, the stop bit goes into RB8 inSpecial Function Register S0CON. The baud rate isdetermined by the Timer 1 overflow rate.Mode 2: 11 bits are transmitted (through TxD) or received(through RxD): start bit (’0’), 8 data bits (LSB first), a 9thdata bit, and a stop bit (’1’). On Transmit, the 9th data bit,TB8 in S0CON, can be assigned the value of ’0’ or ’1’. Forexample, the parity bit could be moved into TB8. Onreceive, the 9th data bit goes into RB8 in S0CON, while thestop bit is ignored. The baud rate is programmable toeither 1/32 or 1/64 the frequency of the micro-controllerclock.Mode 3: 11 bits are transmitted (through TxD) or received(through RxD): a start bit (’0’), 8 data bits (LSB first), a 9thdata bit, and a stop bit (’1’). In fact, mode 3 is the same asmode 2 in all respects except baud rate. The baud rate isdetermined by the Timer 1 overflow rate.

In all four modes, transmission is initiated by anyinstruction that uses S0BUF as a destination register.Reception is initiated in mode 0 by the condition RI = ’0’and REN = ’1’. In the other modes reception is initiated bythe incoming start bit if REN = 1.

UART Multi-Processor CommunicationsModes 2 and 3 have a special provision for multiprocessorcommunications. In these modes, 9 data bits are received.The 9th bit goes into RB8, followed by a stop bit. The portcan be programmed such that when the stop bit isreceived, the serial port interrupt will be activated only ifRB8 = ’1’. This feature is enabled by setting bit SM2 inS0CON. A way to use this feature in multi-processorsystems is as follows:When the master processor wants to transmit a block ofdata to one of several slaves, it first sends out an addressbyte which identifies the target slave. An address bytediffers from a data byte. The 9th bit is ’1’ in an address byteand ’0’ in a data byte. With SM2 = ’1’, no slave will beinterrupted by a data byte reception. An address byte,however, will interrupt all slaves, so that each slave canexamine the received byte and see if it is being addressed.The addressed slave will clear its SM2 bit and prepare toreceive the data bytes that will follow. The slaves thatweren’t being addressed leave their SM2s set and go onabout their business, ignoring the incoming data bytes.SM2 has no effect in mode 0, and in mode 1 it can be usedto check the validity of the stop bit. When receiving in

SM0 SM1 SM2 REN TB8 RB8 TI RI

Symbol Position Name and SignificanceSM0 S0CON.7 Mode selection bit 0.SM1 S0CON.6 Mode selection bit 1.SM2 S0CON.5 Enables the multi processor

communication feature in modes2 and 3. In mode 2 or 3, if SM2 isset, then RI will not be activated,RB8 and S0BUF will not beloaded if the received 9th databit is ’0’. In mode 1, if SM2 is set,then RI will not be activated,RB8 and S0BUF will not beloaded if no valid stop bit wasreceived. In mode 0, SM2 has noinfluence.

REN S0CON.4 Enables serial reception. Set bysoftware to enable reception.Cleared by software to disablereception.

Symbol Position Name and SignificanceTB8 S0CON.3 Is the 9th data bit that will be

transmitted in modes 2 and 3.Set or cleared by software asdesired.

RB8 S0CON.2 In modes 2 and 3, RB8 is the 9thdata bit that was received. Inmode 1, if SM2 is ’0’, RB8 is thestopbit that was received. Inmode 0, RB8 is not used. Load-ing of RB8 in modes 1, 2 and 3depends on SM2.

TI S0CON.1 Is the transmit interrupt flag. Setby hardware at the end of the 8thbit time in mode 0, or at the

Fig.19 S0CON Special Function Registers

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mode 1, if SM2 = ’1’, the receive interrupt will not beactivated unless a valid stop bit is received.

S0BUF RegistersThis register is implemented twice. Writing to S0BUFwrites to the transmit buffer. Reading from S0BUF readsfrom the receive buffer. Only hardware can read from thetransmit buffer and write to the receive buffer.

UART Baud RatesNOTE: fclk used in the following calculations refers to themicro-controller clock frequency (12.288MHz).The serial port can operate with different baud ratesdepending on its mode. The baud rate in mode 0 is derivedfrom state 2 and state 5 and thus fixed:Mode 0 baud rate = fclk/ 6The baud rate in mode 2 depends on the value of bitSMOD.

If SMOD = 0, the baud rate is fclk/32If SMOD = 1, the baud rate is fclk/16

Mode 2 baud rate =

The baud rates in mode 1 and 3 are determined by theTimer 1 overflow rate and the value of SMOD as follows:

Mode 1, 3 baud rate =

The Timer 1 interrupt should be disabled in thisapplication. The Timer itself can be configured for either’timer’ or ’counter’ operation, and in any of its 3 runningmodes. In the most typical applications, it is configured for’timer’ operation, in the auto-reload mode (high nibble ofTMOD = 0010B). In that case the baud rate is given by theformula:

Mode 1, 3 Baud Rate =

One can achieve very low baud rates with Timer 1 byleaving the Timer 1 interrupt enabled, and configuring theTimer to run as a 16-bit timer (high nibble of TMOD =0001B), and using the Timer 1 interrupt to do a 16-bitsoftware reload.

For further details on the UART operation refer to “80C51Based 8-Bit Micro-controllers - Philips Semiconductors(ref. IC20).

Remote Control Pre-processorThe remote control pre-processor is used to reduce thenumber of wake-up’s for the 80c51 core (from IDLEmode).

To Start the remote control pre-processor, bit 7 of RCP6register (SFR address EEH), must be programmed to ‘1’.Afterward, SW has to program the RCP-SFRs:-

• Clock divider rate CDIV (= divider between Xtaland RCP counter)

• AL = 75% of the nominal, shortest allowableLOW pulse

• AH = 125% of the nominal, longest allowablepulse MINUS AL (saves timer span & is easierfor SW)

• BL, BH = same as AL, AH, but then for theHIGH time of the pulse

Because RC5 does not have a real start-pulse (long, withother timing) the registers AL, AH, BL, BH don’t have tobe written every pulse transition.

Further the SW (re-)programs:

• NGP = 0 -> the flag that tells the RCP-HW hasfound a timing-error (not in the first pulse) andso the RC5 message string decoding must beterminated.

• NFP = 0 -> means the RCP-HW is “hunting” forthe first pulse. If there occurs a timing-error dur-ing the first pulse, the micro gets NO wake-upinterrupt. The RCP keeps hunting for a pulsethat matches the “start-pulse-timing”. (= idealfor protocols with a ling start-pulse). TheRCP-HW sets NFP=1, to signal that the first(start-) pulse was found. Further NFP=1 takescare that any following-pulse-with-errorALWAYS generates a wake-up interrupt (termi-nate decoding).

Now the SW goes to sleep in IDLE mode. The Xtal clockcontinues, watchdog timer, timer & RCP keep working(with same Xtal frequency).

When an RC-INT arrives, the micro-core wake-up inSTANDBY mode. Now the SW must read the RCP resultsfrom RA, RB (two 12-bits, folded into 3 SFRS:- RCP3,RCP4, and RCP5) plus the error flags NFP and NGP.(note that after the FIRST pulse, the RCP-HW will alwayscome back with NGP=0).

When there is an error (NGP=1), then the RC-stringdecoding must be terminated (i.e. further, trailing bits willmake an the following string an invalid one).

2SMOD

32------------------ fclk×

2SMOD

32------------------ Timer1OverflowRate( )×

2SMOD

32------------------

fclk

6 256 T1H–( )×------------------------------------------×

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With NO-ERROR the SW only has to check if RA and RBare longer than 1x tp (minus 75% of the shortest allowablepulse=AL) which show whether the pulse had a width of1x tp or 2x tp.

This simplifies the decoding SW considerably (timingerrors are already checked by RCP-HW), for RC5 thebi-phase decoding-method is similar to the older SW.

If an error NGP=1 is received, then break-off the decodingand let SW set NFP=0, so that the HW starts huntingagain for the FIRST pulse.

At the END of an RC5 string there is a special condition: aLOW-pulse, followed by a HIGH data-clean time (>2.5tp),WITHOUT subsequent interrupt. A simple solution is toload the BH register BEFORE the last pulse with 3xtp(minus AL). As a consequence you will get an INT after3tp data clean time: in this special case NGP=1 showsduring 3tp nothing has happened, to the message hasended OK.

The following table shows the timing characteristics ofsome existing Remote Control Protocols:-

Table 13 Remote Control Protocols

I2S Clock Output SelectionThe I2S Clock output can be selected viaI2S.I2S_CLK<1:0> SFRs. The output clock is shown inbelow:-fs=32kHz

LED SupportAll port pins have a 4mA current sinking capability toenable LEDs in series with current limiting resistors to bedriven directly, without the need for additional bufferingcircuitry.

SRAM MEMORY INTERFACEThe SRAM memory interface controls the access to theembedded SRAM and page clearing. The SRAM is sharedbetween Data Capture and Display sections. The DataCapture section uses the SRAM to store acquired

information that has been requested. The Display readsthe SRAM information and converts it to RGB outputvalues.The display RAM is initialized on power-on to a value of20H throughout. The contents of the display RAM is notmaintained when entering power saving modes (stand-by,idle, and power-down). Upon leaving standby mode andresuming normal operation, the display RAM is initializedto a value of 20H throughout again (by hardware). Thesame applies when a software reset is issued. In this case,the display RAM is initialized to 20H throughout as well.The Display RAM occupies a maximum of 20K with anaddress range from 2000H to 6FFFH; the TXT14.DISPLAY BANK<3:0> and TXT15.MICRO BANK<3:0>must keep default value “0000”. The RDS/RBDS DisplayData occupies 1.25K with an address range from 7000H to74FF H. The three modes although having differentaddress ranges occupy physical the same SRAM area.When TXT27.RDS ON = 1, the RDS/RBDS Displaymemory would map to the physical SRAM area. WhenTXT27.RDS ON=0, TXT21.CC/TXT=1 / 0, then the CC /TXT memory would map to the physical SRAM area.

Data CaptureThe Data Capture section takes in the analogueComposite Video and Blanking Signal (CVBS) from VideoSignal Processor, and from this extracts the required data,which is then decoded and stored in SFR or memory.

Name RC5 Sony NEC Motorola Japan Daewoo Samsung Denon

Startbit 889us 2.4ms 9ms 3ms 3.38ms 8ms 4.5ms -

Shortest 889us 600us 560us 512us 420us 450us 560us 275us

Longest 1178us 1.2ms 1.69ms 1024us 1.27ms 1.45ms 1.69ms 1.9ms

Repeat 113.8ms 45ms 67.5ms 34ms 90ms 60ms 60ms 65ms

I2S.I2S_CLK<1:0> I2S Clock Output

00 256fs

01 128fs

10 64fs

11 not allowed

Table 14 I2S Clock Output Selection

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The extraction of the data is performed in the digitaldomain. The first stage is to convert the analogue CVBSsignal into a digital form. This is done using an ADCsampling at 12.288MHz. The data and clock recovery isthen performed by a Multi-Rate Video Input Processor(MulVIP). From the recovered data and clock the followingdata types are extracted WST Teletext (625/525),ClosedCaption, VPS, WSS(625). The extracted data is stored ineither memory (SRAM) via the SRAM Memory Interface orin SFR locations.

Data Capture Features• Video Signal Quality detector.

• Data Capture for 625 line WST

• Data Capture for 525 line WST

• Data Capture for US Closed Caption

• Data Capture for VPS data (PDC system A)

• Data Capture for 625 line Wide Screen Signalling (WSS)bit decoding

• Automatic selection between 525 WST/625WST

• Automatic selection between 625WST/VPS on line 16 ofVBI

• Real-time capture and decoding for WST Teletext inHardware, to enable optimized microprocessorthroughput

• Up to 10 pages stored On-Chip

• Inventory of transmitted Teletext pages stored in theTransmitted Page Table (TPT) and Subtitle Page Table(SPT)

• Automatic detection of FASTEXT transmission

• Real-time packet 26 engine in Hardware for processingaccented, G2 and G3 characters

• Signal quality detector for WST/VPS data types

• Comprehensive Teletext language coverage

• Vertical Blanking Interval (VBI) data capture of WSTdata

Analogue to Digital ConverterThe CVBS input is passed through a differential to singleended converter (S/D-Conv+Level-shift). The analogueoutput of S/D-Conv+Level-shift is converted into a digitalrepresentation by a Video ADC with a sampling rate of12.288MHz.

Multi Rate Video Input ProcessorThe multi rate video input processor is a Digital SignalProcessor designed to extract the data and recover theclock from the digital CVBS signal.

Data StandardsThe data and clock standards that can be recovered areshown in Table 15 below:-

Data Capture TimingThe Data Capture timing section uses the Synchronisationinformation extracted from the CSI signal to generate therequired Horizontal and Vertical reference timings.The timing section automatically recognises and selectsthe appropriate timings for either 625 (50Hz)synchronisation or 525 (60Hz) synchronisation. A flagTXT12.Video Signal Quality is set when the timing sectionis locked correctly to the incoming CVBS signal. WhenTXT12.Video Signal Quality is set another flagTXT12.625/525 SYNC can be used to identify thestandard.

AcquisitionThe acquisition sections extracts the relevant informationfrom the serial stream of data from the MulVIP and storesit in memory.

625 WST ACQUISITION

The family is capable of acquiring 625-line and 525-lineWorld System Teletext. Teletext pages are identified byseven numbers: magazine (page hundreds), page tens,page units, hours tens, hours units, minutes tens andminutes units. The last four digits, hours and minutes, areknown as the subcode, and were originally intended to betime related, hence their names.

Making a page requestA page is requested by writing a series of bytes into theTXT3.PRD<4:0> SFR which correspond to the number ofthe page required. The bytes written into TXT3 are storedin a RAM with an auto-incrementing address. The startaddress for the RAM is set using the TXT2.SC<2:0> todefine which part of the page request is being written,TXT2.ACQ_BANK<0> and TXT3.ACQ_BANK<3:1> areused to define which bank and TXT2.REQ<3:0> is used todefine which of the 10 page requests in the selected bank

Data Standard Clock Rate

625WST 6.9375 MHz

525WST 5.7272 MHz

VPS 5.0 MHz

625WSS 5.0 MHz

Closed Caption 500 KHz

Table 15 Data Slicing Standards

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is being modified. If TXT2.REQ<3:0> is greater than 09h,then data being written to TXT3 is ignored. Table 16 showsthe contents of the page request RAM.Up to 10 pages of teletext can be acquired on the 10 pagedevice when TXT1.EXT PKT OFF is set to logic 1; and upto 9 pages can be acquired when this bit is set to logic 0.If the 'Do Care' bit for part of the page number is set to 0then that part of the page number is ignored when theteletext decoder is deciding whether a page beingreceived off air should be stored or not. For example, if theDo Care bits for the 4 subcode digits are all set to 0 thenevery subcode version of the page will be captured.

Table 16 The contents of the Page request RAM

Note: MAG = Magazine PT = Page Tens PU = Page UnitsHT = Hours Tens HU = Hours UnitsMT = Minutes Tens MU = Minutes Units E = Error checkmodeWhen the Hold bit is set to 0 the teletext decoder will notrecognise any page as having the correct page numberand no pages will be captured. In addition to providing theuser requested hold function this bit should be used toprevent the inadvertent capture of an unwanted pagewhen a new page request is being made. For example, ifthe previous page request was for page 100 and this wasbeing changed to page 234, it would be possible to capturepage 200 if this arrived after only the requested magazinenumber had been changed.The E1 and E0 bits control the error checking which shouldbe carried out on packets 1 to 23 when the page beingrequested is captured. This is described in more detail in alater section (‘Error Checking’).For a multi page device, each packet can only be writteninto one place in the teletext RAM so if a page matchesmore than one of the page requests the data is written intothe area of memory corresponding to the lowest numberedmatching page request.At power-up each page request defaults to any page, holdon and error check mode 0.

Rolling Headers and TimeWhen a new page has been requested it is conventionalfor the decoder to turn the header row of the display green

and to display each page header as it arrives until thecorrect page has been found.When a page request is changed (i.e.: when the TXT3SFR is written to) a flag (PBLF) is written into bit 5, column9, row 25 of the corresponding block of the page memory.The state of the flag for each block is updated every TVline, if it is set for the current display block, the acquisitionsection writes all valid page headers which arrive into thedisplay block and automatically writes an alpha-numericsgreen character into column 7 of row 0 of the display blockevery TV line.When a requested page header is acquired for the firsttime, rows 1 to 23 of the relevant memory block arecleared to space, i.e.: have 20h written into every column,before the rest of the page arrives. Row 24 is also clearedif the TXT0.X24 POSN bit is set. If the TXT1.EXT PKT OFFbit is set the extension packets corresponding to the pageare also cleared.The last 8 characters of the page header are used toprovide a time display and are always extracted from everyvalid page header as it arrives and written into the displayblockThe TXT0. DISABLE HEADER ROLL bit prevents anydata being written into row 0 of the page memory exceptwhen a page is acquired off air i.e.: rolling headers andtime are not written into the memory. The TXT1.ACQ OFFbit prevents any data being written into the memory by theteletext acquisition section.When a parallel magazine mode transmission is beingreceived only headers in the magazine of the pagerequested are considered valid for the purposes of rollingheaders and time. Only one magazine is used even if don'tcare magazine is requested. When a serial magazinemode transmission is being received all page headers areconsidered to be valid.

Error CheckingBefore teletext packets are written into the page memorythey are error checked. The error checking carried outdepends on the packet number, the byte number, the errorcheck mode bits in the page request data and the TXT1.8BIT bit.If an uncorrectable error occurs in one of the Hammingchecked addressing and control bytes in the page headeror in the Hamming checked bytes in packet 8/30, bit 4 ofthe byte written into the memory is set, to act as an errorflag to the software. If uncorrectable errors are detected inany other Hamming checked data the byte is not writteninto the memory.

Teletext Memory OrganisationThe teletext memory is divided into 10 banks of 10 blocks.Normally, when the TXT1.EXT PKT OFF bit is logic 0,

StartColumn

ByteIdentification PRD<4> PRD<3> PRD<2> PRD<1> PRD<0>

0 Magazine DO CARE HOLD MAG2 MAG1 MAG0

1 Page Tens DO CARE PT3 PT2 PT1 PT0

2 Page Units DO CARE PU3 PU2 PU1 PU0

3 Hours Tens DO CARE x x HT1 HT0

4 Hours Units DO CARE HU3 HU2 HU1 HU0

5 Minutes Tens DO CARE x MT2 MT1 MT0

6 Minutes Units DO CARE MU3 MU2 MU1 MU0

7 Error Mode x x x E1 E0

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each of blocks 0 to 8 contains a teletext page arranged inthe same way as the basic page memory of the pagedevice and block 9 contains extension packets. When theTXT1.EXT PKT OFF bit is logic 1, no extension packetsare captured and block 9 of the memory is used to storeanother page. The number of the memory block into whicha page is written corresponds to the page request numberwhich resulted in the capture of the page.Packet 0, the page header, is split into 2 parts when it iswritten into the text memory. The first 8 bytes of the headercontain control and addressing information. They areHamming decoded and written into columns 0 to 7 of row25. Row 25 also contains the magazine number of theacquired page and the PBLF flag but the last 14 bytes areunused and may be used by the software, if necessary.

Row 25 Data ContentsThe Hamming error flags are set if the on-board 8/4Hamming checker detects that there has been anuncorrectable (2 bit) error in the associated byte. It ispossible for the page to still be acquired if some of thepage address information contains uncorrectable errors ifthat part of the page request was a 'don't care'. There is noerror flag for the magazine number as an uncorrectableerror in this information prevents the page being acquired.The interrupted sequence (C9) bit is automatically dealtwith by the acquisition section so that rolling headers donot contain a discontinuity in the page number sequence.The magazine serial (C11) bit indicates whether thetransmission is a serial or a parallel magazinetransmission. This affects the way the acquisition sectionoperates and is dealt with automatically.The newsflash (C5), subtitle (C6), suppress header (C7),inhibit display (C10) and language control (C12 to 14) bitsare dealt with automatically by the display section,described below.The update (C8) bit has no effect on the hardware. Theremaining 32 bytes of the page header are parity checkedand written into columns 8 to 39 of row 0. Bytes which passthe parity check have the MSB set to 0 and are written intothe page memory. Bytes with parity errors are not writteninto the memory.

Inventory PageIf the TXT0.INV on bit is 1, memory block 8 is used as aninventory page. The inventory page consists of two tables,- the Transmitted Page Table (TPT) and the subtitle pagetable (SPT).In each table, every possible combination of the page tensand units digit, 00 to FFh, is represented by a byte. Eachbit of these bytes corresponds to a magazine number soeach page number, from 100 to 8FF, is represented by abit in the table.The bit for a particular page in the TPT is set

when a page header is received for that page. The bit inthe SPT is set when a page header for the page is receivedwhich has the ‘subtitle’ page header control bit (C6)set.The bit for a particular page in the TPT is set when apage header is received for that page. The bit in the SPTis set when a page header for the page is received whichhas the ‘subtitle’ page header control bit (C6) set.

Packet 26 ProcessingOne of the uses of packet 26 is to transmit characterswhich are not in the basic teletext character set. The familyautomatically decodes packet 26 data and, if a charactercorresponding to that being transmitted is available in thecharacter set, automatically writes the appropriatecharacter code into the correct location in the teletextmemory. This is not a full implementation of the packet 26specification allowed for in level 2 teletext, and so is oftenreferred to as level 1.5.By convention, the packets 26 for a page are transmittedbefore the normal packets. To prevent the defaultcharacter data over writing the packet 26 data the deviceincorporates a mechanism which prevents packet 26 datafrom being overwritten. This mechanism is disabled whenthe Spanish national option is detected as the Spanishtransmission system sends even parity (i.e. incorrect)characters in the basic page locations corresponding tothe characters sent via packet 26 and these will not overwrite the packet 26 characters anyway. The specialtreatment of Spanish national option is prevented ifTXT12. ROM VER R4 is logic 0 or if the TXT8.DISABLESPANISH is set.Packet 26 data is processed regardless of the TXT1. EXTPKT OFF bit, but setting theTXT1.X26 OFF disablespacket 26 processing.The TXT8. Packet 26 received bit is set by the hardwarewhenever a character is written into the page memory bythe packet 26 decoding hardware. The flag can be reset bywriting a 0 into the SFR bit.

In the first edition of ETS 300 706, the “@” symbol isavailable for display at level 1 only when:1). the page uses the Latin G0 set and selects the Englishnational option set,or2). when the Hebrew G0 character set is selected.The device will also display @ in response to the packet 26triplet containing NULL accent (mode value 10000) andcharacter 4/0 providing the Latin G0 set is currentlyselected.The * character is available as a level 1 character in all ofthe defined G0 character sets and it is very unlikely that a* character would be invoked at level 1.5 via the tripletNULL accent, character 2/A. Therefore, the second edition

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of ETS 300 706 defines that the @ symbol should bedisplayed in response to the NULL accent, character 2/Atriplet for all G0 character set.The IC will display the * character while providing * is sentas the fallback character on the level 1 page, and dependon the software (DDS) to implement the first edition of ETS300 706 which should also display *, or the second editionof ETS 300 706 which should display the @ symbol.

525 WSTThe 525 line format is similar to the 625 line format but thedata rate is lower and there are less data bytes per packet(32 rather than 40). There are still 40 characters perdisplay row so extra packets are sent each of whichcontains the last 8 characters for four rows. These packetscan be identified by looking at the ‘tabulation bit’ (T), whichreplaces one of the magazine bits in 525 line teletext.When an ordinary packet with T = 1 is received, thedecoder puts the data into the four rows starting with thatcorresponding to the packet number, but with the 2 LSBsset to 0. For example, a packet 9 with T = 1 (packet X/1/9)contains data for rows 8, 9, 10 and 11. The error checkingcarried out on data from packets with T = 1 depends on thesetting of the TXT1. 8 BIT bit and the error checking controlbits in the page request data and is the same as thatapplied to the data written into the same memory locationin the 625 line format.The rolling time display (the last 8 characters in row 0) istaken from any packets X/1/1, 2 or 3 received. In parallelmagazine mode only packets in the correct magazine areused for rolling time. Packet number X/1/0 is ignored.The tabulation bit is also used with extension packets. Thefirst 8 data bytes of packet X/1/24 are used to extend theFastext prompt row to 40 characters. These characters arewritten into whichever part of the memory the packet 24 isbeing written into (determined by the ‘X24 Posn’ bit).Packets X/0/27/0 contain 5 Fastext page links and the linkcontrol byte and are captured, Hamming checked andstored by in the same way as are packets X/27/0 in 625line text. Packets X/1/27/0 are not captured.Because there are only 2 magazine bits in 525 line text,packets with the magazine bits all set to 0 are referred toas being in magazine 4. Therefore, the broadcast servicedata packet is packet 4/30, rather than packet 8/30. As in625 line text, the first 20 bytes of packet 4/30 containencoded data which is decoded in the same way as that inpacket 8/30. The last 12 bytes of the packet contains halfof the parity encoded status message. Packet 4/0/30contains the first half of the message and packet 4/1/30contains the second half. The last 4 bytes of the messageare not written into memory. The first 20 bytes of the each

version of the packet are the same so they are storedwhenever either version of the packet is acquired.In 525 line text each packet 26 only contains ten 24/18Hamming encoded data triplets, rather than the 13 foundin 625 line text. The tabulation bit is used as an extra bit(the MSB) of the designation code, allowing 32 packet 26sto be transmitted for each page. The last byte of eachpacket 26 is ignored.

FASTEXT DETECTION

When a packet 27, designation code 0 is detected,whether or not it is acquired, the TXT13. FASTEXT bit isset. If the device is receiving 525 line teletext, a packetX/0/27/0 is required to set the flag. The flag can be resetby writing a 0 into the SFR bit.

BROADCAST SERVICE DATA DETECTION

When a packet 8/30 is detected, or a packet 4/30 when thedevice is receiving a 525 line transmission, the TXT13.Packet 8/30. The flag can be reset by writing a 0 into theSFR bit. The data of packet 8/30 is written to the block 9.

VPS ACQUISITION

When the TXT0. VPS ON bit is set, any VPS data presenton line 16, field 0 of the CVBS signal at the input of theteletext decoder is error checked and stored in row 25,block 9 of the basic page memory. The deviceautomatically detects whether teletext or VPS is beingtransmitted on this line and decodes the dataappropriately.

Each VPS byte in the memory consists of 4 bi-phasedecoded data bits (bits 0-3), a bi-phase error flag (bit 4)and three 0s (bits 5-7). The TXT13. VPS Received bit isset by the hardware whenever VPS data is acquired. Theflag can be reset by writing a 0 into the SFR bit.

625 WSS ACQUISITION

The Wide Screen Signalling data transmitted on line 23gives information on the aspect ratio and display positionof the transmitted picture, the position of subtitles and onthe camera/film mode. Some additional bits are reservedfor future use. A total of 14 data bits are transmitted. All ofthe available data bits transmitted by the Wide Screen

Fig.20 VPS Data Storage

Teletext pageheader data

VPSbyte 11

VPSbyte 12

VPSbyte 13

VPSbyte 14

VPSbyte 15

VPSbyte 4

VPSbyte 5

0 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23column

row 25

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Signalling signal are captured and stored in SFRs WSS1,WSS2 and WSS3. The bits are stored as groups of relatedbits and an error flag is provided for each group to indicatewhen a transmission error has been detected in one ormore of the bits in the group. Wide screen signalling datais only acquired when the TXT8.WSS ON bit is set. TheTXT8.WSS RECEIVED bit is set by the hardwarewhenever wide screen signalling data is acquired. The flagcan be reset by writing a 0 into the SFR bit.

CLOSED CAPTION ACQUISITION

The US Closed Caption data is transmitted on line 21 (525line timings) and is used for Captioning information, Textinformation and Extended Data Services. Closed Captiondata is only acquired when TXT21.CC ON bit is set.Two bytes of data are stored per field in SFRs, the first byeis stored in CCDAT1 and the second byte is stored inCCDAT2. The value in the CCDAT registers are reset to00h at the start of the Closed Caption line defined byCCLIN.CS<4:0>. At the end of the Closed Caption line aninterrupt is generated if IE.ECC is active.The processing of the Closed Caption data to convert intoa displayable format is performed by Software.

RDS/RBDSThe Radio Data System (RDS)/ Radio Broadcast DataSystem (RBDS) informations are carried in FM radiochannels. The FM radio channels are located in the rangefrom 87.5MHz to 108MHz. Once a radio channel is tuned,the MPX signal is processed by this block.

RDS/RBDS Features• Demodulation of the European Radio Data System

(RDS) or the USA Radio Broadcast Data System(RBDS) signal

• RDS and RBDS block detection

• Error detection and correction

• Fast block synchronization

• Synchronization control (flywheel)

• Mode control for RDS/RBDS processing

• Different RDS/RBDS block information output modes

Analogue to Digital ConverterThe RDS input is passed to a single ended to differentialconverter (S/D-conv+L-shift). The analogue output ofS/D-conv+L-shift is converted into a digital representationby a Video ADC with a sampling rate of 304kHz.

RDS_SubsystemThe RDS_SUBSYSTEM contains Serialiser, RDSdemodulator, and RDS/RBDS decoder.

SerialiserThe RDS Serialiser converts the 304kHz 10-bits paralleldata to 9.728MHz 32-bits serial data (10-bits data, 22-bitsdummy). The output bitstream data of the Serialiser willthen feed to Demodulator.

DEMODULATOR

The RDS demodulator regenerates the raw RDS bitstream (bit rate=1187.5 Hz) from the modulated RDSsignal in two steps. The first step is the demodulation of theDouble-Side-Band Suppressed-Carrier signal around 57kHz into a baseband signal, by carrier extraction anddown-mixing. The second step is the BPSK demodulationof the biphase coded baseband signal, by clock extractionand correlation. The raw RDS bit stream data is providedfor further processing by the RDS/RBDS decoder block.

DECODER

The RDS/RBDS decoder handles the complete dataprocessing and decoding of the continuously receivedserial RDS/RBDS demodulator output data stream.Different data processing modes are software controllablevia SFRs.The RDS/RBDS decoder provides the RDS/RBDS blockdetection, error detection, error correction,synchronization, flywheel for synchronization hold, andprogrammable block data output. New processedRDS/RBDS block information is signalled (interrupt) to themicro-controller as “new data available” by use of theDAVN output. The block data and the correspondingstatus information will be output to the RDS SFRs and canbe read out by micro-controller via SFR Interface.The processing of the RDS/RBDS data to convert into adisplayable format is performed by Software.

RDS/RBDS Block DetectionThe RDS/RBDS block detection is always active.For a received sequence of 26 data bits a valid block andcorresponding offset are identified via syndromecalculation.During synchronization search, the syndrome is calculatedwith every new received data bit (bit-by-bit) for a received26-bit sequence. If the decoder is synchronized, syndromecalculation is activated only after 26 data bits for each newblock received.Under RBDS reception situation, besides the RDS blocksequences with (A, B, C/C’, D) offset also block sequencesof 4 blocks with offset E may be received. If the decoderdetects an ‘E-block’, the block is marked in the block

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identification number (BlNr<2:0>) and is stored in the SFRLBIN<2:0>. In RBDS processing mode the block issignalled as valid ‘E-block’ and in RDS processing mode,where only RDS blocks are expected, signalled as invalid‘E-block’.This information can be used by the micro-controller todetect ‘E-block’ sequences and identify RDS or RBDStransmitter stations.

Error Detection and CorrectionThe RDS/RBDS error detection and correction recognizesand corrects potential transmission errors within areceived block via parity-check in consideration of theoffset word of the expected block. Burst errors with amaximum length of 5 bits are corrected with this method.After synchronization has been found the error correctionis always active depending on the pre-selected ‘errorcorrection mode of synchronization’ (mode SYNCA ...SYNCD), but cannot be carried out in every receptionsituation.During synchronization search, the error correction isdisable for detection of the first block and is enable forprocessing of the second block depending on thepre-selected ‘error correction mode for synchronization’(mode SYNCA ... SYNCD).The processed block data and the status of errorcorrection are stored in the SFRs (Status Registers).

Table 17 RDS processed error correction

Processed blocks are characterized as uncorrectableunder the following conditions:• During synchronization search, if the burst error (for the

second block) is higher than allowed by the pre-selectedcorrection mode SYNCA ... SYNCD.

• After synchronization has been found, if the burst errorexceeds the correctable max. 5 bit burst error or if errorsare detected but error correction is not possible.

SynchronizationThe decoder is synchronized if two valid blocks in a validsequence are detected by the block detection.The search for the first block is done by a bit-by-bitsyndrome calculation, starting after the first 26 bits havebeen received. This bit-by-bit syndrome calculation is

carried out until the first valid and error free block has beenreceived. Then the next expected block calculated andsyndrome calculation is done after the next 26 bits havebeen received. The block-span in which the second validand expected block can be received is selectable viapreviously setting of the Max_Bad_Blocks_Gain(MBBG<4:0>). If the second received block is an invalidblock, then the bad_blocks_counter is incremented andagain the new next expected block is calculated. If thebad_blocks_counter value reaches the pre-selectedMax_Bad_Blocks_Gain, then the bit-by-bit search for thefirst block is started again.If synchronization is found, the synchronization status flag(SYNC) is set and available via SFR read. Thesynchronization is held until the bad_blocks_counter valuereaches the pre-selected Max_Bad_Blocks_Lose value(used for synchronization hold) or an external restart ofsynchronization is performed (NWSY=1; or power-onreset).

FLYWHEEL FOR SYNCHRONIZATION HOLD

For a fast detection of loss of synchronization an internalflywheel shall be implemented. Therefore one counter(bad_blocks_counter) checks the number of uncorrectableblocks and a second counter (good_blocks_counter)checks the number of error free or correctable blocks.Error blocks increment the bad_blocks_counter and validblocks increment the good_blocks_counter. If the countervalue of the good_blocks_counter reaches thepre-selected Max_Good_Blocks_Lose value (MGBL<5:0>the good_blocks_counter and bad_blocks_counter arereset to zero. But if the bad_blocks_counter reaches thepre-selected Max_Bad_Blocks_Lose value (MBBL<5:0>)then new synchronization search (bit-by-bit) is started(SYNC=0) and both counters are reset to zero.The flywheel function is only activated if the decoder issynchronized. The synchronization is held until thebad_blocks_counter reaches the pre-selectedMax_Bad_Blocks_Lose value (loss of synchronization) oran external forced start of new synchronization search(NWSY=1) is performed. The maximum values for theflywheel counters are both adjustable via SFR in a rangeof 0 to 63.

Bit Slip CorrectionDuring poor reception situation phase shifts of one bit tothe left or right (+/- 1 bit slip) between the RDS/RBDS clockand data may occur, depending on the lock conditions ofthe demodulator clock regeneration.If the decoder is synchronized and detects a bit slip(BSLP=1), the synchronization is corrected +1, 0 or -1 bitvia block detection on the respectively shifted expectednew block.

EXB1 EXB0 Description

0 0 no errors detected

0 1 burst error of max. 2 bits corrected

1 0 burst error of max. 5 bits corrected

1 1 uncorrectable block

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Data Processing ControlThe decoder should provide different operating modesselectable by NWSY, SYM0, SYM1, DAC0 and DAC1inputs via the SFRs. The data processing control performsthe pre-selected operating modes and controls therequested output of the RDS/RBDS information.

Restart of Synchronization ModeThe ‘restart synchronization’ (NWSY) control modeimmediately terminates the actual synchronization andrestarts a new synchronization search procedure(NWSY=1). The NWSY flag is automatically reset after therestart of synchronization by decoder (NWSYRe pulse).This mode is required for a fast new synchronization on theRDS/RBDS data from a new transmitter station if thetuning frequency is changed by the radio set.Restart of synchronization search is furthermoreautomatically carried out if the internal flywheel signals aloss of synchronization.

Error Correction Control Mode For SynchronizationFor error correction and identification of valid blocks duringsynchronization search as well as synchronization hold,four different modes are selectable (SYM<1>, SYM<0>).• mode SYNCA (SYM<1>=0, SYM<0>=0): no error

correction; blocks detected as correctable are treated asinvalid blocks internal bad_blocks_counter stillincremented even if correctable errors detected. Ifsynchronized only error free blocks increment thegood_blocks_counter. All blocks except error freeblocks increment the bad_blocks_counter.

• mode SYNCB (SYM<1>=0, SYM<0>=1): errorcorrection of burst error max. 2 bits; blocks corrected aretreated as valid blocks, all other errors detected aretreated as invalid blocks. If synchronized error free andcorrectable max. 2 bit error increment thegood_blocks_counter.

• mode SYNCC (SYM<1>=1, SYM<0>=0): errorcorrection of burst error max. 5 bits; blocks corrected aretreated as valid blocks, all other errors detected aretreated as invalid blocks. If synchronized error free andcorrectable max. 5 bit error increment thegood_blocks_counter.

• mode SYNCD (SYM<1>=1, SYM<0>=1): no errorcorrection; blocks detected as correctable are treated asinvalid always incremented even if correctable errorsdetected. If synchronized error free blocks arecorrectable max. 5 bit errors increment thegood_blocks_counter. Only uncorrectable blocksincrement the bad_blocks_counter.

RBDS Processing ModeThe decoder should be suitable for receivers intended forthe European (RDS) as well as for the USA (RBDS)standard. If RBDS mode is selected (RBDS=1) via theSFR, the block detection and the error detection andcorrection are adjusted to RBDS data processing. That is,also E blocks are treated as valid blocks. If RBDS is resetto zero (RDS_CTRL.RBDS=0), RDS mode is selected.

Data Available Control ModesThe decoder provides three different RDS/RBDS dataoutput processing modes plus one decoder bypass modeselectable via the ’data available’ control mode inputsDAC0 and DAC1.

Table 18 DAV Modes

The decoder provides:- data output of theblock-identification of the last and previously processedblocks, the RDS/RBDS information words and errordetection/correction status of the last two blocks as well asgeneral decoder status information.In addition the decoder output is controlled indirectly by thedata request (SFR read) by micro-controller. The decoderreceives a ‘data overflow’ (DOFL) signal controlled by theSRF. This DOFL signal has to be set to high (DOFL=1) ifthe decoder is synchronized and a new RDS/RBDS blockis received before the previously processed block wascompletely transmitted via SFRs. After detection of dataoverflow the SFRs are not updated (no DecWrE) until resetof the data overflow flag (DOFL=0) by reading via theSFRs or if NWSY=1 which results in start of newsynchronization search (SYNC=0).

mode DAVA:(DAC1=0,DAC0=0)

Standard output mode: If the decoder issynchronized and a new block is received (every26 bits), the actual RDS/RBDS information of thelast two blocks is available with every newreceived block (approx. every 21.9ms).

mode DAVB:(DAC1=0,DAC0=1)

Fast PI search mode: During synchronizationsearch and if a new A or C’ block is received, theactual RDS/RBDS information of this or the lasttwo A or C’ blocks respectively is available withevery new received A or C’ block. If the decoderis synchronized, the "standard output mode" isactive.

mode DAVC:(DAC1=1,DAC0=0)

Reduced data request output mode: If thedecoder is synchronized and two new blocks arereceived (every 52 bits), the actual RDS/RBDSinformation of the last two blocks is available withevery two new received blocks (approx. every43.8ms).

mode DAVD:(DAC1=1,DAC0=1)

Decoder bypassed mode: If this mode is selectedthen the OutMux output of the decoder is reset tolow (OutMux=0). Then the internal row bufferoutput is active and the decoder is bypassed.This mode is not available in normal applicationmode.

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Data Output of RDS/RBDS InformationThe decoded RDS/RBDS block information and thecurrent decoder status should be available via the SFRs.For synchronization of data request betweenmicro-controller and decoder the additional data availableoutput (DAVN) is used for the interrupt. For DAVN timinginformation see next section.If the decoder has processed new information for themicro-controller the data available signal (DAVN) isactivated (low) under the following condition:-• During synchronization search in DAVB mode if a valid

A or C’ block has been detected. This mode can be usedfor fast search tuning (detection and comparison of thePI code contained in the A and C’ blocks.

• During synchronization search in any DAV mode exceptDAVD mode, if two blocks in the correct sequence havebeen detected (synchronization criterion fulfilled).

• If the decoder is synchronized and in mode DAVA andDAVB a new block has been processed. This mode isthe standard output mode, if the decoder issynchronized.

• If the decoder is synchronized and in DAVC mode twonew blocks have been processed.

• If the decoder is synchronized and in any DAV modeexcept DAVD mode loss of synchronization is detected(flywheel loss of synchronization, resulting in restart ofsynchronization search).

• In any DAV mode except DAVD mode, if a reset causedby power-on or voltage-drop is detected (PresN=0).

• Remark: If the decoder is synchronized, the DAVNsignal is always activated after 21.9ms in DAVA orDAVB mode and after 43.8ms in DAVC modeindependent of valid or invalid blocks are detected.

DAVN TimingThe processed RDS/RBDS data are available formicro-controller request for at least 20ms after the DAVNsignal was activated. The DAVN signal is alwaysautomatically de-activated (high) after ~ 10ms.

The decoder ignores new processed RDS/RBDS blocks ifthe DAVN signal is active (low).

Table 19 Data Available Signal (DAVN)

RDS SFRs

CONTROL REGISTER

The RDS has 4 input control registers to which can bewritten by the micro-controller via the MOVX.The RDS provides 3 different RDS/RBDS data outputprocessing modes plus one decoder module bypass modeselectable via the control registers DAC<1:0>.The NWSY control signal is to start new synchronizationprocess, if set to high. This bit of the control register is

Fig.21 DAVN LOW-time (decoder is synchronized)

SYMBOL PARAMETER Typical UNIT

tDVL data valid to DAVN LOW 2.0 us

tTDAV data valid period 21.9 ms

tDV data valid 21.9 ms

tDAVL data available signal is LOW 10.1 ms

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reset to low with a positive NWSYRe output pulsegenerated automatically by the decoder module.The maximum invalid blocks allowed duringsynchronization search (SYNC=0). If the first block neededfor synchronization has been found and the expectedsecond block (after 26 bits) is an invalid block, then thedecoder module internal_bad_blocks_counter isincremented and the next expected block is calculated;exception: if RBDS mode is selected and the first block isblock E, then the next expected block is always block A,until synchronization is found or the maximumbad_blocks_counter value is reached. If the decodermodule internal bad_blocks_counter reaches the value ofthe MBBG<4:0>, then immediately start of newsynchronization search (bit-by-bit) is started to find a newfirst block. The function of Max_Bad_Blocks_Gain isdisable if MAX_Bad_Blocks_Gain is set to zero. Only inthis case the 2 path synchronization search function isactivated.For error correction and identification of valid blocks duringsynchronization search as well as synchronization hold, 4different modes are selectable (SYM<1>, SYM<0>).MBBL<5:0> - Max_Bad_Blocks_Lose: maximum invalidblocks allowed while synchronized (SYNC=1). If thedecoder module internal bad_blocks_counter reaches thisvalue, then immediately start of “new synchronizationsearch” (bit-by-bit) is started (SYNC=0) and the internalbad_blocks_counter as well as the good_blocks_counteritself are reset to zero.MGBL<5:0> - Max_Good_Blocks_Lose: maximum validblocks required to clear the decoder module internalbad_blocks_counter. Only activated while synchronized(SYNC=1). If the decoder module internalgood_blocks_counter reaches this value, thenimmediately the bad_blocks_counter and thegood_blocks_counter itself are reset to zero.RBDS - If this bit set to high, then allow processing ofRBDS ‘E’ block. Otherwise, if set to low, it will enter RDSmode.

STATUS REGISTER

The RDS module has one status register.The output signal, SYNC, from decoder module indicatesthe synchronization found. It is set high, if synchronizationis found; otherwise reset to zero. The SYNC output signaldirectly effects the status register.RSTD is set to high, if a reset occurred, caused bypower-on reset or voltage drop. RSTD register is set bySRSTD signal output from decoder module. The RSTDstatus flag has to be cleared automatically after the statusregister was read by micro-controller. SRSTD is set to high(after power-on reset) for the first received 26 RDCL(from

demodulator module) clock pulses and has to be useddirectly as RSTD register-flag set signal.Last block identification number, LBIN<2:0> hold the blocknumber of the last processed RDS/RBDS data block. TheLBIN<2:0> are controlled by the output signals, BlNr<2:0>,of decoder module. The LBIN<2:0> registers has to beconnected to the inputs of the register(PBlN<2:0>) whichholds the previously processed block number. So ifRCopyE is set to high while DecWrE is active a copy fromthe last to the previously block number will be done.Error status of last block, ELB<1:0>, these registers arecontrolled by the output signals, EXB1 & EXB0. TheELB<1:0> holds the error status of the last processedRDS/RBDS data block. The output of these registers hasto be connected to the input of the register (EPB<1:0>)which holds the previously processed error status. So, ifRCopyE is set to high while DecWrE is active a copy fromthe last to the previously error status will be done.Bad block counter registers, BBC<5:0>, represent theactual bad_blocks_counter value.Good block counter registers, GBC<5:1>, represent theactual good_blocks_counter value.

RDS/RBDS DECODED DATA REGISTER

The decoder module has 4 output registers to put theprocessed/decoded RDS/RBDS block data. Theseregisters can be read by the micro-controller afterdetection of the RDS interrupt (DAVN=low).Last processed data, LDAT<15:0>, hold the parallel outputof the 16 bit from Data<15:0> decoder module output bus,which represents the information word of the lastprocessed RDS/RBDS data block. The output of thisregisters has to be connected to the input of the registerPDAT<15:0> which holds the previously processed blockdata. So if RCopyE is set to high while DecWrE is active acopy from the last to the previously block will be done.

DISPLAYThe display section is based on the requirements for aLevel 1.5 WST Teletext and US Closed Caption. There aresome enhancements for use with locally generatedOn-Screen Displays.The display section reads the contents of the Displaymemory and interprets the control/character codes. Usingthis information and other global settings, the displayproduces the required RGB signals and Video/Data (FastBlanking) signal for the TV signal processing.The display is synchronised to the TV signal processing byway of Horizontal and Vertical sync signals generatedwithin UOCIII. From these signals all display timings arederived.

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Display Features• Teletext and Enhanced OSD modes

• Level 1.5 WST features

• US Closed Caption Features

• 50Hz/60Hz display timing modes

• Two page operation for 16:9 screens

• Serial and Parallel Display Attributes

• Single/Double/Quadruple Width and Height forcharacters

• Smoothing capability of both Double Size, Double Width& Double Height characters

• Scrolling of display region

• Variable flash rate controlled by software

• Globally selectable scan lines per row 9/10/13/16/18.

• Globally selectable character matrix (HxV) 12x9/10,12x13, 12x16, 16x16 and 16x18

• Italics, Underline and Overline

• Soft Colours using CLUT with 4096 colour palette.

• Fringing (Shadow) selectable from N-S-E-W direction.

• Fringe colour selectable

• Contrast reduction of defined area is available in bothTXT and CC mode

• Double window

• Cursor

• Special Graphics characters with two planes, allowingfour colours per character

• 64 Software re-definable DRCs (DynamicallyRe-definable Characters), when it’s used as 4 colourmode for each pixel, the number of DRCs will be 32

• 4 WST Character sets(G0/G2) in single device (e.g.Latin, Cyrillic, Greek, Arabic)

• G1 Mosaic graphics, Limited G3 Line drawingcharacters

• WST Character sets and Closed Caption Character setin single device

• Panorama Mode, display 4:3 signals on 16:9 screen

• SCAVEM for Text

Display ModesThe display section has three distinct modes with differentfeatures available in each. The two modes are:• TXT:- This is the display configured as the WST mode

with additional serial and global attributes to enablethe same functionality as the SAA5497 (ETT)

device.The display is configured as a fixed 25 rowswith 40 characters per row.

• CC:- This is the display configured as the US ClosedCaption mode with the same functionality as thePC83C771 device. The display is configured as amaximum of 16 rows with a maximum of 48characters per row.

• OSD:-This is the display configured as either TXT or CCmode but without the restriction of display size orcharacter matrix.

There is an option of 10/13/16/18 lines per display row forCC style OSD mode, the characters used in these rowscan be either 12x13, 12x16, 12X18, 16X16, 16x18.In CC style OSD mode the number of rows and columnsavailable in limited by the maximum row value of 16, themaximum column value of 48 and the maximum number ofcharacter location of 624. This gives a full occupied displayof 16 rows by 39 columns for maximum rows, or 13 rowsby 48 columns for maximum columns.In TXT style OSD mode the maximum number of rows is25 and the maximum number of columns is 40, both ofthese limits can be achieved simultaneously.Note: Not all combinations of lines per row and maximumdisplay rows give a sensible OSD display, since there islimited number of TV scan lines available.Special Function Register, TXT21 and memory mappedregister are used to control the mode selection.

The following is a list of features available in each mode.Each setting can either be a serial or parallel attribute, andsome have a global effect on the display.

Feature TXT CC

Flash serial serial

Boxes TXT/OSD (Serial) serial

Horizontal Size x1/x2/x4 (serial) x1/x2 (serial)

Vertical Size x1/x2 (serial)x4 (global)

x1/x2 (serial)

Italic N/A serial

Foregroundcolours

8 (serial) 8+8 (parallel)

Backgroundcolours

8 (serial) 16 (serial)

Soft Colours(CLUT)

16 from 4096 16 from 4096

Table 20 Display Features

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CONFIDENTIAL

Display Feature Descriptions

FLASH

Flashing causes the foreground colour pixel to bedisplayed as the background pixels.The flash frequency iscontrolled by software setting and resetting displayregister REG0: Status at the appropriate interval.CC: This attribute is valid from the time set (see Table 27)until the end of the row or until otherwise modified.TXT: This attribute is set by the control character ‘flash’(08h) and remains valid until the end of the row or untilreset by the control character ‘steady’ (09h).

BOXES

CC: This attribute is valid from the time set until end of rowor otherwise modified if set with Serial Mode 0. If set withSerial Mode 1, then it is set from the next characteronwards.In CC text mode the background colour is displayedregardless of the setting of the box attribute bit. Boxes takeaffect only during mixed mode, where boxes are set in this

mode the background colour is displayed. Characterlocations where boxes are not set show video/screencolour (depending on the setting in the display controlregister. REG0: Display Control) in stead of thebackground colour.TXT: Two types of boxes exist the Teletext box and theOSD box. The Teletext box is activated by the ‘start box’control character (0Bh), Two start box characters arerequired begin a Teletext box, with box starting betweenthe 2 characters. The box ends at the end of the line orafter a ‘end box’ control character.TXT mode can also use OSD boxes, they are started usingsize implying OSD control characters(BCh/BDh/BEh/BFh). The box starts after the controlcharacter (‘set after’) and ends either at the end of the rowor at the next size implying OSD character (‘set at’). Theattributes flash, teletext box, conceal, separate graphics,twist and hold graphics are all reset at the start of an OSDbox, as they are at the start of the row. OSD Boxes are onlyvalid in TV mode which is defined by TXT5=03h andTXT6=03h.

SIZE

The size of the characters can be modified in both thehorizontal and vertical directions.CC: Two sizes are available in both the horizontal andvertical directions. The sizes available are normal (x1),double (x2) height/width and any combination of these.The attribute setting is always valid for the whole row.Mixing of sizes within a row is not possible.TXT: Three horizontal sizes are availablenormal(x1),double(x2),quadruple(x4). The controlcharacters ‘normal size’ (0Ch/BCh) enables normal size,the ‘double width’ or double size (0Eh/BEh/0Fh/BFh)enables double width characters. Any two consecutivecombination of ‘double width’ or ‘double size’(0Eh/BEh/0Fh/BFh) activates quadruple width characters,provided quadruple width characters are enabled byTXT4.Quad Width Enable.Three vertical sizes are available normal(x1), double(x2),quadruple(x4). The control characters ‘normal size’(0Ch/BCh) enable normal size, the ‘double height’ or‘double size’ (0Dh/BDh/0Fh/BFh) enable double heightcharacters. Quadruple height character are achieved byusing double height characters and setting the globalattributes TXT7.Double Height (expand) andTXT7.Bottom/Top.If double height characters are used in teletext mode,single height characters in the lower row of the doubleheight character are automatically disabled.

Underline N/A serial

Overline N/A serial

Fringe N+S+E+W N+S+E+W

Fringe Colour 16 (Global) 16 (Serial)

Smoothing YES (Global) YES (Global)

Fast BlankingPolarity

YES YES

Screen Colour 16 (Global) 16 (Global)

DRCS 64 (Global) 64 (Global)

Character Matrix(HxV)

12x9/10/13/16 12x9/10/13/16,16x16/18

No. of Rows 25 16

No. of Columns 40 48

No of Charactersdisplayable

1000 624

Cursor YES YES

Special Graphics(2 planes per

character)

32 32

Scroll NO YES

Feature TXT CC

Table 20 Display Features

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CONFIDENTIAL

ITALIC

CC: This attribute is valid from the time set until the end ofthe row or otherwise modified. The attribute causes thecharacter foreground pixels to be offset horizontally by 1pixel per 4 scan lines (interlaced mode). The base is thebottom left character matrix pixel. The pattern of thecharacter is indented as shown in Fig.22

Fig.22 Italic Characters

TXT: The Italic attribute is not available.

COLOURS

CLUT (Colour Look Up Table)A CLUT (Colour Look Up Table) with 16 colour entries isprovided. The colours are programmable out of a paletteof 4096(4 bits per R, G and B). The CLUT is defined by

writing data to a RAM that resides in the MOVX addressspace of the 80C51.

Italy Shift Scan LineIndented -2

by 10 -1Indented 0

by 9 1Indented 2

by 8 3Indented 4

by 7 5Indented 6

by 6 7Indented 8

by 5 9Indented 10

by 4 11Indented 12

by 3 13Indented 14

by 2 15Indented 16

by 1 17Indented 18

by 0 19

Pixels 02

46

810 12 14

0 2 4 6

Character Size 16 Wide x 18 High

0 2 4 6 8 10

Indented by 6/5/3

Indented by 5/4/2

Indented by 4/3/1

Indented by 3/2/0

Indented by 2/1

Indented by 1/0

Indented by 0

0 2 4 6 8 100 2 4 6 8 10 0 2 4 6 8 10 0 2 4 6 8 10 0 2 4 6 8 10

Indented by 7/6/40123456789

101112131415

12x16 character matrix 12x13 character matrix 12x10 character matrix

Field 1

Field 2

RED3-0b11. . .b4

GRN3-0b7. . .b4

BLU3-0b3. . .b0

Colourentry

0 0 0 0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 1 1 1 1 1

... ... ... ...

1 1 1 1 1 1 1 1 0 0 0 0 14

1 1 1 1 1 1 1 1 1 1 1 1 15

Table 21 CLUT Colour values

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The default value of the CLUT when entering TXT mode isgiven in the table below, this gives the required fullintensity teletext colours.

Foreground ColourCC: The foreground colour can be chosen from 8 colourson a character by character basis. Two sets of 8 coloursare provided. A serial attribute switches between thebanks (see Table 27 Serial Mode 1, bit 7). The colours arethe CLUT entries 0 to 7 or 8 to 15.TXT: The foreground colour is selected via a controlcharacter. The colour control characters takes effect at thestart of the next character (“Set-After”) and remain validuntil the end of the row, or until modified by a controlcharacter. Only 8 foreground colours are available.The TEXT foreground control characters map to the CLUTentries as shown below:

Background ColourCC: This attribute is valid from the time set until end of rowor otherwise modified if set with Serial Mode 0. If set with

Serial Mode 1, then the colour is set from the nextcharacter onwards.The background colour can be chosen from all 16 CLUTentries.TXT: The control character “New background” (“1Dh”) isused to change the background colour to the currentforeground colour. The selection is immediate (“Set at”)and remains valid until the end of the row or until otherwisemodified.The TEXT background control characters map to theCLUT entries as shown below:

BACKGROUND DURATION

The attribute when set takes effect from the currentposition until to the end of the text display defined inREG4:Text Area End.CC: The background duration attribute (see Table 27,Serial Mode 1, bit 8) in combination with the End Of Rowattribute (see Table 27, Serial Mode 1, bit 9) forces thebackground colour to be display on the row until the end ofthe text area is reached.TXT: This attribute is not available.

UNDERLINE

The underline attribute causes the characters to have thebottom scan line of the character cell forced to foregroundcolour, including spaces. If background duration is set,then underline is set until the end of the text area.CC: The underline attribute (see Table 27, Serial Mode0/1, bit 4) is valid from the time set until end of row orotherwise modified.TXT: This attribute is not available.

OVERLINE

The overline attribute causes the characters to have thetop scan line of the character cell forced to foregroundcolour, including spaces. If background duration is set,then overline is set until the end of the text area.

CLUTAddress Default<11:0>

Full IntensityEquivalent(Foreground)

CLUTAddress Default<11:0>

Full IntensityEquivalent(Background)

0 000000000000 Black 8 000000000000 Black

1 111100000000 Red 9 111100000000 Red

2 000011110000 Green A 000011110000 Green

3 111111110000 Yellow B 111111110000 Yellow

4 000000001111 Blue C 000000001111 Blue

5 111100001111 Magenta D 111100001111 Magenta

6 000011111111 Cyan E 000011111111 Cyan

7 111111111111 White F 111111111111 White

Table 22TXT Default CLUT map

Control Code Defined Colour CLUT Entry

00h Black 0

01h Red 1

02h Green 2

03h Yellow 3

04h Blue 4

05h Magenta 5

06h Cyan 6

07h White 7

Table 23 Foreground CLUT mapping

Control Code Defined Colour CLUT Entry

00h+1Dh Black 8

01h+1Dh Red 9

02h+1Dh Green 10

03h+1Dh Yellow 11

04h+1Dh Blue 12

05h+1Dh Magenta 13

06h+1Dh Cyan 14

07h+1Dh White 15

Table 24 Background CLUT mapping

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CC: The overline attribute (see Table 27, Serial Mode 0/1,bit 5) is valid from the time set until end of row or otherwisemodified. Overlining of Italic characters is not possible.TXT: This attribute is not available.

END OF ROW

CC: The number of characters in a row is flexible and candetermined by the end of row attribute (see Table 27,Serial Mode 1, bit 9). However the maximum number ofcharacter positions displayed is determined by the settingof the REG2:Text Position Horizontal and REG4:Text AreaEnd.NOTE: When using the end of row attribute the nextcharacter location after the attribute should always beoccupied by a ’space’.TXT: This attribute is not available, Row length is fixed at40 characters.

FRINGING

A fringe (shadow) can be defined around characters. Thefringe direction is individually selectable in any of theNorth, South, East and West direction usingREG3:Fringing Control. The colour of the fringe can alsobe defined as one of the entries in the CLUT, again usingREG3:Fringing Control.CC: The fringe attribute (see Table 27, Serial Mode 0, bit9) is valid from the time set until the end of the row orotherwise modified.TXT: The display of fringing in TXT mode is controlled bythe TXT4.SHADOW bit. When set all the alphanumericcharacters being displayed are shadowed, graphicscharacters are not shadowed.

Fig.23 South and Southwest Fringing

CURSOR

The cursor operates by reversing the background andforeground colours in the character position pointed to bythe active cursor position. The cursor is enabled usingTXT7.CURSOR ON. When active, the row the cursorappears on is defined by TXT9.R<4:0> and the column is

defined by TXT10.C<5:0>. The position of the cursor canbe fixed using TXT9.CURSOR FREEZE.CC: The valid range for row is 0 to 15. The valid range forcolumn is 0 to 47. The cursor remains rectangular at alltimes, it’s shape is not affected by italic attribute, thereforeit is not advised to use the cursor with italic characters.TXT: The valid range for row positioning is 0 to 24.Thevalid range for column is 0 to 39.

SPECIAL GRAPHICS CHARACTERS

-Normal Special Graphics characterMode(TXT20.Extended special graphics = 0)CC/TXT: Several special characters are provided forimproved OSD special effects. These characters provide achoice of 4 colours within a character cell. Addressing istherefore done using only the even character addresses.The total number of special graphics characters is limitedto max. 32 when Extended Special Graphics is notenabled. They are stored in the character codes 8Xh, 9Xhof the character table (32 ROM characters), or in the DRCswhich overlay character codes 8Xh, 9Xh, AXh and CXh (ifExtended DRC is enabled). Each special graphicscharacter uses two consecutive normal characters. Thepixel planes are stored in adjacent characters, alwaysstarting with an even character. Special graphicscharacters are activated whenTXT20/TXT29.OSD_PLANE = 1.

-Extended Special Graphics characterMode(TXT20.Extended special graphics = 1)CC:- When "TXT20.Extended special graphics" isenabled, all characters from the ROM can be used asspecial graphics characters in this mode. Each specialgraphics character uses two consecutive characters fromthe normal Character Set. Closed Caption character codebit-14 enables display of special graphics on a characterby character basis.

note: Special Graphics capability extended to anycharacter only in Closed_Caption Mode

Four-colour on-screen display characters can be createdin closed caption and teletext style sets, provided they areeither 12x13 or 16x16 or16x18 characters. Four-colourcharacters are generated by overlaying two consecutive

A B C D E FFig.24 Cursor Display

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CONFIDENTIAL

two-colour characters. For example see following figure.The two characters on the left could overlap to produce thefour-colour character on the right. For the characterdefinition the black would represent a 1 and the whitewould represent a 0. Four-colour characters can easily bedefined using the DDS tool. The character is defined on apixel-by-pixel basis, after checking four colours option.

The colours here have been used for the example. Fourcolours are achieved by using the foreground and thebackground colours, for example CLUT entries 0 and 1,and the default (for four-colour characters) CLUT entries 6and 7. In your application software you will need to definethe CLUT Table entries to obtain the colours that yourequire and the foreground and the background colours.

Table 25 Special Character Colour allocation

.

The example in Fig.25 can be done with 8 special graphicscharacters.

SmoothingSmoothing is available in both TXT and CC modes and isactivated using MMR 87E4<5:4>. The clarity of Double

Height, Double Width and Double Size Characters are allimproved when smoothing is enabled.

Character and Attribute Coding

CC MODE

Character coding is split into character oriented attributes(parallel) and character group coding (serial). The serialattributes take effect either at the position of the attribute(Set At), or at the following location (Set After) and remaineffective until either modified by a new serial attribute oruntil the end of the row. A serial attribute is represented asa space (the space character itself however is not used forthis purpose), the attributes that are still active, e.g.overline and underline will be visible during the display ofthe space. The default setting at the start of a row is:• 1x size, flash and italics OFF

• overline and underline OFF

• Display mode = superimpose

• fringing OFF

• background colour duration = 0

• end of row = 0

The coding is done in 15 bit words. The codes are storedsequentially in the display memory. A maximum of 768character positions can be defined for a single display.

PARALLEL CHARACTER CODING

Plane 1 Plane 0 Colour Colour Allocation

0 0 Blue Background Colour

0 1 White Foreground Colour

1 0 Red CLUT Entry 6 or 14 depending onthe set bank

1 1 Green CLUT Entry 7 or 15 depending onthe set bank

VOLUME

Background Colour

Foreground Colour 7

Background Colour Serial Attribute“set at” (Mode 0)

Background Colour“set after” (Mode 1)

Foreground ColourNormal Character

Foreground Colour 6

Special Character

Fig.25 Special Character Example

Bits Description

0-7 8 bit character code

8-10 3 bits for 8 foreground colours

11 Mode bit:

0 = Parallel code

12-13 Character Select Selection:

00 = Character Set 0




14 Character Definition:

0 = Single Plane Character

1 = Two Plane Character (four colour)

Table 26 Parallel Character Coding

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CONFIDENTIAL

SERIAL CHARACTER CODING

Table 27 Serial Character Coding

Character ROM Selection in CC Mode

Bits 12/13 of the parallel character coding are used toselect the character set on character by character basis. InCC Mode only, bits 13 and 12 of character code can

Bits Description

Serial Mode 0

(“set at”)

Serial Mode 1

Char.Pos. 1 (“set at”) Char.Pos.>1 (“set after”)

0-3 4 bits for 16 Backgroundcolours

4 bits for 16 Background colours 4 bits for 16 Background colours

4 0 = Underline OFF1 = Underline ON

Horizontal Size:0 = normal1 = x2

0 = Underline OFF1 = Underline ON

5 0 = Overline OFF1 = Overline ON

Vertical Size:0 = normal1 = x2

0 = Overline OFF1 = Overline ON

6 Display mode:0 = Superimpose1 = Boxing

Display mode:0 = Superimpose1 = Boxing

Display mode:0 = Superimpose1 = Boxing

7 0 = Flash OFF1 = Flash ON

Foreground colour switch0 = Bank 0 (colours 0-7)1 = Bank 1 (colours 8-15)

Foreground colour switch0 = Bank 0 (colours 0-7)1 = Bank 1 (colours 8-15)

8 0 = Italics OFF1 = Italics ON

Background colour duration:0 = stop BGC1 = set BGC to end of row

Background colour duration(set at):0 = stop BGC1 = set BGC to end of row

9 0 = Fringing OFF1 = Fringing ON

End of Row0 = Continue Row1 = End Row

End of Row (set at):0 = Continue Row1 = End Row

10 Switch for Serial codingmode 0 and 1:

0 = mode 0

Switch for Serial coding mode 0and 1:

1 = mode 1

Switch for Serial coding mode 0and 1:

1 = mode 1

11 Mode bit:

1 = Serial code

Mode bit:

1 = Serial code

Mode bit:

1 = Serial code

12 0 = Cont. Red. OFF1 = Cont. Red. ON

0 = Cont. Red. OFF1 = Cont. Red. ON

0 = Cont. Red. OFF1 = Cont. Red. ON

2003 Nov 11 81



CONFIDENTIAL

control the character set selection when TXT20<4> is set.When TXT20<4> is reset to ’0’ the normal BS<1:0>bits(TXT18<1:0>) control character set selection as forText mode.

In table 28 shows the character set selection. Although thehardware allow to select from 4 character sets, due to theDDS tool limitation the Set 0 is only for teletext.

Serial mode 0Serial mode 0 means that these attributes are valid fromthe time set until the end of the row or until otherwisemodified. This differs from serial mode 1, where they arevalid from the next character onwards.

Serial mode 1Serial mode 1 means that these attributes are valid fromthe character following the character code until the end ofthe row or until otherwise modified. This differs from serialmode 0 where they are also valid for the character codeitself. However, for the first character of each line, serialmode 1 behaves differently.When a serial mode 1 character code is set in position 1 ofa line, attributes are valid from the time set as in mode 0.There is also a different set of attributes. All but two ofthese attributes are the same as for the rest of the line. Thetwo different attributes are horizontal and vertical size, bits4 and 5 respectively. These replace Underline andOverline.

Contrast Reduction in CC ModeWhen bit 12 of the serial character coding is set, thisgenerates a contrast reduction box. By setting TXT5 bits 5and 4, contrast reduction can be enabled inside, oroutside, these boxes. When contrast reduction is active,the cont_red output signal is set low. The cont_red signalis always synchronized with VDS. With regard tointeraction with other features, the contrast reduction

attribute will behave in exactly the same fashion as thebackground colour attribute.The actual contrast reduction is carried out in the VideoSignal Processor die and is simply switched in and out bythe cont_red signal from TCG micro-controller. The effectof contrast reduction is to reduce the brightness andcontrast of the video image behind the OSD. For thisreason, contrast reduction is only visible in mixed screenmode with superimposed text.

TXT MODE

Character coding is in a serial format, with only oneattributes being changed at any single location. The serialattributes take effect either at the position of the attribute(Set At), or at the following location (Set After). Theattribute remains effective until either modified by newserial attributes or until the end of the row.The defaultsettings at the start of a row is:• foreground colour white (CLUT Address 7)

• background colour black (CLUT Address 8)

• Horizontal size x1, Vertical size x1 (normal size)

• Alphanumeric ON

• Contiguous Mosaic Graphics

• Release Mosaics

• Flash, Box, Conceal and Twist OFF

The attributes have individual codes which are defined inthe basic character table below:

CC ModeChar code<13:12>

characterSet

ExampleLanguage

00 Set 0 Latin

01 Set 1 Greek

10 Set 2 Cyrillic

11 Set 3 Arabic

Table 28 Character Set Selection

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CONFIDENTIAL

Fig.26 TXT Basic Character Set (Pan-European)

0123456789ABCDEF

0 1 2 3 4 5 6 7a 8 8a A B C2a 3a 6a 70 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

alphablackalpharedalphagreenalphayellowalphabluealphamagentaalphacyanalphawhite

graphicsredgraphicsgreengraphicsyellowgraphicsbluegraphicsmagentagraphicscyangraphicswhite

flash

steady

endboxstartboxnormalheightdoubleheightdoublewidthdoublesize

concealdisplaycontiguousgraphicsseparatedgraphics

blackbkgndnewbkgndholdgraphicsreleasegraphics

bkgndblackbkgndredbkgndgreenbkgndyellowbkgndbluebkgndmagentabkgndcyanbkgndwhite

norm szOSDdbl htOSDdbl wdOSDdbl szOSD

columnrow

bits

b7b6

b5b4

b3 b2 b1 b0

graphicsblack

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

D E F00

00

1000

0100

1100

0110

1110

0010

1010

0101

1101

0011

1011

0111

1111

D E F10

11

0111

1111

E/W = 0 E/W = 1

NatOpt

NatOpt

NatOpt

NatOpt

NatOpt

NatOpt

NatOpt

NatOpt

NatOpt

NatOpt

NatOpt

NatOpt

NatOpt

O S D

O S D

O S D

O S D

O S D

O S D

O S D

O S D

O S D

O S D

O S D

O S D

O S D

O S D

O S D

O S D

O S D

O S D

O S D

O S D

O S D

O S D

O S D

O S D

O S D

O S D

O S D

O S D

O S D

O S D

O S D

O S D

9a

O S D

O S D

O S D

O S D

O S D

O S D

O S D

O S D

O S D

O S D

O S D

O S D

O S D

O S D

O S D

O S D

9

O S D

O S D

O S D

O S D

O S D

O S D

O S D

O S D

O S D

O S D

O S D

O S D

O S D

O S D

O S D

O S D

1001

0001

twist

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CONFIDENTIAL

Screen and Global ControlsA number of attributes are available that affect the wholedisplay region, and cannot be applied selectively toregions of the display.

TV SCAN LINES PER ROWThe number of TV scan lines per field used for eachdisplay row can be defined, the value is independent of thecharacter size being used. The number of lines can beeither 10/13/16 per display row. The number of TV scanlines per row is defined TXT21.DISP_LINES<1:0>.A value of 9 lines per row can be achieved if the display isforced into 525 line display mode byTXT17.DISP_FORCE<1:0>, or if the device is in 10 linemode and the automatic detection circuitry within displayfinds 525 line display syncs.

CHARACTER MATRIX (HXV)There are five different character matrices available, theseare 12x13, 12x16, 16x16 and 16x18. The selection ismade using TXT21.CHAR_SIZE<1:0> and is independentof the number of display lines per row.If the character matrix is less than the number of TV scanlines per row then the matrix is padded with blank lines. Ifthe character matrix is greater than the number of TV scanlines then the character is truncated.

Display ModesCC: When attributes superimpose or when boxing (seeTable 27, Serial Mode 0/1, bit 6) is set, the resulting displaydepends on the setting of the following screen controlmode bits in REG0:Display Control.

Table 29 Display Modes

TXT: The display mode is controlled by the bits in the TXT5and TXT6. There are 3 control functions - Text on,Background on and Picture on. Separate sets of bits areused inside and outside Teletext boxes so that differentdisplay modes can be invoked. TXT6 is used if thenewsflash (C5) or subtitle (C6) bits in row 25 of the basicpage memory are set otherwise TXT5 is used. This allowsthe software to set up the type of display required onnewsflash and subtitle pages (e.g. text inside boxes, TVpicture outside) this will be invoked without any furthersoftware intervention when such a page is acquired.

Display Mode MOD<1 0>

Description

Video 0 0 Video mode disables all displayactivities and sets the RGB to trueblack and VDS to video.

Full Text 0 1 Full Text mode displays screencolour at all locations not covered bycharacter foreground or backgroundcolour. The box attribute has noeffect.

Mixed ScreenColour

1 0 Mixed Screen mode displays screencolour at all locations not covered bycharacter foreground, within boxedareas or, background colour.

Mixed Video 1 1 Mixed Video mode displays video atall locations not covered bycharacter foreground, within boxedareas or, background colour.

Picture On Text OnBackground

OnEffect

0 0 x Text mode, black screen

0 1 0 Text mode, background always black

0 1 1 Text mode

1 0 x Video mode

1 1 0 Mixed text and TV mode

1 1 1 Text mode, TV picture outside text area

Table 30 TXT Display Control Bits

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CONFIDENTIAL

Screen ColourScreen colour is displayed from 10.5 us to 62.5 us after theactive edge of the HSync input and on TV lines 23 to 310inclusive, for a 625 line display, and lines 17 to 260inclusive for a 525 line display.The screen colour is defined by REG0:Display Control andpoints to a location in the CLUT table. The screen colourcovers the full video width. It is visible when the Full Textor Mixed Screen Colour mode is set and no foreground orbackground pixels are being displayed.

Text Display Controls

TEXT DISPLAY CONFIGURATION

Two types of area are possible. The one area is static andthe other is dynamic. The dynamic area allows scrolling ofa region to take place. The areas cannot cross each other.Only one scroll region is possible.

Display MapThe display map allows a flexible allocation of data in thememory to individual rows.Sixteen words are provided in the display memory for thispurpose. The lower 10 bits address the first word in thememory where the row data starts. This value is an offsetin terms of 16-bit words from the start of Display Memory(8000 Hex). The most significant bit enables the displaywhen not within the scroll (dynamic) area.The display map memory is fixed at the first 16 words inthe closed caption display memory.

SOFT SCROLL ACTION

The dynamic scroll region is defined by the REG5:ScrollArea, REG6:Scroll Range, REG14:Top Scroll line and theREG8:Status Register. The scroll area is enabled whenthe SCON bit is set in REG8: Status.The position of the soft scroll area window is defined usingthe Soft Scroll Position (SSP<3:0), and the height of thewindow is defined using the Soft Scroll Height (SSH<3:0>)both are in REG6:Scroll Range. The rows that are scrolledthrough the window are defined using the Start Scroll Row(STS<3:0>) and the Stop Scroll Row (SPS<3:0>) both arein REG5:Scroll Area.The soft scrolling function is done by modifying the ScrollLine (SCL<3:0>) in REG14: Top Scroll Line. and the firstscroll row value SCR<3:0> in REG8:Status. If the numberof rows allocated to the scroll counter is larger than thedefined visible scroll area, this allows parts of rows at thetop and bottom to be displayed during the scroll function.The registers can be written throughout the field and thevalues are updated for display with the next field sync.Care should be taken that the register pairs are written toby the software in the same field.Only a region that contains only single height rows or onlydouble height rows can be scrolled.

b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

Pointer to Row Data

Reserved, should be set to 0

Text Display Enable, valid outside Soft Scroll Area0 = Disable1 = Enable

Table 31 Display map Bit Allocation

Display Memory Text AreaROW

123456789101112131415

0123456789101112131415

0

Dis

play

Map

Ent

ries

Dis

play

Dat

a

Ena

ble

bit =

0

Displaypossible

Displaypossible

Soft Scrollingdisplay possible

Fig.27 Display Map and Data Pointers

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CONFIDENTIAL

ROW

123456789101112131415

0

Soft Scroll PositionPointer SSP<3:0> e.g. 6

Soft Scroll HeightSSH<3:0> e.g.4

Start Scroll Row

Stop Scroll Row

Usable for OSD Display

Should not be used for

Should not be used for

Usable for OSD Display

Soft Scrolling Area

OSD Display

OSD Display

STS<3:0> e.g. 3

SPS<3:0> e.g. 11

Fig.28 Soft Scroll Area

Closed Captioning data row nClosed Captioning data row n+1Closed Captioning data row n+2Closed Captioning data row n+3Closed Captioning data row n+4

ROW

123456789101112131415

0

P01 NBC

0-63 lines

Visible areafor scrolling

Scroll AreaOffset

row1row0

row2row3row4row5row6row7row8

row13row14

Fig.29 CC Text Areas

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Two Page DisplayThis mode enables two different pages to be displayedside by side for use with 16:9 TV Screens. Fig.30 showsthe possible combinations for two page display. The facilityis restricted to 1H/1V. Two page mode is selected using Bit

0 of Display Configuration register 87FF. Two characterspaces are required between the pages to allow thedisplay logic to switch correctly.

Text

Screen Colour Area

Text

OSDText

Screen Colour Area

Text

Subtitle

Text

Screen Colour Area

Video Text

Screen Colour Area

Text

Screen Colour Area

Video CC

Screen Colour Area

VideoCC

OSD

Screen Colour Area Screen Colour Area

TextCC

OSD

CC

OSDText

Fig.30 Two Page TXT/CC/Video Combination

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Two CC_TXT mode control bits exist in two page mode,TXT21<0> controls Text Area A and TXT31<6> (CC_TXTB) controls Text Area B.TXT:-When displaying two teletext pages side by side, Text AreaA display is selected using the Page A<3:0> registerTXT14<3:0> and Text Area B is selected using the PageB<3:0> register TXT28<3:0>. The rolling header and timeinformation written by Acquisition will only apply to theactive page.Active Page Operation:i) When reset to logic ’0’ (default value), acquisition writesthe header and time information to Text Area A. When setto logic ’1’, acquisition writes the header and timeinformation to Text Area B.ii) The display uses the Active Page bit to direct whichpage (’0’ = Text Area A, ’1’ = Text Area B) to allowoperation of the Reveal bit, TXT7<5>, and Cursor,TXT7<6>. The Expand mode is controlled individually oneach page.CC:- When CC display mode is selected in two page modeonly one screen half may be used for CC/OSD and theother either Text or Video. Two page CC display side byside is not possible due to CC display RAM limitation (only1 block RAM for CC).To allow some flexibility in 2 page mode the DRCS Enablebit is duplicated for the second page into TXT23<2>. Thisallows two Text OSD pages, displayed in 2 page mode, touse Character Rom OSD in one page and DRCS in theother.

Character Set SelectionIndividual control of the Basic Character Set / TwistCharacter Set and National Option Table are possibleusing TXT18, TXT19, TXT23 and TXT29. The East/Westbit TXT4<5> will apply to both pages.

BoxesThe teletext mode control registers (TXT5 & TXT6) areduplicated (TXT24 & TXT25) so that, for example, a textpage can be displayed on one side and a subtitled page.

Display AttributesSeparate control of Fringing, Screen colour andTransparent mode is required for each Text Area.Fringing : Control of which page has fringing is controlledby TXT4<0> for Text Area A and TXT26<3> for Text AreaB. The fringe colour and direction applies to both pages i.e.Fringing Control MMR 87F3.Trans : The facility to display Black background astransparent is controlled by TXT4<1> for Text Area A andTXT26<6> for Text Area B.

Screen Colour : Only the Screen colour definition for Textis required to be duplicated since only 1 CC page ispossible on a side with video on the other. The TextScreen Colour register Txt17<2:0> applies to Text area Aand Txt27<2:0> shall determine Screen Colour in TextArea B.

Double WindowIn this mode, the video picture will display in the left half ofthe screen, the other half is for Text. The control bit isenabled in SFR Video_process.DW_PA<1:0>=”01”enables double window functionality.

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PanoramaLinear and non-linear horizontal scaling circuit for aspectratio conversion 4:3 video signal to 16:9 screen arecontrolled by SFR Video_process.DW_PA<1:0>.

Table 32 DW and Panorama Scaling Modes

Text

DW=0, two-page=1

Text

DW=1, two-page=1

DW=0, without Text, two-page=0

Text

DW=0, with Text, two-page=0

Fig.31 Double Window Feature

DW_PA<1:0> Modes

00 Normal mode, both DW and Panorama modeare disable.

01 Double Window Mode Enable

10 Enable linear scaling for 4:3 video signaldisplaying on 16:9 screen.

11 Enable non-linear scaling for 4:3 video signaldisplaying on 16:9 screen

4:3 video signal

linear scaling

non-linear scaling

Fig.32 4:3 Video Signal Scaling to 16:9 Screen

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Display Positioning (Single Page)The display consists of the Screen Colour covering thewhole screen and the Text Area that is placed within thevisible screen area. The screen colour extends over a

large vertical and horizontal range so that no offset isneeded. The text area is offset in both directions relative tothe vertical and horizontal sync pulses.

Display Positioning (Two Page)The display consists of the two Screen Colours coveringeach half of the screen and two Text Areas that are placedwithin the visible screen area. The screen colour extendsover a large vertical and horizontal range so that no offsetis needed. The both text areas are offset in both directionsrelative to the vertical and horizontal sync pulses. Thesecond page may be positioned relative to HSYNC delayusing the Page B Position MMR, active to the vertical andhorizontal sync pulses. The second page may bepositioned relative to HSYNC delay using the Page BPosition MMR.

Horizontal Sync.Vertical

Text Area

Screen Colour Area

Text Area Start

49.78µs

Sync.

0.25 char. offsetText Area End

Screen Colour Offset = 7.11µs

TextVerticalOffset

6 LinesOffset

H-Sync delay

Fig.33 Display Area Positioning (Single Page)

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The visible text area for Page A is controlled using theTEXT AREA START and TEXT AREA END MMRs. PageB visible text area is controlled using the TEXT AREASTART B and TEXT AREA END B MMRs.

Horizontal Sync.Vertical

Text

Screen Colour Area

Text Area

49.78µs

Sync.

0.25 char. offset

Text Area

Screen Colour Offset = 7.11µs

TextVerticalOffset

6 LinesOffset

H-Sync delay

AreaA

Text

AreaB

Text Area End A Text Area

Min.2 Char.Spaces

Start B

End B

Start A

Page B Start

0.25 char. offset

Fig.34 Display Area Positioning (Two Page)

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CONFIDENTIAL

SCREEN COLOUR DISPLAY AREA

This area is covered by the screen colour. The screencolour display area starts with a fixed offset of 8 us fromthe leading edge of the horizontal sync pulse in thehorizontal direction. A vertical offset is not necessary.

TEXT DISPLAY AREA (SINGLE PAGE)The text area can be defined to start with an offset in boththe horizontal and vertical direction.

The horizontal offset is set in REG2: Text Area Start. Theoffset is done in full width characters using TAS<5:0> andquarter characters using HOP<1:0> for fine setting. Thevalues 00h to 03h for TAS<5:0> will result in a corrupteddisplay.The width of the text area is defined in REG4:Text AreaEnd by setting the end character value TAE<5:0>. Thisnumber determines where the background colour of theText Area will end if set to extend to the end of the row. Itwill also terminate the character fetch process thuseliminating the necessity of a row end attribute. Thisentails however writing to all positions.The vertical offset is set in REG1:Text Position VerticalRegister. The offset value VOL<5:0> is done in number ofTV scan lines.NOTE: REG1:Text Position Vertical Register should notbe set to 00 Hex as the Display Busy interrupt is notgenerated in these circumstances.

TEXT DISPLAY AREA (TWO PAGE)Control of Page A in two page mode is as per the controlin single page mode.

Three extra memory mapped registers control the positionof the second page: REG17: Text Area Start B, REG18:Text Area End B and REG19: Page B Position.Page B positioning register controls the positioning of TextArea B relative to HSYNC delay. A minimum two charactergap should be allowed between each page to allow thereset of attributes.Control of the vertical offset is as per single page operationusing REG1: Text Position Vertical Register.The text area can be defined to start with an offset in thehorizontal direction as follows:

Table 35 Text Display Area B

The horizontal offset is set in REG17: Text Area Start. Theoffset is done in full width characters using TAS B<5:0>and quarter characters using HOP B<1:0> for fine setting.The values 00h to 03h for TAS<5:0> will result in acorrupted display.The width of the text area is defined in REG18: Text AreaEnd by setting the end character value TAE B<5:0>. Thisnumber determines where the background colour of theText Area B will end if set to extend to the end of the row.It will also terminate the character fetch process thuseliminating the necessity of a row end attribute. Thisentails however writing to all positions.

Character SetTo facilitate the global nature of the device the characterset has the ability to accommodate a large number ofcharacters, which can be stored in different matrices.

CHARACTER MATRICES

The character matrices that can be accommodated are: -(HxVxPlanes) 12x9x1, 12x13x1, 12x16x1, 16x16x1 and16x18x1. These modes allow two colours per characterposition.In CC mode four additional character matrices areavailable to allow four colours per character: -(HxVxPlanes) 12x13x2, 12x16x2, 16x16x2 and 16x18x2.The characters are stored physically in ROM in a matrix ofsize either 12x16, 16x18.

CHARACTER SET SELECTION

Four character sets are available in the device. A set canconsist of alphanumeric characters as required by theWST Teletext or FCC Closed Captioning, Customer

Horizontal starts 7.11us after the leading edge of H-Sync for49.78 us.

Vertical line 9, field 1 (321, field 2) with respect to leadingedge of vertical sync (line numbering using 625Standard).

Table 33 Screen Colour Display Area

Horizontal Up to 48 full sized characters per row.Start position setting from 3 to 64 characters fromthe leading edge of H-Sync. Fine adjustment inquarter characters.

Vertical 256 lines (nominal 41- 297).Start position setting from leading edge of verticalsync legal values are 4 to 64 lines.(line numbering using 625 Standard)

Table 34 Text Display Area

Horizontal Up to 48 full sized characters per row.Start position setting from 3 to 128 characters fromthe leading edge of H-Sync. Fine adjustment inquarter characters.

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CONFIDENTIAL

definable On-Screen Display characters, and SpecialGraphic characters.CC:- Two control mechanism are available controlledusing TXT20<4>.When Char Select Enable is set inactive (TXT20<4>):Only a single character set can be used for display and thisis selected using the Basic Set selection TXT18.BS<1:0>.When selecting a character set in CC mode the Twist Setselection TXT19.TS<1:0> should be set to the same valueas TXT18.BS<1:0> for correct operation.When Char Select Enable is set active (TXT20<4>):The Character Set is selected using the Display Charactercode (Bit-12 & Bit-13) on a character by character basis.Selection is as per the basic character set selection(TXT18.BS<1:0>).TXT:- Two character sets can be displayed at once. Theseare the basic G0 set or the alternative G0 set (Twist Set).The basic set is selected using TXT18.BS<1:0>, Thealternative/twist character set is defined byTXT19.TS<1:0>. Since the alternative character set is anoption it can be enabled or disabled using TXT19.TEN,and the language code that is defined for the alternativeset is defined by TXT19.TC<2:0>.The National option table is selected usingTXT18.NOT<3:0>. A maximum of 32 National Optiontables can be defined when combined with the E/W controlbit (TXT4 Bit-5).An example of the character set selection and definitionsis shown in Table 36

Table 36 Character Set Selection

ROM ADDRESSING

Three ROM’s are used to generate the correct pixelinformation. The first contains the National Option look-uptable, the second contains the Basic Character look-uptable and the third contains the Character Pixelinformation. Although these are individual ROM, sincethey do not need to be accessed simultaneously they areall combined into a single ROM unit.

Although the hardware implement of character setselection of Closed Caption can select one of the four sets,but due to the DDS tool restrictive, the Look-Up Set 0 is forTeletext only; the Look-Up Set1, Set2 and Set3 are forClosed Caption and Teletext depend on S/W setting.

S<1:0>/TS<1:0> CharacterSet

Example Language

00 Set 0 Latin

01 Set 1 Greek

10 Set 2 Cyrillic

11 Set 3 Closed Caption

CHAR PIXELDATA

LOOK-UPBasic + Nat Opt

0000H

0800H

4000H

2048 location

14 x 16 bits

Look-Up Set 0

Look-Up Set1

Look-Up Set2

Look-Up Set3

0000

0200

0400

0600

0800

Fig.35 ROM Organization

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CONFIDENTIAL

CHARACTER TABLE

The character table is shown in Table 37:-

Re-definable CharactersA number of Dynamically Redefinable Characters (DRC)are available. These are mapped onto the normalcharacter codes, and replace the predefined ROM value.

-Normal DRC Mode(TXT26.EXTENDED DRCS = 0):There are 32 DRC’s, the first 16 occupy the charactercodes 80Hto 8FH, the second 16 occupy the locations 90Hto 9FH. This allows for 32 DRC’s in TXT mode, 32 DRC’sin CC mode and 32 Normal or 16 Special DRC’s in OSDmode.The remapping of the standard OSD to the DRC’s isactivated when the TXT20.DRCS ENABLE<7> for Page A,or TXT23.DRCS ENABLE<2> for Page B bit is set. Theselection of Normal or Special OSD symbols is defined bythe TXT20.OSD PLANES<6> for Page A, TXT29.OSDPLANES<4> for Page B.

-Extended DRC Mode(TXT26.EXTENDED DRCS = 1):Extra character codes (column A/C) will be used as DRCcharacters, thus there are max. 64 DRC’s.Each character is stored in a matrix of 16x18x1 (H x Vxplanes), this allows for all possible character matrices.

Character code columns (Bits 4-7)

0 1 2 3 4 5 6 7 8 9 A B C D E F

Cha

ract

er c

ode

row

s (B

its 0

-3)

0 ® SP 0 @ P ú p

1 ˚ ! 1 A Q a q

2 1/2 " 2 B R b r

3 ¿ # 3 C S c s

4 ™ $ 4 D T d t

5 ¢ % 5 E U e u

6 £ & 6 F V f v

7 ´ 7 G W g w

8 à ( 8 H X h x

9 _ ) 9 I Y i y

A è á : J Z j z

B â + ; K [ k ç

C ê , < L é l

D î - = M ] m Ñ

E ô . > N í n ñ

F û / ? O ó o n

Table 37 Closed Caption Character Table

Special Characters are in column 8 & 9.

Additional table locations for normal characters

Table locations for normal characters

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CONFIDENTIAL

DEFINING CHARACTERS

The DRC RAM is mapped into the 80C51 RAM addressspace and starts at location 8800H. The character matrixis 16 bits wide and therefore requires two bytes to bewritten for each word, the first byte (even addresses)addresses the lower 8 bits and the second byte (oddaddresses) addresses the upper 8 bits.For characters of 9, 10, 16 or 18 lines high the pixelinformation starts in the first address and continuessequentially for the required number of address.Characters of 13 lines high are slightly different to theothers as they have the added feature of fringing acrossrow boundaries. This is not normally possible, but can beachieved by programming a copy of the bottom line of thecharacter above and the top line of the character belowwithin the DRCS character definition. This technique isespecially useful for clustered characters.

With the addition of the larger 18 line high characters, thisfeature of fringing across clustered characters is no longeressential. For DRCS, however, this feature has beenretained for backward compatibility. It should be noted that13 line ROM characters are no longer coded in this way.The required character is defined with an initial offset of 1address with the bottom line of the character above copiedinto the very first address (line 0). The top line of thecharacter below is copied below the character definition(line 14), see Fig.37. Only lines 1 to 13 are actuallydisplayed. Lines 0 and 14 are only read by the fringinggenerator.To allow some flexibility in 2 page mode the DRCS Enablebit is duplicated for the second page into TXT23<2>.Thisshall allow two Text OSD pages, displayed in 2 pagemode, to use Character ROM OSD in one page and DRCSin the other.

Display SynchronizationThe horizontal and vertical synchronizing signals from theTV deflection are used as inputs. Both signals can beinverted before being delivered to the Display section fortiming reference.CC: The polarity is controlled using either VPOL or HPOLin REG2:Text position Vertical.TXT: SFRs bits TXT1.HPOL & TXT1.VPOL control thepolarity.

Video/Data Switch (Fast Blanking) PolarityThe polarity of the Video/Data (Fast Blanking) signal canbe inverted. The polarity is set with the VDSPOL in REG7:RGB Brightness register.

Video/Data Switch AdjustmentTo take into account the delay between the RGB valuesand the VDS signal due to external buffering, the VDSsignal can be moved in relation to the RGB signals. TheVDS signal can be set to be either a clock cycle before or

CHAR 1

CHAR 2

CHAR 0

A000102030405060708090A0B0C0D0E0F

CHAR XX Address

16 bits

Micro Address8800h

8823h8824h

8847h8848h

886Bh

8C7Fh

8C5Ch8C5Bh

8C38h

8C80h

Fig.36 Organisation of DRC RAM

1011CHAR 30

CHAR 31

CHAR 33

CHAR 34

CHAR 32

CHAR 62

CHAR 63

8CA3h8CA4h

8CC7h8CC8h

8CEBh

90B8h

90DBh90DCh

90FFh

VDSPOL VDS Condition

0 1 RGB display

0 0 Video Display

1 0 RGB display

1 1 Video Display

Table 38 Fast Blanking Signal Polarity

Fig.37 13 Line High DRC’s Character Format

Top Left

Bottom Right

FringingTop Line

Hex

00300C0300C0300C00C00300C0003000C003000

440

Line 13 fromcharacter above

Line 1 fromcharacter below

Fringing1A8000

Pixel

Pixel

Line not used

LineNo.0123456789

101112131415

Bottom Line

MSB LSB

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CONFIDENTIAL

after the RGB signal, or coincident with the RGB signal.This is done using VDEL<2:0> in REG15:Configuration.

RGB Brightness ControlA brightness control is provided to allow the RGB upperoutput voltage level to be modified. The RGB amplitudemay be varied between 60% and 100%.The brightness is set in the RGB Brightness register asfollows: -

Contrast ReductionTXT: The COR bits in SFRs TXT5 & TXT6 control whenthe COR output of the device is activated (i.e. Pulled-low).This output is intended to act on the TV’s display circuits toreduce contrast of the video when it is active. The result ofcontrast reduction is to improve the readability of the textin a mixed teletext and video display.The bits in the TXT5 & TXT6 SFRs allow the display to beset up so that, for example, the areas inside teletext boxeswill be contrast reduced when a subtitle is being displayedbut that the rest of the screen will be displayed as normalvideo.In Teletext display mode the serial teletext box attributeand OSD box attribute define the region of the screenwhere Contrast Reduction is active.In CC display mode the serial character attribute ‘Boxing’is used to define the region of the screen in which theContrast Reduction is active.

Memory Mapped RegistersThe memory mapped registers are used to control thedisplay. The registers are mapped into the Micro-controllerMOVX address space, starting at address 87E0h andextending to 87FF.

BRI3-0 RGB Brightness

0 0 0 0 Lowest value

... ...

1 1 1 1 Highest value

Table 39 RGB Brightness

MMR MAP

ADD R/W Functions BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0

87F0 R/W DisplayControl

SRC<3> SRC<2> SRC<1> SRC<0> - msh MOD<1> MOD<0>

87F1 R/W Text PositionVertical

VPOL HPOL VOL<5> VOL<4> VOL<3> VOL<2> VOL<1> VOL<0>

87F2 R/W Text Area Start HOP<1> HOP<0> TAS<5> TAS<4> TAS<3> TAS<2> TAS<1> TAS<0>

87F3 R/W FringingControl

FRC<3> FRC<2> FRC<1> FRC<0> FRDN FRDE FRDS FRDW

87F4 R/W Text Area End - - TAE<5> TAE<4> TAE<3> TAE<2> TAE<1> TAE<0>

87F5 R/W Scroll Area SSH<3> SSH<2> SSH<1> SSH<0> SSP<3> SSP<2> SSP<1> SSP<0>

87F6 R/W Scroll Range SPS<3> SPS<2> SPS<1> SPS<0> STS<3> STS<2> STS<1> STS<0>

87F7 R/W RGB Brightness VDSPOL - - - BRI<3> BRI<2> BRI<1> BRI<0>

87F8 R Status read BUSY FIELD SCON FLR SCR<3> SCR<2> SCR<1> SCR<0>

87F8 W Status write - - SCON FLR SCR<3> SCR<2> SCR<1> SCR<0>

87FC R/W H-Sync. Delay - HSD<6> HSD<5> HSD<4> HSD<3> HSD<3> HSD<1> HSD<0>

87FD R/W V-Sync. Delay - VSD<6> VSD<5> VSD<4> VSD<3> VSD<2> VSD<1> VSD<0>

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CONFIDENTIAL

Table 40 MMR Map

87FE R/W Top Scroll Line - - - - SCL<3> SCL<2> SCL<1> SCL<0>

87FF R/W Configuration CC VDEL<2>

VDEL<1> VDEL<0> TXT/V 0 - Two_Page

87E0 R/W Text Area StartB

HOPB<1> HOPB<0>

TASB<5> TASB<4> TASB<3> TASB<2> TASB<1> TASB<0>

87E1 R/W Text Area End B - - TAEB<5> TAEB<4> TAEB<3> TAEB<2> TAEB<1> TAEB<0>

87E2 R/W Page B Position 0 PGB<6> PGB<5> PGB<4> PGB<3> PGB<2> PGB<1> PGB<0>

87E3 R/W Text PositionVertical B

- - VOLB<5> VOLB<4> VOLB<3> VOLB<2> VOLB<1> VOLB<0>

87E4 R/W Text PositionVertical Range

- - SMTHB SMTH RANGE

<1>

RANGE

<0>

RANGEB

<1>

RANGEB

<0>

MMR BIT DEFINITION

Names BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 RESET

Display Control. SRC<3> SRC<2> SRC<1> SRC<0> - msh MOD<1> MOD<0> 00H

SRC<3:0> Screen Colour definition

msh unused, must keep reset value -> ‘0’

MOD<1:0> 00 - Video

01 - Full Text

10 - Mixed Screen Colour

11 - Mixed Video

Text PositionVertical

VPOL HPOL VOL<5> VOL<4> VOL<3> VOL<2> VOL<1> VOL<0> 00H

VPOL 0 - Input polarity

1 - Inverted input polarity

HPOL 0 - Input Polarity

1 - Inverted input polarity

VOL<5:0> Display start Vertical Offset from V-Sync. (lines)

Text Area Start HOP<1> HOP<0> TAS<5> TAS<4> TAS<3> TAS<2> TAS<1> TAS<0> 00H

HOP<1:0> Fine Horizontal Offset in quarter of characters

TAS<5:0> Text area start

Fringing Control. FRC<3> FRC<2> FRC<1> FRC<0> FRDN FRDE FRDS FRDW 00H

FRC<3:0> Fringing colour, value address of CLUT

FRDN 0 - No fringe in North direction

1 - Fringe in North direction

FRDE 0 - No fringe in East direction

1 - Fringe in East direction

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FRDS 0 - No fringe in South direction

1 - Fringe in South direction

FRDW 0 - No fringe in West direction

1 - Fringe in West direction

Text Area End - - TAE<5> TAE<4> TAE<3> TAE<2> TAE<1> TAE<0> 00H

TAE<5:0> Text Area End, in full characters

Scroll Area SSH<3> SSH<2> SSH<1> SSH<0> SSP<3> SSP<2> SSP<1> SSP<0> 00H

SSH<3:0> Soft Scroll Height

SSP<3:0> Soft Scroll Position

Scroll Range SPS<3> SPS<2> SPS<1> SPS<0> STS<3> STS<2> STS<1> STS<0> 00H

SPS<3:0> Stop Scroll row

STS<3:0> Start Scroll row

RGB Brightness VDSPOL - - - BRI<3> BRI<2> BRI<1> BRI<0> 00H

VDSPOL VDS Polarity

0 - RGB (1), Video (0)

1 - RGB (0), Video (1)

BRI<3:0> RGB Brightness control

Status read BUSY FIELD SCON FLR SCR<3> SCR<2> SCR<1> SCR<0> 00H

BUSY 0 - Access to display memory will not cause display problems

1 - Access to display memory could cause display problems.

FIELD 0 - Odd Field

1 - Even Field

FLR 0 - Active flash region foreground and background displayed

1 - Active flash region background only displayed

SCR<3:0> First scroll row

Status write - - SCON FLR SCR<3> SCR<2> SCR<1> SCR<0> 00H

SCON 0 - Scroll area disabled

1 - Scroll area enabled

FLR 0 - Active flash region foreground and background colour displayed

1 - Active flash region background colour only displayed

SCR<3:0> First Scroll Row

H-Sync. delay - HSD<6> HSD<5> HSD<4> HSD<3> HSD<3> HSD<1> HSD<0> 00H

HSD<6:0> H-Sync delay, in full size characters

V-Sync Delay - VSD<6> VSD<5> VSD<4> VSD<3> VSD<2> VSD<1> VSD<0> 00H

VSD<6:0> V-Sync delay in number of TV lines

Top Scroll Line - - - - SCL<3> SCL<2> SCL<1> SCL<0> 00H

SCL<3:0> Top line for scroll

Configuration CC VDEL<2> VDEL<1> VDEL<0> TXT/V 0 - Two_Page 00H

CC 0 - OSD mode

1 - Closed Caption mode

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CONFIDENTIAL

Table 41 MMR Descriptions

VDEL<2:0> Pixel delay between VDS and RGB output

000 - VDS switched to video, not active

001 - VDS active one pixel earlier then RGB

010 - VDS synchronous to RGB

100 - VDS active one pixel after RGB

TXT/V BUSY Signal switch

0 - Vertical

1 - Horizontal

Two_Page Two Page mode select

0 - Single page

1 - Dual page

Text Area Start B HOP<1> HOP<0> TAS<5> TAS<4> TAS<3> TAS<2> TAS<1> TAS<0> 00H

HOP<1:0> Fine Horizontal Offset in quarter of characters

TAS<5:0> Text area start

Text Area End B - - TAE<5> TAE<4> TAE<3> TAE<2> TAE<1> TAE<0> 00H

TAE<5:0> Text Area End, in full characters

Page B Position 0 PGB<6> PGB<5> PGB<4> PGB<3> PGB<2> PGB<1> PGB<0> 00H

PGB<6:0> Page B Position

Text PositionVertical B

- - VOLB<5> VOLB<4> VOLB<3> VOLB<2> VOLB<1> VOLB<0> 00H

VOLB<5:0> Page B start Vertical Offset from V-Sync. Value is in horizontal scan lines. Must be set to VOL<5:0> in double window mode.

Vertical Range - - SMTHB SMTH RANGE<1>

RANGE<0>

RANGEB<1>

RANGEB

<0>

00H

SMTHB 0 - Smoothing inactive (page B)

1 - Smoothing active for Double Size, Double Height and Double Width (page B)

SMTH 0 - Smoothing inactive (single page or page A)

1 - Smoothing active for Double Size, Double Height and Double Width (single page or page B)

RANGE<1:0> Bits<7:6> of VOL (single page or page A vertical offset)

RANGEB<1:0> Bits<7:6> of VOLB (page B vertical offset). Must be set to RANGE<1:0> in double window and two page mode.

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SCAVEM TEXT OUTPUT

The Scavem (Scan Velocity Modulator) circuit is existed inthe Video Signal Processor die. The function is to enhanceedge details by varying the speed of the electric beam,providing a sharp and crisp picture. The generatedcharacter would have this feature by providing aSCAVTXT signal to video processing die. The SCAVTXTsignal is generated from R, G and B signals. The SFR,SCAVTXT.SCAVEM_EN is high active to enable thesignal output. The Scavem text processing needs about200ns. The SCAVTXT signal should go to Video SignalProcessor earlier than R, G and B signals 200ns as well.

For flexibility of adjusting the delay between SCAVTXTand R, G, and B signals, an SFR, SCAVTXT. EARLY<2:0>is for this purpose.

Table 42 Delay between SCAVTXT and R, G, B

The pulse width of SCAVEM text signal is defined in theSFR, SCAVTXT.PULSE_WIDTH<1:0>.

Table 43 SCAVEM Text pulse width

FLASH MEMORYThese may be programmed/erased via the ISP Interface.The flash memory can be erased/written over 100k times.

ISP InterfaceISP is via Hs-mode I2C upto 1.2 Mb/s.

FLASH MEMORY ORGANIZATION

The sectors are used to put program and character codes.

EARLY<2:0> SCAVTXT output earlier than R, G, and B signals

000 0 ns

001 74 ns

010 111 ns

011 148 ns

100 185 ns

101 212 ns

110 259 ns

111 296 ns

PULSE_WIDTH<1:0> SCAVEM Text pulse width

00 37 ns

01 74 ns

10 111 ns

11 148 ns

Sector x-1

Sector 1

Sector 0

page 0

page 1

page ss-1

256 bytes

Fig.38 Flash memory organization

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Programming proceduresFlash programming procedure is shown as below:

Enter ISP modeThere are mainly two cases using ISP mode when theUOCIII is mounted on PCB or TV. One case is the contentof flash memory is empty. Another case is that thecustomer code (program and character codes) wereprogrammed in flash memory and need to be upgraded.

Enter ISP mode when flash memory is emptyIn this case, the I2C bus is not occupied by themicro-controller, therefore follow the flows:- send thecorrect slave address, erase flash, write flash, and verifyflash sections can access to the flash memory via I2C.

Enter ISP mode when code is existed in flash memoryand is runningIn this case, embedded software should release theI2C-bus first and then following the flows:- send the correctslave address, erase flash, write flash, and verify flashsections can access to the flash memory via I2C.

The complete programming flow is supported by the WISPtool from Philips Semiconductors.

Erase flash

write flash

verify flash

Enter ISP mode

Power-on-reset

Fig.39 Flash programming procedure

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FUNCTIONAL DESCRIPTION OF VIDEO PROCESSOR

Vision IF amplifier

The vision IF amplifier can demodulate signals withpositive and negative modulation. The PLL demodulator iscompletely alignment-free.

The VCO of the PLL circuit is internal and the frequency isfixed to the required value by using the clock frequency ofthe TCG µ-Controller as a reference. The setting of thevarious frequencies (e.g. 38, 38.9, 45.75 and 58.75 MHz)can be made via the control bits IFA-IFC in subaddress2FH. Because of the internal VCO the IF circuit has a highimmunity to EMC interferences.

The output of the AFC detector can be read from outputbyte 04H and has a resolution of 7 bits (25 kHz per step).By means of this information a fast tuning algorithm can bedesigned.

The IC contains a group delay correction circuit which canbe switched between the BG and a uncompensated groupdelay response characteristic. This has the advantage thatin multi-standard receivers no compromise has to be madefor the choice of the SAW filter. This group delay correctionis realised for the demodulated CVBS output signal. TheIC contains in addition a sound trap circuit with aswitchable centre frequency.

Digital Broadcast reception

Apart from processing analogue TV signals, the IF circuitcan also preprocess digital TV signals before they are sentto a digital signal processor. These signals have to besupplied to the sound IF inputs. In this mode the IFreference frequency is fixed at 43.008 or 49.152 MHz. It isalso possible to supply an external reference signal todemodulator. The demodulator multiplies the incomingsignal with the fixed oscillator frequency. The mixed downsignal is low pass filtered to obtain a I-signal. The “Stereo”and “AV Stereo” versions have a differential output,however, it is possible to use a single-ended output. Thevarious output signal conditions can be set by means ofthe IFO2-IFO0 bits in subaddress 31H (see also table 94).The “Mono” versions have a single-ended output.

The AGC has two modes of operation: the internal modein which the IC sets the gain with its own reference and anexternal mode in which the gain can be controlled with anexternal circuit. In the second case the SIFAGC pin is usedas an input to control the IF gain with an external circuit.

QSS Sound circuit

The sound IF amplifier is similar to the vision IF amplifierand has an external AGC decoupling capacitor.

The single reference QSS mixer is realised by a multiplier.In this multiplier the SIF signal is converted to theintercarrier frequency by mixing it with the regeneratedpicture carrier from the VCO. The mixer output signal issupplied to the output via a high-pass filter for attenuationof the residual video signals. With this system a highperformance hi-fi stereo sound processing can beachieved.

The AM sound demodulator is realised by a multiplier. Themodulated sound IF signal is multiplied in phase with thelimited SIF signal. The demodulator output signal issupplied to the output via a low-pass filter for attenuationof the carrier harmonics.

Switching between the QSS output and AM output is madeby means of the AM bit in subaddress 33H.

FM demodulator

The FM demodulator is realised as narrow-band PLL withinternal loop filter, which provides the necessary selectivitywithout using an external band-pass filter. To obtain agood selectivity a linear phase detector and a constantinput signal amplitude are required. For this reason theintercarrier signal is internally supplied to the demodulatorvia a gain controlled amplifier and AGC circuit. To improvethe selectivity an internal bandpass filter is connected infront of the PLL circuit.

The nominal frequency of the demodulator is tuned to therequired frequency (4.5/5.5/6.0/6.5 MHz) by means of acalibration circuit which uses the clock frequency of theTCG(1) µ-Controller as a reference. It is also possible tofrequencies of 4.72 and 5.74 MHz so that a second soundchannel can be demodulated. In the latter application anexternal bandpass filter has to be applied to obtainsufficient selectivity (the sound input can be activated bymeans of the setting of CMB2-CMB0 bits in subaddress4AH). The setting to the wanted frequency is realised bymeans of the control bits FMA, FMB and FMC in thecontrol bit 33H.

From the output status bytes it can be read whether thePLL frequency is inside or outside the window and whetherthe PLL is in lock or not. With this information it is possibleto make an automatic search system for the incomingsound frequency. This can be realised by means of asoftware loop which switches the demodulator to the

(1) TCG = Text/Control/Graphics

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various frequencies and then select the frequency onwhich a lock condition has been found.

The amplitude deemphasis output signal changed with 6dB by means of the AGN bit. In this way output signaldifferences between the 4.5 MHz standard (frequencydeviation ±25 kHz) and the other standards (frequencydeviation ±50 kHz) can be compensated.

FM radio mode

The FM demodulator can be used for the demodulation ofFM radio signals. This mode is activated by means of theFMR-bit (subaddress 34H). The selectivity must be madeby means of a SAW filter at the sound input with a centrefrequency of 33.4 MHz for Europe and 41.25 MHz for theUSA. For this application the IF demodulator must be setto a fixed frequency (43.008 MHz for Europe and49.152 MHz for the USA). The resulting input frequencyfor the FM demodulator is then 9.6 MHz for Europe and7.9 MHz for the USA. This frequency must be selected bymeans of the bits FMA, FMB and FMC (see table 104). Inthe FM radio mode the demodulated intercarrier soundoutput signal can be supplied to the output pin(s) (FMRO)so that an external bandpass filter can be applied betweenthis pin and the SSIF pin.

The SSIF input can be either pin 33 or pin 53 (pins 96 or76 respectively for the “face down” version). The selectionis made by means of the ESSIF bit in subaddress 35H.

The mono intercarrier sound circuit can also be combinedwith an external FM tuner (IF frequency of 10.7 MHz). Inthat case an external 10.7 MHz bandpass filter is required.The demodulator centre frequency is set with the FMD bit(subaddress 33H).

FM stereo decoding is possible in versions that contain thedigital multi-standard stereo decoder. This mode isselected by means of the IFO2-IFO0 bits in subaddress31H.

Audio input selector and volume control

STEREO AND AV STEREO VERSIONS

The audio input selector circuit has 4 external stereoinputs, a stereo output for SCART/CINCH and stereooutputs for headphone and audio power amplifiers. Theselection is made with the bits SAS2/0, SO2/0 andHPO2/0. AV stereo versions without Audio DSP have noheadphone output. The input signal selection for thevolume controlled audio outputs is realised by the HPO2/0bits.

The gain from an external audio input to each of the(non-controlled) analog output is 0 or +6 dB (controlled bythe DSG bit). A supply voltage of 5V allows input andoutput amplitude of 1VRMS full scale. The audio selectorcircuit has a separate supply voltage pin. For audio outputsignal amplitudes of 2VRMS full scale, as required tocomply with the SCART specification, the audio supplyvoltage must be 8V. In that case the gain of the audioamplifier must be doubled. This can be realised with theDSG bit in subaddress 32H.

The circuit contains an analogue stereo volume controlcircuit with a control range of about 70 dB. This volumecontrol circuit is used for the headphone channel (stereoversions with Audio DSP) or for the main channel (AVstereo versions without Audio DSP). The analogue controlcircuit also contains an Automatic Volume Levelling (AVL)function. When this function is activated it stabilises theaudio output signal to a certain level so that big fluctuationsof the output power are prevented.

MONO VERSIONS

The audio input selector circuit has 4 inputs for monosignals. The selection is made with the HPO2/0 bits.

The circuit contains an analogue volume control circuitwith a control range of about 70 dB and an AVL circuit.

CVBS and Y/C input signal selection

ALL VERSIONS

The ICs have 3 inputs for external CVBS signals. All CVBSinputs can be used as Y input for the insertion of Y/Csignals. However, the CVBS(Y)2 input has to be combinedwith the C3 input. It is possible to add and extraCVBS(Y/C) input via the pins which are intended to beused for YUV interface (or RGB/YPRPB input). Theselection of this additional CVBS(Y/C) input is made viathe YC bit. The CVBS selector has one independentlyswitchable output. The switch configuration is given inFig. 40. The choice of the various modes can be made viathe INA-IND bits in subaddress 38H.

The function of the IFVO/SVO/CVBSI pin is determined bythe SVO1/SVO0 bits. When used as output a selection canbe made between the IF video output signal or theselected CVBS signal (monitor out). This pin can also beused as additional CVBS input. This signal is inserted infront of the group delay / sound trap circuit. It is alsopossible to use the group delay and sound trap circuit forthe CVBS2 signal (via the CV2 bit).

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For the CVBS(Y/C) inputs the circuit can detect whether aCVBS or Y/C signal is present on the input. The result canbe read from the status register (YCD bit in subaddress03H) and this information can be used to put the inputswitch in the right position (by means of the INA-IND bitsin subaddress 38H). The Y/C detector is only active for theCVBS(Y)3/C3, CVBS(Y)4/C4 and CVBS(Y)x/Cx inputs. Itis not active for the CVBS(Y)2/C3 input.

The video ident circuit can be connected to all video inputsignals. This ident circuit is independent of thesynchronisation and can be used to switch thetime-constant of the horizontal PLL depending on thepresence of a video signal (via the VID bit). In this way avery stable OSD can be realised. The result of the videoident circuit can be read from the output bit SID(subaddress 00)

CVBSOC3CVBS/Y-2

Fig.40 CVBS switch

CVBS1

CVBS/Y-3

+

SOUND TRAP

GROUP DELAY

CORRECTION

IFOUT SVO/IFOUT/CVBSI YSYNC

4H/2H PAL/NTSC

COMB FILTER

Y

C

SYNC

SEPARATOR

H/V

SYS

SVO1/SVO0CV2 or SVO1

CFA0

IFOUT

CVBS/Y-4 C4 CVBS/Y-x Cx

GD

SVO1

IFOX

VIDEO

IDENTIFICATION

SID

G/Y-3

Synchronisation circuit

The IC contains separator circuits for the horizontal andvertical sync pulses. To obtain an accurate timing of thedisplayed picture the input signal of the sync separator isnot derived from the various CVBS/Y or RGB/YPRPBinputs but from the YOUT pin. For this reason the YOUTpin must be capacitively coupled to the YSYNC pin. Thedelay between the various inputs and the YOUT signal canhave rather large differences (e.g. comb filter active ornot). By choosing the YOUT signal as input signal for thesync separator these delays have no effect on the pictureposition. Only for RGB signals without sync on green theinput of the sync separator has to be connected to one ofthe CVBS inputs. This selection is made by means of theSYS bit.

The horizontal drive signal is obtained from an internalVCO which is running at a frequency of 25 MHz. Thisoscillator is stabilised to this frequency by using the clocksignal coming from the reference oscillator of the TCGµ-Controller.

To obtain a stable On-Screen-Display (OSD) under allconditions it is important that the first control loop isswitched off or set to low gain when no signal is availableat the input. The input signal condition is detected by thevideo identification circuit. The video identification circuitcan automatically switch first control loop to a low gainwhen no input signal is available. This mode is obtainedwhen the VID bit is set to “0”. When the VID bit is “1” themode of the first control loop can be switched by means ofthe FOA/FOB or POC bits.

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For a good performance during normal TV reception(display of the front-end signal) various connections areactive between the vision IF amplifier and thesynchronisation circuit (e.g. gating pulses for the AGCdetector and noise gating of the sync separator). Theseconnections are not allowed when external video signalsare displayed. The switching of these connections can becoupled to the input signal selection bits (INA-IND). Thismode is obtained when the VDXEN bit is “0”. Due to theinput signal selector configuration it is possible that theinternal CVBS signal is available on one of the other CVBSinputs. In this condition the connections between the visionIF amplifier and the synchronisation circuit can beswitched on and off by means of the VDX bit. The VDXENbit must be set to “1” for this mode.

The vertical synchronisation is realised by means of adivider circuit.

Horizontal and vertical drive

The horizontal drive is switched on and off via the softstart/stop procedure. The soft start function is realised bymeans of variation of the TON of the horizontal drivepulses. During the soft-stop period the horizontal outputfrequency is doubled resulting in a reduction of the EHT sothat the picture tube capacitance can easily be discharged.In addition the horizontal drive circuit has a ‘low-powerstart-up’ function.

The vertical ramp generator needs an external resistor andcapacitor. For the vertical drive a differential output currentis available. The outputs must be DC coupled to thevertical output stage.

The IC has the following geometry control functions:

• Vertical amplitude

• Vertical slope

• S-correction

• Vertical shift

• Vertical zoom

• Vertical scroll

• Vertical linearity correction. When required the linearitysetting for the upper and lower part of the screen canhave a different setting.

• Horizontal shift

• EW width

• EW parabola width

• EW upper and lower corner parabola correction

• EW trapezium correction

• Horizontal parallelogram and bow correction.

When the vertical amplitude is compressed (zoomfactor <1) it is still possible to display the black currentmeasuring lines in the overscan. This function is activatedby means of the bit OSVE in subaddress 40H.

The vertical guard input is combined with an I/O function.The following functions can be realised with this pin:

• Just vertical guard input.

• Combination of vertical guard and LED drive output. Inthis condition the output is high-ohmic during the verticalretrace (1 ms) so that the vertical guard pulse can bedetected.

• Single ended output switch

• Input port

The functionality of this pin is controlled by the VGM1/0and LED bits.

When the East-West geometry function is not required(e.g. for 90° picture tubes) the EW output pin can be usedfor the connection of the AVL capacitor. This function ischosen by means of the AVLE bit.

The UOCIII devices can also be used as input processorfor 100 Hz or LCD TV receivers. In that case the deflectiondrive signals are not required. For these applications anH/V timing signal can be obtained from the flybackinput/sandcastle output pin. This mode is activated bymeans of the CSY bit (subaddress 4AH). The horizontaloutput pin is switched to “high” in this condition. A changeof the CSY bit is possible only in the stand-by mode(STB = 0).

Chroma, luminance and feature processing

Some versions contain a 4H/2H (2D) adaptive PAL/NTSCcomb filter. The comb filter is automatically activated whenstandard CVBS signals are received. A signal isconsidered as “standard signal” when a PAL or NTSCsignal is identified and when the vertical divider is in themodes ‘standard narrow window’ or ‘standard TVnorm’.For non-standard signals and for SECAM signalsthe comb filter is bypassed and the signal is filtered bymeans of bandpass and trap filters.

The chroma band-pass and trap circuits (including theSECAM cloche filter) are realised by means of internalfilters and are tuned to the right frequency by comparingthe tuning frequency with the reference frequency of thecolour decoder.

The circuit contains the following picture improvementfeatures:

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• Peaking control circuit. The peaking function can beactivated for all incoming CVBS, Y/C and RGB/YPRPBsignals. Various parameters of the peaking circuit canbe adapted by means of the I2C-bus. The mainparameters are:

– Peaking centre frequency (via the PF1/PF0 bits insubaddress 19H).

– Ratio of positive and negative peaks (via theRPO1/RPO0 bits in subaddress 47H). The peaks inthe direction “white” are the positive peaks.

– Ratio of pre- and aftershoots (via the RPA1/RPA0bits in subaddress 47H).

• Video dependent coring in the peaking circuit. Thecoring can be activated only in the low-light parts of thescreen. This effectively reduces noise while havingmaximum peaking in the bright parts of the picture.

• Black stretch. This function corrects the black level forincoming signals which have a difference between theblack level and the blanking level. The amount ofstretching (A-A in Fig. 72) and the minimum requiredback ground to activate the stretching can be set bymeans of the I2C-bus (BSD/AAS in subaddress 45H).

• Gamma control. When this function is active the transfercharacteristic of the luminance amplifier is madenon-linear. The control curve can be adapted by meansof I2C-bus settings (see Fig. 74). It is possible to makethe gamma control function dependent on the picturecontent (Average Picture Level, APL). The effect isillustrated in Fig. 75. Previously this function wasmentioned under the name “white stretch function”.

• Blue-stretch. This circuit is intended to shift colour near‘white’ with sufficient contrast values towards more blueto obtain a brighter impression of the picture.

• Dynamic skin tone (flesh) control. This function isrealised in the YUV domain by detecting the coloursnear to the skin tone.

• Scan-Velocity modulation output. Also the SVM functioncan be activated for all incoming CVBS, Y/C andRGB/YPRPB signals. The delay between the RGBoutput signals and the SVM output signal can beadjusted (by means of the SVM2-SVM0 bits insubaddress 48H) so that an optimum pictureperformance can be obtained. Furthermore a coringfunction can be activated. It is possible to generate ScanVelocity Modulation drive signals during the display of‘full screen’ teletext (not in mixed mode). Anotherfeature is that the SVM output signal can be madedependent on the horizontal position on the screen(parabola on the SVM output).

Colour decoder

The ICs decode PAL, NTSC and SECAM signals. ThePAL/NTSC decoder does not need external referencecrystals but has an internal clock generator which isstabilised to the required frequency by using the clocksignal from the reference oscillator of the TCGµ-Controller.

Under bad-signal conditions (e.g. VCR-playback in featuremode), it may occur that the colour killer is activatedalthough the colour PLL is still in lock. When this killingaction is not wanted it is possible to overrule the colourkiller by forcing the colour decoder to the required standardand to activate the FCO-bit (Forced Colour On) insubaddress 3CH. The sensitivity of the colour decoder forPAL and NTSC can be increased by means of the settingof the CHSE1/CHSE0 bits in subaddress 3CH.

The Automatic Colour Limiting (ACL) circuit (switchablevia the ACL bit in subaddress 3BH) prevents thatoversaturation occurs when signals with a highchroma-to-burst ratio are received. The ACL circuit isdesigned such that it only reduces the chroma signal andnot the burst signal. This has the advantage that the coloursensitivity is not affected by this function.

The SECAM decoder contains an auto-calibrating PLLdemodulator which has two references, viz: the dividedreference frequency (obtained from the µ-Controller)which is used to tune the PLL to the desired free-runningfrequency and the bandgap reference to obtain the correctabsolute value of the output signal. The VCO of the PLL iscalibrated during each vertical blanking period, when theIC is in search or SECAM mode. The frequency offset ofthe B-Y demodulator can be reduced by means of theSBO1/SBO0 bits in subaddress 3CH.

The base-band delay line is integrated. In devices withoutCVBS comb filter this delay line is also active during NTSCto obtain a good suppression of cross colour effects. Thedemodulated colour difference signals are internallysupplied to the delay line. The baseband comb filter can beswitched off by means of the BPS bit (subaddress 3CH).

The subcarrier output is combined with a 3-level outputswitch (0 V, 2.1 V and 4.5 V). The output level and theavailability of the subcarrier signal is controlled by theCMB2-CMB0 bits.

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RGB output circuit

In the RGB control circuit the signal is controlled oncontrast, brightness and saturation. The IC has a YUVinterface so that additional picture improvement ICs canbe applied. To compensate signal delays in the externalYUV path the clamp pulse in the control circuit can beshifted by means of the CLD bit in subaddress 44H. Whenthe YUV interface is not required some of the pins can beused for the insertion of RGB/YPRPB signals or asadditional CVBS(Y)/C input. When the YUV interface is notused one of the pins (VOUT) is transferred to generalpurpose output switch (SWO1). The IC has also a YUVinterface to the digital die. Via this loop digital features like“double window” are added.

A tint control is available for the base-band U/V signals.For this reason this tint control can be activated for allcolour standards. The signals for OSD and text areinternally supplied to the control circuit. The output signalhas an amplitude of about 1.2 V black-to-white at nominalinput signals and nominal settings of the various controls.

To obtain an accurate biasing of the picture tube the‘Continuous Cathode Calibration’ system has beenincluded in these ICs. The system is slightly adaptedcompared with the previous circuits. In the newconfiguration the cut-off level of the picture tube iscontrolled with a continuous loop whereas the correction ofthe amplitude of the output signals is realised by means ofa digital loop. As a consequence the current measurementcan be controlled from the µ-Processor. The value of the“high current” in the CCC loop can be chosen via the SLG0and SLG1 bits (subaddresses 42H and 46H). The gaincontrol in the 3 RGB channels is realised by means of 7-bitDACs. The total gain control range is ±6 dB. The changein amplitude at the cathodes of the picture tube for oneLSB is about 1.1 VP-P. The setting of the control DAC isdetermined by the following registers:

• The white point setting of the R, G and B channel insubaddress 20H to 22H. This register has a resolution of6 bits and the control range in output signal amplitude is±3 dB.

• The cathode drive setting (CL3-CL0 in subaddress42H). This setting is valid for all channels, the resolutionis 4 bits and the control range is ±3 dB.

• The gain setting of the R, G and B channel. Duringswitch on this register is loaded with the preset gainsetting of subaddress 23H to 25H and when necessaryit will be adapted by the CCC control loop. Theseregisters have a resolution of 7 bits. The control of thegain setting is illustrated in table 44.

Table 44 Addition of WP, CL and gain register settings

The setting of the gain registers of the 3 channels can bestored during switch off and can be loaded again duringswitch-on so that the drive conditions are maintained.

When required the operation of the CCC system can bechanged into a one-point black current system. Theswitching between the 2 possibilities is realised by meansof the EGL bit (EGL = 0) in subaddress 42H. When usedas one-point control loop the system will control the blacklevel of the RGB output signals to the ‘low’ referencecurrent and not on the cut off point of the cathode. In thisway spreads in the picture tube characteristics will not betaken into account. In this condition the settings of the“white point control registers” (subaddress 20H - 22H) andthe “cathode drive level bits” (CL3 - CL0 in subaddress42H) are added to the settings of the RGB preset gainregisters (subaddress 23H - 25H).

A black level off-set can be made with respect to the levelwhich is generated by the black current stabilizationsystem. In this way different colour temperatures can beobtained for the bright and the dark part of the picture. Theblack level control is active on the Red and the Greenoutput signal. It is also possible to control the black level ofthe Blue and the Green output signal (OFB bit = 1).

In the Vg2 adjustment mode (AVG = 1) the black currentstabilization system checks the output level of the 3channels and indicates whether the black level of thehighest output is in a certain window (WBC-bit) or below orabove this window (HBC-bit). This indication can be readfrom the status byte 01 and can be used for automaticadjustment of the Vg2 voltage during the production of theTV receiver. During this test the vertical scan remainsactive so that the indication of the 2 bits can be madevisible on the TV screen.

The control circuit contains a beam current limiting circuitand a peak white limiting circuit. The control is realised bymeans of a reduction of the contrast and brightness controlsettings. The way of control (first contrast and thenbrightness or contrast and brightness in parallel) can bechosen by means of the CBS bit (subaddress 44H). Thepeak white level is adjustable via the I2C-bus.

WPR(GB) ‘0’ B5 B4 B3 B2 B1 B0 max 64

CL ‘0’ B3 B2 B1 B0 ‘0’ ‘0’ max 60

CCC-gain B6 B5 B4 B3 B2 B1 B0 max 126

R(GB)-gain B6 B5 B4 B3 B2 B1 B0 max 126

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To prevent that the peak white limiting circuit reacts on thehigh frequency content of the video signal a low-pass filteris inserted in front of the peak detector. The circuit alsocontains a soft-clipper which prevents that the highfrequency peaks in the output signal become too high. Thedifference between the peak white limiting level and thesoft clipping level is adjustable via the I2C-bus in a fewsteps.

During switch-off of the TV receiver a fixed beam currentis generated by the black current control circuit. This

current ensures that the picture tube capacitance isdischarged. During the switch-off period the verticaldeflection can be placed in an overscan position so thatthe discharge is not visible on the screen.

A wide blanking pulse can be activated in the RGB outputsby means of the HBL bit in subaddress 43H. The timing ofthis blanking can be adjusted by means of the bits WBF/Rbits in subaddress 26H.

I2C-BUS USER INTERFACE DESCRIPTION OF THE VIDEO PROCESSOR

The UOCIII series is fully controlled via the I2C-bus. Control is exercised by writing data to one or more internal registers.Status information can be read from a set of info registers to enable the controlling microcontroller determine whetherany action is required.The device has an I2C-bus slave transceiver, in accordance with the fast-mode specification, witha maximum speed of 400 kbits/s. Information concerning the I2C-bus can be found in brochure “I2C-bus and how to useit” (order number 9398 393 40011). To avoid conflicts in a real application with other ICs providing similar orcomplementary functions, there are two possible slave addresses available which can be selected by the SVM pin (pin65).

Possible slave address

The device will not respond to a ‘general call’ on the I2C-bus, i.e. when a slave address of 0000000 is sent by a master.

Write registers

Each address of the address space (see below) can only be written.

Correct operation is not guaranteed if registers in the range $FB to $FF will be addressed!

Overview address space

Read registers

The output registers of the TV processor are only available via auto-increment mode, no address can be used and allregisters must be read.

SVM PIN SLAVE ADDRESS A6 TO A0

scavem application 1 0 0 0 1 0 1

tied to 5 volts 1 0 0 0 1 1 1

ADDRESS WORDS WORDLENGTH DESCRIPTION

$00 to $29 42 words 1 byte I2C addresses enabled andusable

$2A to $2E - - Not used

$2F to $4A 28 words 1 byte I2C addresses enabled andusable

$4B to $FA - - Not used

$FB to $FF 5 words 1 byte I2C addresses enabled notusable

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DESCRIPTION OF THE I2C-BUS SUBADDRESSES

Table 45 Inputs TV processor

FUNCTIONSUBADDR

(HEX)

DATA BYTE POR

D7 D6 D5 D4 D3 D2 D1 D0 Value

Spare 00 0 0 0 0 0 0 0 0 00Spare 01 0 0 0 0 0 0 0 0 00Spare 02 0 0 0 0 0 0 0 0 00Volume control (L) 03 0 A6 A5 A4 A3 A2 A1 A0 20Volume control R (2) 04 0 A6 A5 A4 A3 A2 A1 A0 20Horizontal shift (HS) 05 0 0 A5 A4 A3 A2 A1 A0 20Horizontal parallelogram 06 0 0 A5 A4 A3 A2 A1 A0 20Horizontal bow 07 0 0 A5 A4 A3 A2 A1 A0 20Vertical linearity 08 VL1 VL0 A5 A4 A3 A2 A1 A0 20Vertical scroll 09 0 0 A5 A4 A3 A2 A1 A0 20EW width (EW) (1) 0A 0 0 A5 A4 A3 A2 A1 A0 20EW parabola/width (PW) (1) 0B 0 0 A5 A4 A3 A2 A1 A0 20EW upper corner parabola(1) 0C 0 0 A5 A4 A3 A2 A1 A0 20EW lower corner parabola(1) 0D 0 0 A5 A4 A3 A2 A1 A0 20EW trapezium (TC) (1) 0E 0 0 A5 A4 A3 A2 A1 A0 20Vertical slope (VS) 0F 0 0 A5 A4 A3 A2 A1 A0 20Vertical amplitude (VA) 10 0 0 A5 A4 A3 A2 A1 A0 20S-correction (SC) 11 0 0 A5 A4 A3 A2 A1 A0 20Vertical shift (VSH) 12 0 0 A5 A4 A3 A2 A1 A0 20Vertical zoom (VX) 13 0 0 A5 A4 A3 A2 A1 A0 20Off-set IF demodulator 14 0 0 A5 A4 A3 A2 A1 A0 20AGC take-over 15 0 0 A5 A4 A3 A2 A1 A0 20Spare 16 0 0 0 0 0 0 0 0 00Black level offset R 17 0 0 A5 A4 A3 A2 A1 A0 20Black level offset G 18 0 0 A5 A4 A3 A2 A1 A0 20Peaking 19 PF1 PF0 A5 A4 A3 A2 A1 A0 20White limiting 1A 0 0 SOC1 SOC0 A3 A2 A1 A0 08Brightness 1B 0 0 A5 A4 A3 A2 A1 A0 20Saturation 1C 0 0 A5 A4 A3 A2 A1 A0 20Contrast 1D 0 0 A5 A4 A3 A2 A1 A0 20Base-band tint control 1E 0 0 A5 A4 A3 A2 A1 A0 20Spare 1F 0 0 0 0 0 0 0 0 00White point R 20 0 0 A5 A4 A3 A2 A1 A0 00White point G 21 0 0 A5 A4 A3 A2 A1 A0 00White point B 22 0 0 A5 A4 A3 A2 A1 A0 00PGR - Preset Gain Red 23 LPG A6 A5 A4 A3 A2 A1 A0 00PGG - Preset Gain Green 24 0 A6 A5 A4 A3 A2 A1 A0 00PGB - Preset Gain Blue 25 0 A6 A5 A4 A3 A2 A1 A0 00Timing of ‘wide blanking’ (1) 26 WBF3 WBF2 WBF1 WBF0 WBR3 WBR2 WBR1 WBR0 88Hue for NTSC 27 0 0 A5 A4 A3 A2 A1 A0 00IF Preset Value 1 28 0 EPVI A5 A4 A3 A2 A1 A0 00

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CONFIDENTIAL

Note

1. These functions are only available when the East-West drive output is active (AVLE = 0).

2. This function is available only in the “Stereo” and “AV Stereo” versions.

3. Only available in the “Mono” versions

4. The AVL function can only be activated when a capacitor is connected to the EW output pin (AVLE = 1) or to thesubcarrier output pin (via the bits CMB2-CMB0).

IF Preset Value 2 29 0 0 A5 A4 A3 A2 A1 A0 00Spare 2A 0 0 0 0 0 0 0 0 00Spare 2B 0 0 0 0 0 0 0 0 00Spare 2C 0 0 0 0 0 0 0 0 00Spare 2D 0 0 0 0 0 0 0 0 00Spare 2E 0 0 0 0 0 0 0 0 00Vision IF 0 2F 0 IFD IFA IFB IFC VSW MOD AFN 00Vision IF 1 30 0 STM AGCM IFLF GD AGC1 AGC0 FFI 00Vision IF 2 31 CMSS VA1 VA0 VAI IFS IFO2 IFO1 IFO0 00Sound 0 32 0 NRR 0 DSG RDS MONO FMWS1 FMWS0 00Sound 1 33 AGN AM SM1 SM0 FMD FMC FMB FMA 00Sound 2 34 0 0 AVLE QSS BPB AVL(4) FMR FMI 00Sound 3 35 0 FMS AVLM 0 ESSIF CMCA BPB2 AMLOW 00Audio selection 0 36 0 HPVC SPT 0 SMLS SO2 SO1 SO0 00Audio selection 1 37 0 E2D(3) SAS2 SAS1 SAS0 HPO2 HPO1 HPO0 00Video selection 0 38 CS1A CS1B CS1C CS1D INA INB INC IND 00Video selection 1 39 0 0 0 CFA0 CV2 SVO1 SVO0 SYS 00Video selection 2 3A 0 0 VDXEN VDX YD3 YD2 YD1 YD0 00Colour decoder 0 3B CM3 CM2 CM1 CM0 MAT MUS ACL CB 00Colour decoder 1 3C SBO1 SBO0 CHSE1 CHSE0 CLO DTR BPS FCO 00Synchronisation 0 3D SDC HP2 FOA FOB POC STB HTXT VID 00Synchronisation 1 3E WBI RED FSL OSO FORF FORS DL NCIN 00Synchronisation 2 3F 0 VGM1 VGM0 LED SSL SD2 SD1 SD0 00Deflection 0 40 VSD OSVE DFL XDT SBL AVG EVG HCO(1) 00Deflection 1 / Control 0 41 DEFL SVMA MVK 0 0 0 FBC EVB 00Control 1 42 INTF EGL SLG0 AKB CL3 CL2 CL1 CL0 00Control 2 43 IE3 IE2 DINT YC YUV2 YUV1 YUV0 HBL(1) 00Control 3 44 GAM TFR CLD CBS OUV PWL RBL RGBL 00Control 4 45 BKS BSD AAS DSK WS1 WS0 BLS TUV 00Control 5 46 OFB HCT FINM FIN SLG1 BLBG LLB DSA 00Peaking 47 0 0 RPA1 RPA0 RPO1 RPO0 COR1 COR0 00SVM 0 48 0 CRA0 SPR2 SPR1 SPR0 SVM2 SVM1 SVM0 00SVM 1 49 DSS 0 0 0 VMA1 VMA0 SMD1 SMD0 00Miscellaneous 1 4A 0 DISG DDLE CSY SWO1 CMB2 CMB1 CMB0 00Miscellaneous 2 4B 0 0 0 0 BPYD 0 0 0 00

FUNCTIONSUBADDR

(HEX)

DATA BYTE POR

D7 D6 D5 D4 D3 D2 D1 D0 Value

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CONFIDENTIAL

Table 46 Outputs TV-processor

FUNCTION SUBADDRDATA BYTE

D7 D6 D5 D4 D3 D2 D1 D0

Output status bytes 00 POR SID LOCK SL CD3 CD2 CD1 CD0

01 XPR NDF FSI IVW WBC HBC BCF COMB

02 SUP AGC IN3 IN2 SUPR X FMW FML

03 X X X IVWF SN2 SN1 SN0 YCD

04 AFC7 AFC6 AFC5 AFC4 AFC3 AFC2 AFC1 AFC0

05 GLOK RG6 RG5 RG4 RG3 RG2 RG1 RG0

06 PTW GG6 GG5 GG4 GG3 GG2 GG1 GG0

07 X BG6 BG5 BG4 BG3 BG2 BG1 BG0

08-09 X X X X X X X X

0A 0 0 0 DFL4 DFL3 DFL2 DFL1 DFL0

0B DISC9 DISC8 DISC7 DISC6 DISC5 DISC4 DISC3 DISC2

0C-0F X X X X X X X X

Explanation input control data TV-processor

Table 47 Volume control (L and R)

Table 48 Horizontal shift

Table 49 Horizontal parallelogram

Table 50 Horizontal bow

Table 51 Upper/lower vertical linearity control

Table 52 Vertical linearity (VL1/VL0 setting 0/0)

DAC SETTING CONTROL

0 attenuation 70 dB

7F no attenuation

DAC SETTING CONTROL

0 −2 µs

20 0

3F +2 µs

DAC SETTING CONTROL

0 screen top 0.75 µs delayed andscreen bottom 0.75 µs advanced withrespect to centre

20 no correction

3F screen top 0.75 µs advanced andscreen bottom 0.75 µs delayed withrespect to centre

DAC SETTING CONTROL

0 screen top and bottom 1.0 µs delayedwith respect to centre

20 no correction

3F screen top and bottom 1.0 µsadvanced with respect to centre

VL1 VL0 SETTING

0 0 ‘full-screen’ vertical linearity (seeTable 52)

0 1 only ‘lower’ vertical linearity

1 0 only ‘upper’ vertical linearity

DAC SETTING CONTROL

0 ratio bottom/top of screen: 117%

20 no correction

3F ratio bottom/top of screen: 85%

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Table 53 Vertical scroll (at zoom setting of 3FH,percentage of nominal visible amplitude); note 1

Note

1. The vertical scroll function is active only in the expandmode of the vertical zoom, i.e at a DAC position whichis larger than 10H.

Table 54 EW width

Table 55 EW parabola/width

Table 56 EW upper/lower corner parabola

Table 57 EW trapezium

Table 58 Vertical slope

Table 59 Vertical amplitude

Table 60 S-correction

Table 61 Vertical shift

Table 62 Vertical zoom

Table 63 Offset IF demodulator

Note

1. This control is intended to correct for DC offset in theIF-PLL to improve the S/N ratio of the intercarriersound signal.

Table 64 AGC take-over

DAC SETTING CONTROL

0 picture shift −18%

20 no picture shift

3F picture shift +18%

DAC SETTING CONTROL

0 output current 700 µA

3F output current 0 µA

DAC SETTING CONTROL


3F output current 440 µA at top andbottom of screen

DAC SETTING CONTROL

0 output current +262 µA (+55%)


3F output current −262 µA (−55%)

DAC SETTING CONTROL

0 output current at top of screen 100 µAlower that at bottom

20 no correction

3F output current at top of screen 100 µAhigher than at bottom

DAC SETTING CONTROL

0 correction −20%

20 no correction

3F correction +20%

DAC SETTING CONTROL

0 amplitude 80%

20 amplitude 100%

3F amplitude 120%

DAC SETTING CONTROL

0 correction −10%

0E no correction

3F correction 25%

DAC SETTING CONTROL

0 shift −5%

20 no correction

3F shift +5%

DAC SETTING CONTROL

0 amplitude 75%

19 amplitude 100%

3F amplitude 138%

DAC SETTING CONTROL

0 negative correction

20 no correction

3F positive correction

DAC SETTING CONTROL

0 tuner take-over at IF input signal of0.4 mV

3F tuner take-over at IF input signal of80 mV

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Table 65 Black level offset R/V - G/U;

Note

1. Offset DAC can be used for offset correction on RG oron UV. The range for both cases is different.

Table 66 Peaking centre frequency and delay

Table 67 Peaking control (overshoot in direction ‘black’)

Table 68 Soft clipping level

Table 69 Peak White Limiting; note 1

Note

1. CVBS/Y input signal at which the Peak White Limitingis activated (max contrast setting). Nominal inputsignal: 0.7 VBL-WH.

Table 70 Brightness control

Table 71 Saturation control

Table 72 Contrast control

Table 73 Base-band tint control

Table 74 White point R/G/B

Table 75 RGB gain preset; note 1

Note

1. The gain of the RGB amplifiers is controlled by meansof 7-bit DACs. The value of the gain is dependent onthe setting of the “White Point RGB” registers(subaddress 20H - 22H), the setting of the “Cathodedrive level” (CL3 - CL0 in subaddress 42H) and theCCC loop control. During switch-on of the TV receiverthe preset value of the gain setting has to be loaded.

DAC SETTING CONTROL

0 −100 mV (R/G), -50mV (U/V)

20 no offset

3F +100 mV (R/G), +50mV (U/V)

PF1 PF0 CENTRE FREQUENCY DELAY

0 0 2.7 MHz 190 ns

0 1 3.1 MHz 160 ns

1 0 3.5 MHz 143 ns

1 1 4.0 MHz 125 ns

DAC SETTING CONTROL

0 depeaking (overshoot −18%)

0D no peaking

3F overshoot 75%

SOC1 SOC0VOLTAGE DIFFERENCE BETWEEN

SOFT CLIPPING AND PWL

0 0 0% above PWL level



1 1 soft clipping off

DAC SETTING CONTROL

00 0.40 VBL-WH

0F 0.60 VBL-WH

DAC SETTING CONTROL

0 correction −0.4 V

20 no correction

3F correction +0.4 V

DAC SETTING CONTROL

0 colour off (−52 dB)

17 saturation nominal

3F saturation +300%

DAC SETTING CONTROL

0 RGB amplitude −14 dB

20 RGB amplitude nominal

3F RGB amplitude +6 dB

DAC SETTING CONTROL

0 −30°20 0°3F +30°

SETTING CONTROL

0 gain −3 dB

20 no correction

3F gain +3 dB

LPG CONDITION

0 normal operation

1 preset gain setting is loaded

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Table 76 Preset gain setting for R, G and B, note 1

Note

1. These values are valid in the following condition:

a) The white point setting for the R, G and B channelis set to 0

b) The cathode drive setting (CL3-CL0) is set to 0

c) The contrast setting is −3 dB

d) The gain of the RGB output amplifiers is 80

Table 77 Timing of ‘wide blanking’

Table 78 Hue control for NTSC

Table 79 IF PLL oscillator preset value; note 1

Note

1. During “mix-down” of DVB signals with an externalreference carrier (CMB2/CMB1/CMB0 = 1/0/0) thefrequency of the oscillator can be defined by means ofthe settings of the “IF Preset Value” registers(subaddress 28H and 29H).

Table 80 PLL demodulator frequency setting

Table 81 Video mute

Table 82 Modulation standard

Table 83 AFC switch

Table 84 Search tuning mode

Table 85 Internal or external AGC mode

Table 86 Calibration of IF PLL demodulator

SETTING CRT DRIVE VOLTAGE

0 45 VP-P

40 90 VP-P

7F 180 VP-P

WBF/R3-0 SETTING

0 3.5 / 7.8 µs

0F 5.9 / 10.2 µs

HUE CONTROL

0 −40°20 0°3F +40°

EPVI CONDITION

0 normal operation

1 preset value is loaded

IFD IFA IFB IFC IF FREQUENCY

0 0 0 0 58.75 MHz

0 0 0 1 45.75 MHz

0 0 1 0 38.90 MHz

0 0 1 1 38.00 MHz

0 1 0 0 33.40 MHz

0 1 0 1 43.008 MHz

0 1 1 0 33.90 MHz

0 1 1 1 49.152 MHz

1 X X X external reference carrier

VSW STATE

0 normal operation

1 IF-video signal switched off

MOD MODULATION

0 negative

1 positive

AFN MODE

0 normal operation

1 AFC not active

STM MODE

0 normal operation

1 reduced sensitivity of video indent circuit

AGCM MODE

0 internal mode of DVB AGC

1 external mode for DVB AGC

IFLF MODE

0 calibration system active

1 calibration system not active

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Table 87 Group delay on CVBS1 signal

Table 88 IF AGC speed

Table 89 Fast filter IF-PLL

Table 90 Selection of sync input signal for the video identcircuit

Table 91 Video output signal amplitude

Table 92 System I output signal amplitude correction

Table 93 IF sensitivity

GD CONDITION

0 no group delay correction

1 group delay correction switched on

AGC1 AGC0 AGC SPEED

0 0 0.7 × norm

0 1 norm

1 0 3 × norm

1 1 6 × norm

FFI CONDITION

0 normal time constant

1 increased time constant

CMSS CONDITION

0 input from sync separator in IF ident circuit

1 input from main sync separator

VA1 VA0 OUTPUT SIGNAL AMPLITUDE

0 0 no correction

1 0 amplitude −5%

1 1 amplitude +5%

VAI MODE

0 no correction

1 amplitude +12%

IFS IF SENSITIVITY

0 normal

1 reduced

Table 94 IF output selection, note 1

Note

1. The result of this setting of the IFO2-IFO0 bits is also dependent on the setting of the IF-PLL frequency (IFA-IFC insubaddress 2FH) and the FMR bit (subaddress 34H). The following conditions are possible:

a) Analogue TV mode (required settings: FMR = 0 and IFA/IFB/IFC = 000/001/010/011/100/110). In this mode thevalid IFO2-IFO0 settings are: 000, 001, 010 and 111.

b) DVB mode (required settings: FMR = 0 and IFA/IFB/IFC = 101 or 111). In this mode the valid IFO2-IFO0 settingsare: 000, 011, 100, 110 and 111. The mixed-down DVB signals are now available at the outputs (DVBP/Nindicates a balanced output, DVPSE a single ended output).

c) FM radio mode (required settings: FMR = 1 and IFA/IFB/IFC = 101 or 111). The valid IFO2-IFO0 settings are thesame as for the DVB mode.

IFO2 IFO1 IFO0STEREO and AV STEREO versions MONO versions

DESCRIPTIONPIN 43 PIN 44 PIN 43

0 0 0 mute mute mute high ohmic output

0 0 1 IFOUT mute IFOUT IF output without sound trap / group delay

0 1 0 IFOUT + sndtrap mute IFOUT + sndtrap IF output with sound trap / group delay

0 1 1 DVBP / FMRO DVBN / FMRO DVBSE / FMRO DVB output or FM radio output

1 0 0 DVBSE / FMRO mute DVBSE / FMRO DVB output or FM radio output

1 1 0 mute DVBSE / FMRO DVBSE / FMRO DVB output or FM radio output

1 1 1 black DC black DC black DC black level DC output

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CONFIDENTIAL

Table 95 No Red reduction during blue stretch

Table 96 Gain from audio inputs to audio outputs

Table 97 Radio Data System (RDS)

Table 98 Activate mono-FM demodulator (in “stereo”versions)

Table 99 Window select for FM demodulator

Table 100 Gain FM demodulator

Table 101Selection QSS out or AM out

Table 102 Sound mute

Note

1. The sound enhancer is active only during FM sound. Itlimits the noise which is generated by the digitalacquisition circuit. For AM sound only the positions“mute off” and “mute on” should be used.

Table 103FM demodulator at 10.7 MHz

Table 104Centre frequency FM demodulator/sound trap

Table 105Enable AVL function on East-West output pin

Table 106 Mode of Quasi Split Sound amplifier

NRR CONDITION

0 red reduction active

1 not active

DSG GAIN

0 0 dB

1 +6 dB

RDS CONDITION

0 not active

1 demodulated audio signal supplied to RDSdecoder

MONO MODE

0 mono-FM demodulator not active

1 mono-FM demodulator active

FMWS1 FMWS0 WINDOW

0 0 100 kHz

0 1 225 kHz

1 0 450 kHz

1 1 900 kHz

AGN MODE

0 normal operation1 gain +6 dB

AM MODE

0 QSS output selected

1 AM output selected

SM1 SM0 CONDITION

0 0 mute off

0 1 sound enhancer; note 1

1 0 mute on

FMD MODE

0 frequency FM demodulator determined by thebits FMA, FMB and FMC

1 frequency FM demodulator 10.7 MHz

FMC FMB FMA FM DEMOD. SOUND TRAP

0 0 0 5.5 MHz 5.5 MHz

0 0 1 6.0 MHz 6.0 MHz

0 1 0 4.5 MHz 4.5 MHz

0 1 1 6.5 MHz 6.5 MHz

1 0 0 5.74 MHz 5.5 MHz

1 0 1 7.90 MHz −1 1 0 4.72 MHz 4.5 MHz

1 1 1 9.60 MHz −

AVLE CONDITION

0 East-West functionality active

1 AVL functionality active

QSS MODE

0 QSS amplifier not active, input of sound PLLconnected to vision IF amplifier output

1 QSS amplifier active, output connected toQSSO or to input sound PLL (via FMI bit)

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CONFIDENTIAL

Table 107 Bypass of sound bandpass filter

Table 108 Auto Volume Levelling

Table 109 FM radio function enabled

Table 110 Connection of output of QSS amplifier

Table 111 FM mono demodulator sensitivity

Table 112 Maximum audio gain when AVL is active

Table 113 SSIF input pin selection

Table 114 Activate complete mono channel (in “stereo”versions)

Table 115 Bypass sound bandpass filter section 2

Table 116 Audio output signal for AM sound

Table 117 Head phone volume control

Table 118 Sync Performance Trick mode

Table 119 Sound mute loudspeaker output

Table 120 Audio select for SCART/CINCH output, note 1

Note

1. These bits are only valid for stereo and AV stereoversions

2. Only valid in versions with Audio DSP

BPB CONDITION

0 normal operation

1 sound bandpass filter bypassed

AVL MODE

0 not active

1 active

FMR MODE

0 TV mode

1 FM radio mode

FMI MODE

0 output connected to QSSO output1 output connected to sound PLL circuit

FMS MODE

0 normal operation

1 reduced sensitivity

AVLM MODE

0 normal gain

1 maximum gain

ESSIF MODE

0 SSIF at pin 33

1 SSIF at pin 53

CMCA MODE

0 stereo mode

1 mono LF path only HP left

BPB2 MODE

0 bandpass filter active

1 bandpass filter bypassed

AMLOW CONDITION

0 normal output signal amplitude

1 output signal amplitude reduced with 6 dB

HPVC CONDITION

0 volume control not active

1 volume control active

SPT MODE

0 influence S/N detector on phi1 loop disabled

1 influence S/N detector on phi1 loop enabled

SMLS CONDITION

0 normal operation

1 output muted

SO2 SO1 SO0 AUDOUTSL/R

0 0 0 FM MONO / AM0 0 1 AUDIOIN20 1 0 AUDIOIN30 1 1 AUDIOIN41 0 0 AUDIOIN51 0 1 fixed output of Audio DSP,

note 21 1 0 vol. contr. output Audio DSP,

note 21 1 1 mute

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Table 121 Selection of audio output signal on AUDEEMpin, note 1 (Mono versions)

Note

1. This function can be activated only when the MOD bitis 0.

Table 122 Audio select for Audio DSP input

Table 123 Audio select; note 1

Note

1. The function of the HPO2/0 bits depends on the ICversion. For stereo versions with Audio DSP these bitscontrol the input signal selection for the Headphonechannel. For stereo versions without Audio DSP andfor mono versions they control the input signalselection for the speaker output channel.

2. Only valid in versions with Audio DSP

Table 124 CVBS/PIP output

Table 125 Video input selection

Notes for table 124 and 125

1. This command is valid only when the CVBSX (Y/CX)function is activated via the YC-bit.

Table 126 Comb filter mode

Table 127 CVBS2 input signal selection

E2D MODE

0 deemphasis (front-end audio available)

1 selected audio signal available

SAS2 SAS1 SAS0 SELECTION

0 0 0 FM MONO / AM0 0 1 AUDIOIN20 1 0 AUDIOIN30 1 1 AUDIOIN41 0 0 AUDIOIN51 0 1 spare1 1 0 spare1 1 1 mute

HPO2 HPO1 HPO0 AUDOUTHPL/R

0 0 0 FM MONO / AM0 0 1 AUDIOIN20 1 0 AUDIOIN30 1 1 AUDIOIN41 0 0 AUDIOIN51 0 1 fixed output of Audio DSP,

note 21 1 0 vol. contr. output Audio DSP,

note 21 1 1 mute

CS1A CS1B CS1C CS1D SELECTED SIGNALS

0 0 0 0 mute

0 0 0 1 CVBS1 (internal from IF)

0 0 1 0 CVBS2

1 0 1 0 Y2 + C3

0 0 1 1 CVBS3

1 0 1 1 Y3 + C3

0 1 0 0 CVBS4

1 1 0 0 Y4 + C4

0 1 0 1 CVBSX; note 1

1 1 0 1 YX + CX; note 1

INA INB INC IND SELECTED SIGNALS

0 0 0 1 CVBS1 (internal from IF)

0 0 1 0 CVBS2

1 0 1 0 Y2/C3

0 0 1 1 CVBS3

1 0 1 1 Y3/C3

0 1 0 0 CVBS4

1 1 0 0 Y/C4

0 1 0 1 CVBSX; note 1

1 1 0 1 Y/CX; note 1

CFA0 COMB FILTER

0 adaptive 4H/2H comb filter for PAL/NTSC

1 comb filter off

CV2 MODE

0 CVBS2 input directly selected

1 CVBS2 input signal is supplied sound trapand group delay correction circuit. Theselection of this signal is realised by means ofthe CS1A-D and INA-D bits (setting 0001).

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CONFIDENTIAL

Table 128 Function of IFVO/SVO/CVBSI pin

Note

1. When this function is selected the setting of the CV2bit is neglected. The signal is supplied to the soundtrap and group delay correction circuit. The selectionof this signal is realised by means of the CS1A-D andINA-D bits (setting 0001).

Table 129 Active input for sync separator, note 1

Note

1. Sync coupled to the selected CVBS input should onlybe used when the external RGB signal contains nosync pulse.

Table 130 Control of coupling between vision IF amplifierand synchronisation circuit

Table 131 Coupling between vision IF amplifier andsynchronisation circuit

Table 132 Y-delay adjustment

Table 133 Colour decoder mode, note 1

Note

1. The decoder frequencies for the various standards areobtained from an internal clock generator which issynchronised by a 24.576 MHz reference signal whichis obtained from the µ-Controller clock generator.

a) The nominal standard frequencies are:

b) A: 4.433619 MHz

c) B: 3.582056 MHz (PAL-N)

d) C: 3.575611 MHz (PAL-M)

e) D: 3.579545 MHz (NTSC-M)

The nominal oscillator frequency may have a slightlydifferent value (see also Table 249)

2. In the auto modes (CM3-CM0 setting 1000 and 1100)PAL with frequency D and NTSC with frequencies Band C are not possible.

Table 134 PAL-SECAM/NTSC matrix

Table 135 NTSC matrix

SVO1 SVO0 PIN FUNCTION

0 0 wrong function, do not use

0 1 selected CVBS available at output

1 0 pin used as CVBS input; note 1

1 1 wrong function, do not use

SYS MODE

0 sync coupled to YSYNC input

1 sync coupled to selected CVBS/Y input

VDXEN MODE

0 coupling controlled by the input signalselection bits (INA-IND)

1 coupling controlled by the VDX bit

VDX MODE

0 the circuits are coupled

1 the circuits are not coupled

YD0 to YD3 FSC = 4.43 MHz FSC = 3.58 MHz

YD3 YD3 × 220 ns + YD3 × 280 ns +

YD2 YD2 × 110 ns + YD2 × 140 ns +

YD1 YD1 × 55 ns + YD1 × 70 ns +

YD0 YD0 × 30 ns YD0 × 30 ns

CM3 CM2 CM1 CM0 DECODER MODE FREQ

0 0 0 0 PAL/NTSC/SECAM A

0 0 0 1 PAL/SECAM A

0 0 1 0 PAL A

0 0 1 1 NTSC A

0 1 0 0 SECAM

0 1 0 1 PAL/NTSC B

0 1 1 0 PAL B

0 1 1 1 NTSC B

1 0 0 0 PAL/NTSC/SECAM(2) ABCD

1 0 0 1 PAL/NTSC C

1 0 1 0 PAL C

1 0 1 1 NTSC C

1 1 0 0 PAL/NTSC (Tri-Norma) (2) BCD

1 1 0 1 PAL/NTSC D

1 1 1 0 PAL D

1 1 1 1 NTSC D

MAT MATRIX POSITION

0 adapted to standard

1 PAL matrix

MUS MATRIX POSITION

0 Japanese matrix

1 USA matrix

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CONFIDENTIAL

Table 136 Automatic colour limiting

Table 137 Chroma bandpass centre frequency

Table 138 SECAM B-Y black level offset adjustment

Table 139 PAL/NTSC ident sensitivity (burst amplitude atstrong signal (typical value)

Table 140 Centre frequency of cloche filter

Table 141 Chroma trap mode

Table 142 Bypass of chroma base-band delay line

Table 143 Forced Colour-On

Table 144 Setting duty cycle of horizontal drive signal,note 1 on page 119

Note

1. The setting of the duty cycle of the horizontal drivesignal can only be adapted when the IC is in the‘stand-by’ mode (STB = 0)

Table 145 Synchronization of OSD/TEXT display

Table 146 Phase 1 (ϕ1) time constant

Table 147 Synchronization mode

Table 148 Stand-by

Table 149 Source of CSO signal for teletext decoder

ACL COLOUR LIMITING

0 not active

1 active

CB CENTRE FREQUENCY

0 FSC

1 1.1 × FSC

SBO1 SBO0 OFFSET

0 0 + 4 kHz

0 1 + 1 kHz

1 0 − 1 kHz

1 1 − 4 kHz

CHSE1 CHSE0 SENSITIVITY

0 0 −34 dB

0 1 −37 dB

1 0 −41 dB

1 1 −46 dB

CLO CENTRE FREQUENCY

0 4.29 MHz

1 4.33 MHz

DTR MODE

0 single chroma trap

1 dual chroma trap, more suppression but lessbandwidth

BPS DELAY LINE MODE

0 active

1 bypassed

FCO CONDITION

0 off

1 on

SDC CONDITION

0 duty cycle 55:45

1 duty cycle 60:40

HP2 µ-CONTROLLER COUPLED TO

0 ϕ1 loop

1 ϕ2 loop

FOA FOB MODE

0 0 normal

0 1 slow

1 0 OSD mode (very slow)

1 1 fast

POC MODE

0 active

1 not active

STB MODE

0 stand-by

1 normal

HTXT MODE

0 CSO derived from dedicated sync separator

1 CSO derived from main sync separator

2003 Nov 11 120



CONFIDENTIAL

Table 150 Mode of ϕ1 loop

Table 151 Increased wide blanking

Table 152 Disable reference oscillator check in the SUPoutput bit (see also Table 234)

Table 153 Forced slicing level for vertical sync

Table 154 Switch-off in vertical overscan

Table 155 Forced field frequency

Table 156 Interlace

Table 157 Vertical divider mode

Table 158 Function of VGUARD/SWIO pin

Table 159 Mode of LED driver / switch output

Table 160 Slicing level sync separator

Table 161 Source selection for video identification

Table 162 Vertical scan disable

VID MODE

0 ϕ1 loop dependent on the video ident system

1 ϕ1 loop only dependent on FOA/FOB or POCbits

WBI MODE

0 normal mode

1 wide blanking range adapted to Doublewindow mode

RED CONDITION

0 reference oscillator check enabled

1 reference oscillator check disabled

FSL SLICING LEVEL

0 slicing level dependent on noise detector

1 fixed slicing level of 60%

OSO MODE

0 Switch-off undefined

1 Switch-off in vertical overscan

FORF FORS FIELD FREQUENCY

0 0 auto (60 Hz when line not in sync)

0 1 60 Hz

1 0 keep last detected field frequency

1 1 auto (50 Hz when line not in sync)

DL STATUS

0 interlace

1 de-interlace

NCIN VERTICAL DIVIDER MODE

0 normal operation

1 switched to search window

VGM1 VGM0 FUNCTION

0 0 vertical guard

0 1 vertical guard combined with LEDdrive output

1 0 switch output (0 - 5 V)

1 1 input port, detector output via NDFbit

LED MODE

0 LED drive off / switch output HIGH

1 LED drive on / switch output LOW

SSL SLICING LEVEL

0 50%

1 30%, direction top sync

SD2 SD1 SD0 VIDEO INPUT

0 0 0 selected input signal (viaINA-IND bits)

0 0 1 CVBS1 (internal from IF)0 1 0 CVBS20 1 1 CVBS3/Y31 0 0 CVBS4/Y41 0 1 G/Y-2 (CVBS/Y-X)1 1 0 G/Y-3

VSD SETTING

0 normal operation

1 vertical scan switched off

2003 Nov 11 121



CONFIDENTIAL

Table 163 Black current measuring lines in overscan (forvertical zoom setting < 1)

Table 164 Disable flash protection

Table 165 X-ray detection

Table 166Service blanking

Table 167 Adjustment Vg2 voltage

Table 168 Enable vertical guard (RGB blanking)

Table 169 EHT tracking mode

Table 170 Read-out deflection timer

Table 171 Scan Velocity Modulation output signal (1)

Note

1. Input signal: 1 MHz with an amplitude of 350 mVP-P

Table 172 Macro Vision Keying

Table 173 Fixed beam current switch-off

Table 174 Extended vertical blanking

Table 175 Amplitude/polarity of YUV interface signal

Note

1. YPRPB input: (colour bar 100% saturation):

Y = +1.0 VP-P; PR = +0.7 VP-P; PB = +0.7 VP-P.

2. YUV input: (colour bar 75% saturation):

Y = 1.4 VP-P; U = −1.33 VP-P; V = −1.05 VP-P.

OSVE MODE

0 normal operation

1 measuring lines in overscan

DFL MODE

0 flash protection active

1 flash protection disabled

XDT MODE

0 protection mode, when a too high EHT isdetected the receiver is switched to stand-byand the XPR-bit is set to 1

1 detection mode, the receiver is not switchedto stand-by and only the XPR-bit is set to 1

SBL SERVICE BLANKING MODE

0 off

1 on

AVG MODE

0 normal operation

1 Vg2 adjustment (WBC and HBC bits in outputbyte 01 can be read)

EVG VERTICAL GUARD MODE

0 not active

1 active

HCO TRACKING MODE

0 EHT tracking only on vertical

1 EHT tracking on vertical and EW

DEFL MODE

0 read-out disabled

1 read-out enabled

SVMA OUTPUT SIGNAL AMPLITUDE

0 600 mVP-P

1 1200 mVP-P

MVK MODE

0 Macro vision keying not active

1 Macro Vision keying active

FBC MODE

0 switch-off with blanked RGB outputs

1 switch-off with fixed beam current

EVB SETTING

0 normal vertical blanking

1 extended vertical blanking in the upper andlower part of the picture; see also Fig. 82

INTF INTERFACE SIGNAL AMPLITUDE

0 signal according to YPRPB standard; note 1

1 signal according to YUV standard; note 2

2003 Nov 11 122



CONFIDENTIAL

Table 176 Enable gain loop in the CCC system

Table 177 Selection high current in CCC system

Table 178 Black current stabilization

Table 179 Cathode drive level

Table 180 Enable fast blanking of RGB/YPRPB-3 input

Table 181 Enable fast blanking of RGB/YPRPB-2 input

Table 182 Enable digital interface

EGL MODE

0 control loop not active

1 control loop active

SLG1 SLG0 MODE

0 0 current level 220 µA




AKB MODE

0 active

1 not active

CL3 - CL0 CONTROL

0 gain −3 dB

7 nominal value

F gain +3 dB

IE3 FAST BLANKING

0 not active

1 active

IE2 FAST BLANKING

0 not active

1 active

DINT MODE

0 not active

1 active

Table 183 RGB/YUV/YPRPB switching options

Notes

1. In this position the V output is changed to general purpose switch output (SWO1). This output is controlled by theSWO1 bit in subaddress 4AH.

2. The amplitude and polarity of the input and output signals are determined by the setting of the INTF bit

3. YUV input: (colour bar 75% saturation): Y = 1.4 VP-P; U = −1.33 VP-P; V = −1.05 VP-P.

4. YPRPB input: (colour bar 100% saturation): Y = +1.0 VP-P; PR = +0.7 VP-P; PB = +0.7 VP-P.

5. When both inputs are activated (by means of IE2/IE3 or fast blanking) the input with the highest priority is dependenton the selected option.

YC YUV2 YUV1 YUV0 RGB/YPRPB-3 INPUTRGB/YUV/YPRPB-2 INPUT ORYUV/YPRPB INTERFACE OR

CVBS (Y/C) INPUT

INPUT WITHHIGHEST

PRIORITY (5)

0 0 0 0 RGB with fast insertion RGB with fast insertion; note 1 RGB-3

0 0 0 1 RGB with fast insertion interface; note 2

0 0 1 0 RGB with fast insertion YUV with fast insertion; notes 1 + 3 YUV-2

0 0 1 1 RGB with fast insertion YPRPB input; notes 1+ 4 RGB-3

0 1 0 0 YPRPB input; note 4 YPRPB input; notes 1 + 4 YPRPB-3

0 1 0 1 YPRPB input; note 4 RGB with fast insertion; note 1 RGB-2

0 1 1 0 YPRPB input; note 4 interface; note 2

0 1 1 1 YPRPB input; note 4 YUV with fast insertion; notes 1 + 3 YUV-2

1 0 0 0 RGB with fast insertion CVBS-X or Y/C-X input RGB-3

1 1 1 1 YPRPB input; note 4 CVBS-X or Y/C-X input YPRPB-3

2003 Nov 11 123



CONFIDENTIAL

Table 184 RGB blanking mode

Table 185 Gamma control

Table 186 DC transfer ratio of luminance signal

Table 187 Delay of clamp pulse

Table 188 Control sequence of beam current limiting

Table 189 Off-set control on UV input signals

Table 190 Peak White limiting

Table 191 RGB blanking

Table 192 Blanking of RGB outputs

Table 193 Black stretch

Table 194 Black Stretch Depth (A-A in Fig. 72)

Table 195 Black area to switch off the black stretch

Table 196 Dynamic skin control on/off

Table 197 Gamma control and white stretch settings

Note

1. This figure indicates the maximum increase of the gainin the lower part of the characteristic (slope of thecurve, see Fig. 74).

2. The APL (Average Picture Level) figure indicates theaverage luminance level at which the white stretchcharacteristic starts shifting from maximum stretchingto the linear curve. At an increase of the APL of about13% the curve is linear (see also Fig. 75).

HBL MODE

0 normal blanking (horizontal flyback)

1 wide blanking

GAM CONDITION

0 not active

1 active

TFR TRANSFER RATIO

0 no black level shift due to video content

1 black level shift of 10 IRE for complete whitepicture

CLD DELAY

0 normal timing

1 extra delay of 400 ns

CBS MODE

0 normal operation (contrast → brightness)1 control on contrast and brightness in parallel

OUV MODE

0 off-set control on R/G output signals

1 off-set control on U/V input signals

PWL MODE

0 peak white limiting circuit not active

1 peak white limiting circuit active

RBL RGB BLANKING

0 not active

1 active

RGBL CONDITION

0 normal operation

1 RGB outputs blanked continuously

BKS BLACK STRETCH

0 off

1 on

BSD MODE

0 15 IRE

1 30 IRE

AAS MODE

0 10% back ground needed

1 20% back ground needed

DSK MODE

0 off

1 on

WS1 WS0 EXPANSION (1) APL (2)

0 0 0% −0 1 6% 17%

1 0 8% 25%

1 1 12% 28%

2003 Nov 11 124



CONFIDENTIAL

Table 198 Blue stretch

Table 199 Tint control on UV signals

Table 200 Black level offset on Blue channel

Table 201 High contrast in Text mode

Table 202 Fast insertion mode

Table 203 Forced mode of RGB/YUV/YPRPB inputs

Table 204 Blanking of blue and green output

Table 205 Low level of beam current limiter

Table 206 Dynamic skin tone angle

Table 207 Ratio pre- and aftershoot

Table 208 Ratio of positive and negative peaks

Table 209 Video dependent coring (peaking)

Table 210 Coring on SVM

BLS BLUE STRETCH MODE

0 off

1 on

TUV MODE

0 not active

1 active

OFB MODE

0 offset control on Red channel

1 offset control on Blue channel

HCT MODE

0 normal operation

1 RGB output signal increased with 3 dB

FINM MODE

0 normal operation

1 fast insertion active behind the digitalinterface

FIN MODE

0 normal mode

1 selected input forced on

BLBG CONDITION

0 normal operation

1 blanking of the blue and green channel

LLB CONDITION

0 internal bias current of BCL pin switched off

1 internal bias current of BCL pin of 0.5 mAswitched on

DSA CONDITION

0 117

1 123

RPA1 RPA0 RATIO

0 0 1 : 1

0 1 1.5 : 1

1 0 2 : 1

RPO1 RPO0 RATIO

0 0 1 : 10 1 1 : 1.31 0 1 : 1.71 1 1 : 0.7

COR1 COR0 SETTING

0 0 off

0 1 coring active between 0 and 20 IRE



CRA0 SETTING

0 8%

1 15%

2003 Nov 11 125



CONFIDENTIAL

Table 211 Parabola on SVM output; note 1

Note

1. The Scan Velocity Modulation output can be madedepend on the horizontal position on the screen. Thepositions A, B and C are indicated in Fig. 77 on page231.

Table 212 Delay of RGB output to SVM output

Table 213 Amplitude of SVM output, note 1

Note

1. The output signal amplitudes are specified for an inputsignal amplitude that is 50% of the nominal value.

Table 214 Scan Velocity Modulation mode

Table 215 Gain selection of DISCO

Table 216 Stabilization of the 1.8 V supply voltage; note 1

Note

1. The 1.8 V supply voltage is derived from the internallygenerated 2.5 V supply rail by means of an emitterfollower. The control loop of this 2.5 V supply can beclosed taking into account the spread of this emitterfollower (DDLE = 1). In this way a very stable 1.8 Vsupply is guaranteed. It is also possible to stabilise the2.5 V supply by means of an internal control loop(DDLE = 0).

Table 217 Soft start-up mode

SPR2 SPR1 SPR0SETTING AT POSITIONS A, B

AND C (dB)

A B C

0 0 0 0 0 00 0 1 0 −3 −30 1 0 −3 0 00 1 1 0 0 −31 0 0 −3 −3 01 0 1 0 −3 −61 1 0 −6 −3 0

SVM0 to SVM2 DELAY SETTING

SVM2 SVM2 × 100 ns +SVM1 SVM1 × 50 ns +SVM0 SVM0 × 25 ns

VMA1 VMA0 SETTING

0 0 off0 1 0.9 VP-P

1 0 1.3 VP-P

1 1 1.8 VP-P

SMD1 SMD0 MODE

0 0 off

0 1 SVM on video

1 0 SVM on teletext or OSD

1 1 SVM on video or OSD (fastswitching)

DISG MODE

0 normal gain

1 gain increased with 6 dB

DDLE MODE

0 control loop 2.5 V internally

1 control loop 2.5 V externally

DSS MODE

0 normal operation

1 soft start-up disabled

2003 Nov 11 126



CONFIDENTIAL

Table 218 Condition flyback input pin (FBISO)

Table 219 Output switch (SWO1)

Table 220 Condition AVL/SWO/SSIF/REFO/IFREFI

Table 221 Y-delay bypass mode (note 1)

Note

1. This mode can only be activated in the YC-mode(INA=1).

CSY CONDITION

0 normal flyback input

1 composite H/V timing output

SWO1 CONDITION

0 output is ‘LOW’

1 output is ‘HIGH’

CMB2 CMB1 CMB0 CONDITION

0 0 0 AVL and

SIF to FM mono demodulator

SIF to stereo demodulator

0 0 1 output voltage 2.1 V + subcarrier(REFO)

0 1 0 SWO output voltage low (<0.8 V)

0 1 1 SWO output voltage high (>4.5 V)

1 0 0 external reference carrier for DVBmix-down (REFIN)

1 0 1 SSIF to digital stereo decoder.

SSIF to FM mono demodulator.

1 1 0 SSIF to digital stereo decoder.

SIF to FM mono demodulator.

1 1 1 SSIF to FM mono demodulator.

SIF to digital stereo decoder.

BPYD CONDITION

0 Y-delay bypassed

1 Y-delay enabled

2003 Nov 11 127



CONFIDENTIAL

Explanation output control data TV-processor

Table 222 Power-on-reset

Table 223 Video input signal identification

Table 224 IF-PLL lock indication

Table 225 Phase 1 (ϕ1) lock indication

Table 226Colour decoder mode, note 1

Note

1. The values for the various frequencies can be found inthe note of table 133.

Table 227 X-ray protection

Table 228 Output vertical guard

Table 229 Field frequency indication

Table 230 Condition vertical divider, note 1

Note

1. More information is given in note 61 on page 214

Table 231 Indication black current stabilization; note 1

Note

1. This function is valid only during the adjustment of theVg2 voltage (AVG = 1)

Table 232 Condition black current loop

Table 233 Comb filter mode

POR MODE

0 normal

1 power-down

SID CONDITION

0 no video signal identified

1 video signal identified

LOCK INDICATION

0 not locked

1 locked

SL INDICATION

0 not locked

1 locked

CD3 CD2 CD1 CD0 STANDARD

0 0 0 0 no colour standard identified

0 0 0 1 NTSC with freq. A

0 0 1 0 PAL with freq. A

0 0 1 1 NTSC with freq. B

0 1 0 0 PAL with freq. B

0 1 0 1 NTSC with freq. C

0 1 1 0 PAL with freq. C

0 1 1 1 NTSC with freq. D

1 0 0 0 PAL with freq. D

1 0 1 0 SECAM

XPR OVERVOLTAGE

0 no overvoltage detected

1 overvoltage detected

NDF VERTICAL OUTPUT STAGE

0 OK

1 failure

FSI FREQUENCY

0 50 Hz

1 60 Hz

IVW VERTICAL WINDOW INDICATION

0 vertical sync pulse not in narrow window

1 15 succeeding sync pulses in narrow window

WBC HBC CONDITION

0 0 outside window; current too low

0 1 outside window; current too high

1 X in window

BCF CONDITION

0 black current loop is stabilised

1 black current loop is not stabilised

COMB MODE

0 comb filter not active

1 comb filter active

2003 Nov 11 128



CONFIDENTIAL

Table 234 Supply voltage and reference oscillatorindication

Note

1. When RED = 1 only the supply voltage condition ischecked.

Table 235 Indication tuner AGC

Table 236 Indication RGB-3 input condition

Table 237 Indication RGB-2 input condition

Table 238 Protection of 1.8 V supply voltage

Table 239 Indication FM-PLL in/out window

Table 240 Indication FM-PLL in/out lock

Table 241 Condition vertical divider, note 1

Note

1. More information is given in note 61 on page 214

Table 242 Signal-to-Noise ratio of the demodulated CVBSsignal (IFVO)

Table 243 Output of Y/C detector; note 1

Note

1. The Y/C detector is only active for the CVBS(Y)3/C3,CVBS(Y)4/C4 and CVBS(Y)x/Cx inputs and not for theCVBS(Y)2/C3 input.

SUP CONDITION

0 supply voltage (5 Volt) not present orreference oscillator not OK

1 supply voltage (5 Volt) present and referenceoscillator OK, note 1

AGC CONDITION

0 tuner gain control active

1 no gain control of tuner

IN3 RGB INSERTION

0 no

1 yes

IN2 RGB INSERTION

0 no

1 yes

SUPR SUPPLY VOLTAGE PROTECTION

0 supply voltage OK

1 supply voltage too high

FMW CONDITION

0 FM-PLL in window

1 FM-PLL out of window

FML CONDITION

0 FM-PLL out of lock

1 FM-PLL locked

IVWF VERTICAL WINDOW INDICATION

0 vertical sync pulse not in narrow window

1 7 succeeding sync pulses in narrow window

SN2 SN1 SN0 CONDITION

0 0 0 S/N ≤ 18 dB

0 0 1 S/N ≥ 18 dB and ≤ 25 dB

0 1 0 S/N ≥ 25 dB and ≤ 28 dB

0 1 1 S/N ≥ 28 dB and ≤ 31 dB

1 0 0 S/N ≥ 31 dB and ≤ 37 dB

1 0 1 S/N ≥ 37 dB and ≤ 40 dB

1 1 0 S/N ≥ 40 dB and ≤ 43 dB

1 1 1 S/N ≥ 43 dB

YCD CONDITION

0 CVBS signal at input

1 Y/C signal at input

2003 Nov 11 129



CONFIDENTIAL

Table 244 AFC output (two-complement notation); 25 kHzper step

Table 245 Indication CCC gain loop

Table 246 Indication “picture tube warm”

Table 247 Read-out CCC registers, see note on Table 76

OUTPUT FREQUENCY DEVIATION

0 no frequency deviation

3C deviation: +1.5 MHz or more

C4 deviation: −1.5 MHz or more

GLOK CONDITION

0 gain loop not yet stabilised

1 gain loop stabilised

PTW CONDITION

0 cathode current below selected current

1 cathode current ≥ selected current

RG6 - RG0GG6 - GG0BG6 - BG0

CRT DRIVE VOLTAGE

0 45 VP-P

40 90 VP-P

7F 180 VP-P

Table 248 Deflection timer read-out

Note

1. IF and sound are operational

DFL4 DFL3 DFL2 DFL1 DFL0 STATE CONDITION

0 0 0 0 0 standby POR situation

0 0 0 0 1 standby Only standby supply is present

0 0 0 1 0 standby Standby supply is present and ‘SUP’ bit = ‘1’, note 1

0 0 1 1 0 slow start Slow start of horizontal output is active when ‘SUP’ bit = ‘1’

0 0 1 0 1 slow start Slow start of horizontal output is active when ‘SUP’ bit = ‘0’

0 1 0 0 0 soft stop Soft stop of horizontal output is active

0 1 1 1 1 operational Slow start of horizontal output is ended, device is operational

2003 Nov 11 130



CONFIDENTIAL

Table 249 Subcarrier oscillator frequency, note 1.

Note

1. The nominal decoder frequencies are obtained froman internal clock generator which is synchronised by a24.576 MHz reference signal from the µ-controllerclock. These frequencies can have a small offset fromthe standard subcarrier frequencies.

The nominal frequencies are:

a) A: 4.433625 MHz

b) B: 3.582000 MHz (PAL-N)

c) C: 3.575625 MHz (PAL-M)

d) D: 3.579563 MHz (NTSC-M)

DECODER FREQUENCY

DISC9-DISC2 A B C D

00000000 -750 -750 -750 -750

10000000 nom. nom. nom. nom.

11111111 +750 +750 +750 +750

2003 Nov 11 131



CONFIDENTIAL

GENERAL DESCRIPTION OF THE TV SOUNDPROCESSOR

The TV Sound Processor is a digital TV sound processorfor analog multi-channel sound systems in TV sets. It isbased on a 24 bit DSP and designed to support severalapplications.

A new easy-to-use control concept was implemented foreasiest configuration programming of the very complexfunctionality of the TV Sound Processor. Pre-definedsetups are available for all implemented sound processingmodes. A loudspeaker switching concept allows it to adaptthe pre-defined setups to the specific loudspeakerapplication.The built-in intelligence for pre-definedstandards and Auto Standard Detection (ASD) allows aneasy setup of the demodulator and decoder part.

The control concept for the audio processor is based onthe following new features:

• Pre-defined setups for the sound processing modes likeDolby® Pro Logic® and Virtual Dolby® Surround (422,423)

• Flexible configuration of audio outputs to theloudspeaker configuration with an additional outputcrossbar

• Master volume function

The control concept for the demodulator and decoder(DEMDEC) is based on the following new features:

• Easy demodulator setup for all implemented standardswith Demodulator and Decoder Easy Programming(DDEP) for a pre-selected standard or combined withAuto Standard Detection (ASD) for automatic detectionof a transmitted standard

• Automatic decoder configuration and signal routingdepending on the selected or detected standard

• FM overmodulation adaptation option to avoid clippingand distortion

Supported standards

The multistandard capability of the TV Sound Processorcovers all terrestrial TV sound standards, FM Radio andsatellite FM.

The AM sound of L/L' standard is normally demodulated inthe 1st sound IF. The resulting AF signal has to be enteredinto the mono audio input of the TV Sound Processor. Asecond possibility is to use the AM demodulator in theDEMDEC part, however this may result in limitedperformance.

Korea has a stereo sound system similar to Europe. It issupported by the TV Sound Processor. Differencesinclude deviation, modulation contents and identification. Itis based on M standard.

Other features of the DEMDEC are:

• M/BTSC and N standards supported

• M/Japan (EIAJ) supported

• FM Radio stereo decoding

• Alignment-free, fully digital system

• For BTSC full dbx® performance

• SAP demodulation (without dbx®) simultaneously withstereo decoding, or mono plus SAP with dbx®

• Line/pilot frequency selectable from 15.734 kHz and15.625 kHz (or automatic detection / auto search)

• High selectivity for pilot detection, high robustnessagainst high-frequent audio components

• Pilot lock indicator

• SAP detector

• Separate noise detectors for stereo and SAP withadjustable threshold levels, hysteresis, and automutefunction

An overview of the supported standards and soundsystems and their key parameters is given in the followingtables.

The analog multi-channel sound systems (A2, A2+ andA2*) are sometimes also named 2CS (2 carrier systems).



2003 Nov 11 132

CONFIDENTIAL

ANALOG 2-CARRIER SYSTEMS

Table 250 Frequency modulation

Table 251 Identification for A2 systems

2-CARRIER SYSTEMS WITH NICAMTable 252 NICAM standards

Notes

1. See 'EBU specification' or equivalent specification.

STANDARDSOUNDSYSTEM

CARRIERFREQUENCY

(MHz)

FM DEVIATION(kHz)

NOM./MAX./OVER

MODULATION BANDWIDTH/DE-EMPHASIS

(kHz/µs)SC1 SC2

M mono 4.5 15/25/50 mono − 15/75

M A2+ 4.5/4.724 15/25/50 1⁄2(L + R) 1⁄2(L − R) 15/75 (Korea)

B/G A2 5.5/5.742 27/50/80 1⁄2(L + R) R 15/50

I mono 6.0 27/50/80 mono − 15/50

D/K (1) A2* 6.5/6.258 27/50/80 1⁄2(L + R) R 15/50

D/K (2) A2* 6.5/6.742 27/50/80 1⁄2(L + R) R 15/50

D/K (3) A2* 6.5/5.742 27/50/80 1⁄2(L + R) R 15/50

PARAMETER A2/A2* A2+ (KOREA)

Pilot frequency 54.6875 kHz = 3.5 × line frequency 55.0699 kHz = 3.5 × line frequency

Stereo identificationfrequency

Dual identification frequency

AM modulation depth 50% 50%

STANDARD

SC1

SC2(MHz)

NICAMDE-EMPHASIS

ROLL-OFF(%)

NICAMCODINGFREQUENCY

(MHz)TYPE

MODULATION

INDEX(%)

NOM./MAX.

DEVIATION(kHz)

NOM./MAX./OVER

B/G 5.5 FM − 27/50/80 5.85 J17 40 note 1

I 6.0 FM − 27/50/80 6.552 J17 100 note 1

D/K 6.5 FM − 27/50/80 5.85 J17 40 note 1

L 6.5 AM 54/100 − 5.85 J17 40 note 1

117.5 Hz line frequency133

-------------------------------------= 149.9 Hz line frequency105

-------------------------------------=

274.1 Hz line frequency57

-------------------------------------= 276.0 Hz line frequency57

-------------------------------------=



2003 Nov 11 133

CONFIDENTIAL

SATELLITE SYSTEMS

An important specification for satellite TV reception is the Astra specification. The TV Sound Processor is suited for thereception of Astra and other satellite signals.

Table 253 FM satellite sound

Notes

1. For other satellite systems, frequencies of, for example, 5.80, 6.60 or 6.65 MHz can also be received. A de-emphasisof 60 µs, or in accordance with J17, is available.

2. m/st/d = mono or stereo or dual language sound.

3. Adaptive de-emphasis = compatible to transmitter specification.

CARRIER TYPECARRIER

FREQUENCY(MHz)

MODULATIONINDEX

MAXIMUMFM DEVIATION

(kHz)MODULATION

BANDWIDTH/DE-EMPHASIS

(kHz/µs)

Main 6.50(1) 0.26 85 mono 15/50(1)

Sub 7.02/7.20 0.15 50 m/st/d(2) 15/adaptive(3)






2003 Nov 11 134

CONFIDENTIAL

BTSC/SAP, JAPAN (EIAJ) AND FM RADIO SYSTEMS

Table 254 Frequency modulation

*: not applicable due to dbx® noise reduction

Table 255 Identification for BTSC/SAP, Japan (EIAJ) and FM Radio systems

STANDARDSOUNDSYSTEM

CARRIERFREQUENCY

(MHz)

FM DEVIATION(kHz)

NOM./MAX./OVER

MODULATION BANDWIDTH/DE-EMPHASIS

(kHz/µs)SC1

M mono 4.5 15/25/50 mono 15/75

M BTSC 4.5 50 max MPX (FM/AM) 14/n.a.*

SAP 5fh=78,67kHz 15 max SAP (FM) 8/n.a.*

M Japan 4.5 15/25/50 MPX (FM/FM) 15/50

FM Radio stereo 4.5...10.7 40/75/150 MPX (FM/AM) 15/75 or 15/50

PARAMETER PILOT TONE FREQUENCY

BTSC 1fh=15.734 kHz

Japan/(EIAJ) 3.5fh= 55,069 kHz

FM Radio 19kHz



2003 Nov 11 135

CONFIDENTIAL

FUNCTIONAL DESCRIPTION SOUND PROCESSOR

The UOCIII TV Sound Concept

The UOCIII sound concept is implemented over the video processor and TCG-microcontroller.

Fig. 41 is showing this concept.

Only relevant blocks, functions and signal flows for sound are given. For details of the application see UOCIII applicationnotes.

The tuner receives a RF signal and converts it to IF. Via appropriate SAW filters the SIF signal is delivered to the QSSstage of the video processor and if channels according to standard L/L’ are received also to the AM demodulator. TheQuasi Split Sound demodulation generates the SSIF or intercarrier signal. By the SSIF switch it is possible to choosebetween the internally derived intercarrier and an external second SIF (2NDSIF EXT), e.g. an intercarrier coming from aPIP frontend. In other applications a 10.7 MHz radio IF or satellite FM may be connected to this input. The selected SSIFpasses some anti alias filtering, is amplified in an AGC amplifier (SSIF AGC) and is then converted from analogue todigital (SSIF ADC).

The audio signal out of the AM demodulator is connected to the analogue crossbar at the video processor. All other inputsto this multiplexer/audio switch come from external, either from a PIP frontend or SCART/CINCH (AUD IN x) or the DACoutput signals from the digital controller. The audio AD converters are digitising the audio signals foreseen for furtherdigital processing. One stereo output (AUDOUT S) is available for connections to SCART/CINCH sockets.

Fig.41 UOCIII Sound Concept

(only relevant blocks, functions and signal flow for sound are shown)

RF1TUNER

+ SAWfilters

SSIF

SW

SSIF

AGC

DEMDEC

HW/DSP

AUDIO IN 4

AUDIO IN 3

AUDIO IN 2

FMMONO/AM

AudioADC

DAC1

I2S proc./interface

DAC2

AUDOUTS L,R

AUDOUTLS L,R

AUDOUTHP L,R

I2S OUTI2SIN/outSSIF

DAC1PROC

LSPROC

Dig.

Out

put C

ross

barDigital

InputCross-bar

SSIF

ADC

AUXaudiocontr.

I2SDO1

analogue crossbar

Video-proc.part

Dig.Controllerpart

I2SDI1/O I2SDO2

AUDIO IN 5

FM3dB/9dB

-3dB

-3dB

-3dB

-3dB

3dB/9dB

3dB/9dBQSS

orVIF

AMSIFIN

VIFIN

2003 Nov 11 136



CONFIDENTIAL

The sound part on the digital controller consists of thedemodulator/decoder (DEMDEC), a digital input crossbar,the digital audio processing for the loudspeaker and DACchannels, the I2S processing and interfacing, a digitaloutput crossbar as well as the DA conversion.

An auxiliary audio control (volume control, AUX audiocontr.) is available on the video processor. Here it isapplied to the headphone channel.

The part of the concept located in the digital controller willbe described in the next chapters.

Functional Overview Of the digital controller soundpart

The digital controller sound part consists of the SSIF ADC,audio ADCs, DEMDEC HW, the sound DSP core, audioDACs and I2S interface hardware as shown in fig. 42. TheDEMDEC part of the Sound DSP is used for the decoderand partly demodulator tasks. The AUDIO part providesthe sound features, from the level adjust unit up to theoutput crossbar. Audio DACs and I2S hardware areconverting the processed signals to analogue or digitalaudio.

Dig

ital I

nput

Cro

ssba

r

L/A

R/B

MONO

I2S1L IN

I2S1R IN

Noise/Silence

Generator

Audio ControlBMT

AUX2/I2S2 Channel Processing

AUX3/DAC1 Channel Processing

Dolby®Pro Logic®

VDS

Main Channel Processing

SW Channel Processing

Centre Channel Processing

Surround Channel Processing

(L+R)/2

Audio Monitor

I2S1 OUT

I2S2 OUT

DA

C2

I2S

DAC2OUTL

AUX1/I2S1 Channel Processing

Dig

ital O

utpu

t Cro

ssba

r

SAP

I2S

IN

(*)

Sound DSP

I2Sproc

Beeper

DE

MD

EC

Har

dwar

edig.SSIFSSIF

ADC

SSIF

AUDADC

A_ADC1AUDADCIN

A_ADC2

DE

MD

EC

DAC2OUTR

DAC1OUTL

DAC1OUTR

DA

C1

I2S3 OUT(*)

(*) : connected to one pin that can be used alternatively as I2S IN or I2S3 OUT

DA

FO

1D

AF

O2

DA

C1L

DA

C1R

Fig.42 Overview of the UOCIII Sound Functions on the digital controller

The SSIF signal is applied to the SSIF ADC for conversionand is then fed to the DEMDEC hardware processingmainly for demodulation but also some decoding tasks.Remaining decoding is done in the DEMDEC block of theSound DSP. The DEMDEC processing will be described inthe next chapter.

The audio signals (AUD ADC IN) from the analoguecrossbar pass the audio ADC and are fed directly into theAUDIO part of the Sound DSP like the I2S signals, whichis coming from I2S processing hardware. After level adjustall signals from the DEMDEC and the I2S input areavailable at the digital input crossbar. A special input is

2003 Nov 11 137



CONFIDENTIAL

provided for the Noise/Silence Generator needed forDolby® Pro Logic® processing.

The loudspeaker signal processing is performed in themain, SW (subwoofer), centre and surround channelsaccording to the signal type received. Channels AUX1 andAUX2 are provided for I2S signal processing and channelAUX3 is dedicated to DAC1 signal handling.

All channel processing delivers signals to the digital outputcrossbar, which offers the facility to connect each of thechannel signals to the appropriate DACs, or to the I2Soutputs.

In standard TV applications the main channel signal (L, R)will be connected to the DAC2 for reproduction at thespeakers. With multichannel signals centre, surround orsubwoofer channels may be passed to the I2S outputswhere external DACs may be applied. By this it is possibleto build Dolby Normal/Wide, Dolby Phantom Centre orDolby 3 Stereo set-ups and also a VDS423 application.

Details of the audio processing will be described infollowing chapters.

Demodulator and decoder

INTRODUCTION

The TV sound processor provides an easy-to-useprogramming interface and built-in intelligence for thedemodulator and decoder part.

The sound demodulator is able to search for soundcarriers and react to transmission mode changesautonomously, without interaction of the micro controllersoftware.

It is possible for a typical terrestrial TV application to set upthe entire demodulator with transmission of few controlwords.

The control interface still allows access to every detail,called demodulator expert mode, for special applicationssuch as satellite TV, more elaborated search algorithmsetc.

The new TV Sound Processor Demodulator andDecoder Easy Programming (DDEP) interface providesthree possible approaches to setup the demodulator anddecoder parts:

• Auto Standard Detection (ASD)

• Static Standard Selection (SSS)

• Demodulator and Decoder Expert Mode (DDXM)

MIXER

The digitized 2nd SIF input signal is fed to the mixers,which mix one or both input sound carriers down to zero IF.The mixer frequency is derived by the standard setting(Easy Programming) or in the Demodulator and DecoderExpert Mode (DDXM) by a 24-bit control word for eachcarrier. For NICAM demodulation, a feedback signal isadded to the control word of the second carrier mixer toestablish a carrier-frequency loop.

FM AND AM DEMODULATION

An FM or AM input signal is fed via a band-limiting filter toa one of two demodulators that can be used for either FMor AM demodulation. Four filters with different bandwidthare available. The output signal of the first demodulatorcan be used for further demodulation of multiplex signalsused in the BTSC, EIAJ and FM Radio standards.

FM IDENTIFICATION

The identification of the FM sound mode is performed byAM synchronous demodulation of the pilot signal andnarrow-band detection of the identification frequencies.The result is available via the control bus interface. Aselection can be made for three different modes thatrepresent different trade-offs between speed and reliabilityof identification. The mode is set by DDEP (for FMtwo-carrier standards) or via expert mode. DDEP alsoperforms automatic FM de-matrix control in dependenceon the identification.

FM/AM DECODING

A high-pass filter suppresses DC offsets from the FM / AMdemodulators due to carrier frequency offsets andsupplies the monitor/peak function with DC values and anun-filtered signal, e.g. for the purpose of carrier detection.

The audio bandwidth is approx. 15 kHz.

The de-emphasis function offers fixed settings for thesupported standards (50 µs, 60 µs, 75 µs and J17).

An adaptive de-emphasis is available for Wegener-Panda1 encoded programs.

A matrix performs the de-matrixing of the A2 stereo, dualand mono signals to obtain the left (L) and right (R) orlanguage A and B signals.

FM PILOT CARRIER PRESENT DETECTOR

The TV Sound Processor provides FM A2 standard pilotcarrier detection.

2003 Nov 11 138



CONFIDENTIAL

NICAM DEMODULATION

The NICAM signal is transmitted via DQPSK modulation ata bit rate of 728 kBit/s. The NICAM demodulator performsDQPSK demodulation and feeds the resulting bit streamand clock signal to the NICAM decoder.

A timing loop controls the sample rate conversion circuitryto lock the sampling rate to the symbol timing of theNICAM data.

NICAM DECODER

The NICAM decoder performs all decoding functions inaccordance with the EBU NICAM 728 specification. Afterlocking to the frame alignment word, the data is descrambled by applying the defined pseudo-random binarysequence; the NICAM decoder will then synchronize to theperiodic frame flag bit C0.

The status of the NICAM decoder can be read out from theNICAM status register by the user (see the control-busregister description). The OSB bit indicates that thedecoder has locked to the NICAM data. The VDSP bitindicates that the decoder has locked to the NICAM dataand that the data is valid sound data. The C4 bit indicatesthat the sound conveyed by the FM mono channel isidentical to the sound conveyed by the NICAM channel.The error byte contains the number of sound sampleerrors, resulting from parity checking, that occurred in thepast 128 ms period. The Bit Error Rate (BER) can becalculated using the following equation;

During NICAM mode a switchable J17 de-emphasis issupplied.

NICAM AUTO-MUTE

If the Auto Standard Detection (ASD) or the StaticStandard Detection (SSS) feature is activated thefollowing auto mute function is in effect.

If NICAM B/G, I, D/K is received, the auto-mute is enabledand the signal quality becomes poor, the built-in controlautomatically switches the output signal (DEC output) toFM channel 1. The automatic switching depends on theNICAM bit error rate. The auto-mute function can bedisabled via the control bus.

This function is enabled by setting bit NIC_AMUTE to 0.Upper and lower error limits may be defined by writingappropriate values to the corresponding control bits(NICLOERRLIM and NICUPERRLIM). When the numberof errors in a 128 ms period exceeds the upper error limitthe auto-mute function will switch the output sound fromNICAM to whatever sound is on the first sound carrier (FM

or AM). When the error count is smaller than the lowererror limit the NICAM sound is restored.

The auto-mute function can be disabled by setting bitNIC_AMUTE to 1. In this condition clicks become audiblewhen the error count increases; the user will hear a signalof degrading quality.

For NICAM L applications, it is recommended todemodulate AM sound in the first sound IF. Thedemodulated AM is provided by the internal IF processor.For applications with external IF processing the externaldemodulated AM signal can be connected to theSCART/Mono input of the TV Sound Processor. By settingthe EXTAM bit, the auto-mute function will switch to theaudio ADC input signal named EXTAM instead ofswitching to the first sound carrier. The ADC sourceselector should be set to internal AM mono signal or to theexternal SCART/mono input, where the AM sound signalshould be connected.

BTSC STEREO DECODER

The FM demodulated composite signal is fed into the MPXdemodulator for synchronous AM demodulation of the subcarrier. The demodulator includes a pilot detector and pilotcancellation circuit. The main channel (baseband part,encoded (L + R)/2) signal passes a 75 µs fixedde-emphasis filter, while the compressed sub channelsignal goes through the dbx decoder. Both signals are fedto the stereo dematrix to obtain the L and R signals.

SAP DEMODULATOR

The composite signal is fed to the FM sub channeldemodulator and detector circuit. A noise detector can beused to mute the SAP output in the event of insufficientsignal conditions. The SAP identification signal can beread by the control bus.

dbx® DECODER

The circuit includes the noise reduction system inaccordance with the BTSC system specification andconforms to the standard of quality defined by THATCorporation

JAPAN (EIAJ) DECODER

The above mentioned FM sub channel demodulator,together with a matching low pass filter, is used to decodethe EIAJ multiplex signal. The resulting main and subchannel signals then pass through the similar blocks as inFM A2 mode, that is DC notch filtering, fixed deemphasis(75 µs) and dematrix.

BER bit errorstotal bits----------------------- error byte 1.74× 10 5–×≈=

2003 Nov 11 139



CONFIDENTIAL

FM RADIO DEMODULATOR

The above mentioned MPX demodulator can also be usedto decode a FM Radio input signal with a 19 kHz pilot tone.A freely selectable intermediate frequency (IF) between4.5 and 10.7 MHz can be applied to the SIF input. Both theEuropean and North American modes (pre-emphasis 75µs and 50 µs, respectively) are supported.

EASY PROGRAMMING

For a complete description of DDEP and application hintsrefer to the technical report HSIS/TR0107.

Overview

DEMDEC Easy Programming (short DDEP) is the name ofthe high-level control interface to the DEMDEC DSP of theTV sound processor. Its main intention is to make thedevelopment of system control software for the DEMDECas simple as possible, while optimally exploiting theavailable hardware and DSP resources.

The functionality of DDEP is divided into three main areas:

1. Demodulator and decoder configuration with optionalstandard and second carrier / subcarrier search;

2. Decoding, signal routing and switching for simplehandling of broadcast sound signal types, plusencoding of the main status register;

3. FM overmodulation adaptation: optional adaptivereduction of levels and filter widening in case ofovermodulation, in order to avoid distortions due toclipping or overflow.

The DDEP software controls both the demodulatorhardware and the real-time signal processing softwarerunning on the same DSP, e.g. by changing filtercoefficients, pointers etc., often depending on statusinformation generated by hardware or software.

Most functions act like "background processes": smallcode sections are executed at a reduced rate (for instanceevery 32th sample at 32 kHz = 1000 times per second), inorder to accommodate a large amount of program codewithout consuming too much of the available processingpower of the DSP. A "control timeslot" is reserved in theDSP software in which both control register decoding andbackground processing is performed.

DDEP in short

DDEP can operate in one of two modes, which differ onlyin the type of standard handling. Additionally, a few optionsare available to the user.

In ASD (Auto Standard Detection) mode, an automatic TVsound standard and carrier search is performed at achannel switch, following preferences determined by theuser or the system controller, such that a standarddetection and identification (stereo / dual) result isobtained as fast as the hardware permits. If only the stereosystem within a standard changes later, the searchprocedure adapts (e.g. B/G A2 to B/G NICAM or viceversa).

The SSS (Static Standard Selection) mode requires theuser to select the sound standard (incl. stereo system) bymeans of a standard code (e.g. code 4 denotes "B/G A2",the European analog FM two-carrier standard) and nosearching is done. This mode is like a subset of the ASDmode in that it acts similarly as the ASD mode if thestandard detection has found the selected standard.However, in SSS mode the decoder never changes to adifferent standard, and the user must supply settings thatASD selects by its own expertise (IDENT speed for A2standards and line frequency for BTSC). The SSS modecan be used to enforce a certain sound standard in caseASD was unable to find a sound carrier and is needed toselect FM Radio decoding. The ASD routines operate as ifusing the SSS mode to select a certain standard.

In both of these modes, the DDEP system handles theother signal processing and settings automatically withouta need for further interaction, and also allows the sameoptions:

1. It is possible not to use the default NICAMconfiguration for a detected or selected standard, butsupply other settings via the NICAM configurationregister.

2. The default thresholds and hysteresis sizes fornoise-based automute and SAP detection can beoverruled.

3. The optional overmodulation adaptation may be usedin ASD as well as in SSS mode.

4. A pre-scaling of the EXTAM signal is usually neededto obtain a correct level.

5. As NICAM sound often seems softer than the FMsound, an additional level adjust for this signal path ispossible.

6. Levels of the DEMDEC output signals may bechanged individually if a level other than the nominal-15 dBFS (with nominal modulation degrees) isdesired, all signal levels can be adjusted before thefirst digital crossbar.

2003 Nov 11 140



CONFIDENTIAL

DDEP can be switched off completely, allowing useraccess to all low-level settings. All automatism are thendisabled. This so called "DEMDEC expert mode" ("manualmode") requires detailed knowledge and understanding ofthe involved hardware and software and will be explainedin a later report. A satellite TV application unfortunatelyrequires the expert mode since satellite sound is notsupported by DDEP. As usual for this application, allconfigurations like carrier frequencies and deemphasistypes must be supplied by the set user or have to bepre-programmed.

Note that DDEP does not include handling the SIFfrontend (input selection, AGC etc.) since this isapplication dependent.

Fig.43 sketches the handling of the two different controlregister sets for DDEP and expert mode and theirtranslation into software and hardware settings.

All central DDEP functions are controlled by writing asingle register, the DDEPR register is located in the XRAM(data memory) of the DSP and accessible via the PI businterface (I2C).

Fig.43 Control Flow

DDEP controlregisters

expert modecontrol registers

ASD searchprocedures

Overmod.Adaptation

standarddependent

low-level control routines, internal variables, hardware registers

real time signal processing software

(detectors)(pointers, coefficients etc.)

SSS mode

(export mode only)

2003 Nov 11 141



CONFIDENTIAL

DEMDEC hardware blocks

Due to the high bandwidth and computationalrequirements, the actual demodulation of the soundcarrier(s) is implemented in dedicated digital hardware.These are

1. a SSIF frontend with AGC and high-speed ADC;

2. two FM / AM demodulator channels withprogrammable mixer frequencies and four differentfilter bandwidths;

3. a NICAM demodulator and decoder for all NICAMstandards;

4. an identification circuit for all standards;

5. an additional "BSJ" ("BTSC, SAP, Japan") blockprovides MPX demodulation (for BTSC and FMRadio), FM subchannel demodulation plus matchingfilter (for SAP and the Japanese EIAJ standard), and anoise detector.

The dedicated demodulator and decoder hardwaredelivers "raw" signals that cannot be used without furtherprocessing in the DEMDEC realtime software. Each signalcomes in with a sample rate of n*32 kHz.

Sample rate for the audio processing and DEMDEC is 32kHz.

Figure 44 shows the described hardware blocks and theirconnection to the DSP. The hardware is usually controlledby the DDEP software, or by the controller via the expertmode.

Fig.44 Demodulator & Decoder Block Diagram

BSJ block

AGC A/Dmixerch. 1

mixerch. 2

decimationfilters

FM / AMdemodulator

#1

MPXdemodulator

EIAJ lowpass

FM subchannel

demodulator

noisedetector

decimationfilters

FM / AMdemodulator

#2

NICAMdemod. &decoder

clockcontrol

4 fs

2 fs

1 fs

clockgeneration

(24.576 MHz)

FM

AM

FMIdentification(Europe / Korea /

Japan)

EPICS7ADSPInputRegis-

ters (DIO)

analogSSIF

control signal forcarrier tracking

2003 Nov 11 142



CONFIDENTIAL

Signal processing in DSP software

The output signals of the above-mentioned hardwareblocks (next to signal from other sources like ADC or I2S)read in by the DSP, processed, decoded, and forwarded tothe digital input crossbar for further processing (volume,tone control, effects etc.). Fig.45 shows this signal flow ina simplified structure.

The signals from the analogue sound carriers are passingthrough several filters like down-sampling anddeemphasis, noise reduction processing (Wegener-Panda/ dbx® expanders), and dematrixing. For the NICAM signalonly a J17 deemphasis is needed. The decoded signalsare available at the DEMDEC outputs (identical to inputsof the digital input crossbar). The first (topmost) pair ofoutput channels, called DEC (from DECoder), is intendedto carry the stereo or bilingual (dual) signal; an extra“MONO” channel always contains the mono signal fromthe first sound carrier (always FM or AM), or the mainchannel (baseband, [L+R]/2) of the MPX typestandardsBTSC, FM Radio and EIAJ. (This channel may containdifferent audio contents in case of NICAM.) Another signalchannel named “SAP” transports a SAP signal if detectedduring a BTSC reception. An “external AM” signal shouldbe used for standard L since the “internal” digital AMdemodulator does usually not achieve the S/Nperformance of an analogue demodulator operating on thefirst sound IF. This signal may be available via an ADCinput. If standard L is active, DDEP can feed this signal tothe MONO output of the DEMDEC (and to the DEC as wellif no NICAM is detected), or alternatively use the internalAM demodulator output.

By means of this signal routing, the processing paths in theaudio backend do not need to select a specific sourcedepending on the currently activesound standard as it wasrequired on earlier Philips stereo decoders (FM/AM,NICAM source). For every audio processing path, thecontroller can select the DEC, MONO etc. output like anyother signal source (ADC, I2S input,..). The informationabout the signal type (mono, stereo, dual) on the DECchannels is available by two status bits. This also allowsthe audio backend to implement a “smart matrix” whichselects one of the two languages in dual mode, or stereoin other cases.

The MONO output can be selected in case that stereo/dualis not wanted, which a two-channel output to anotherdestination is still possible. A special case is a NICAMtransmission with independent contents of analogue andNICAM sound carriers (indicated by status flag RSSF=0)when the mono channel carries a different signal than theNICAM channels.

Internal scalings are applied in DDEP mode such that alloutputs signals have a level of -15 dBFS for nominalmodulation degrees (e.g. 54% full scale sine wave = 27kHz FM deviation of a B/G FM carrier). Additional leveladjustments can be performed at the digital crossbar in theaudio DSP. In export mode, the internal scalings, switchesetc. must be controlled via the expert mode registers.



2003 Nov 11 143

CONFIDENTIAL

Fig.45 Signal processing modules

4xDIO

4xDIO

lowpass,dec. by 2

2xDIO

2xDIO

decimationby 2 &equalizer

decimationby 2 &equalizer

DC notch,deemph.

FMdematrix

DIO

DIO

NICAM (J17)deemphasis

DEC

MONO

SAP

FM / AM / BTSC

NICAM

compromiselowpassor dbx

FM subch.

EIAJ main

scalingch. 1

ch. 2

output leveladjust

ADC (L)

MONOSEL

DECSEL

lowpass,dec. by 2

lowpass,dec. by 2

lowpass,dec. by 2

lowpass,dec. by 2

lowpass,dec. by 2

DC notch,deemph.

75 sdeem.

lowpass,dec. by 2

lowpass,dec. by 2

DCnotch

DCnotch

dbx

DC notch,deemph.

DC notch,deemph.

DECPATH

®

®

2003 Nov 11 144



CONFIDENTIAL

Audio Processor

The functional overview of Audio part of the Sound DSP is shown in Fig.46

Fig.46 Audio Backend Operation of UOCIII (DSP functions)

®

+

Mas

ter

Vol

ume

S

C

S

UB

L,

R

Trim

DPL®

AVL

VDS423/422 ®

orTruSurround ®

MA

IN M

Sel

EPS orESS or3D Sound®

MAINBa/Tr

Loudn

BBE®

Bas

s M

anag

emen

t

S D

elay

Dig

ital O

utpu

t Cro

ssba

r

CBa/TrLoudn

SBa/Tr

L,RSM

AUX1,2Vol/Trim

AUX1,2

SM

AUX3Vol/Trim

AUX3SM

Noise/SilenceGen.

(L+R)/2

CMSel

SMSel

SUBSM

CSM

SSM

Beeper

IIS INADC (L, R)DEC (L,R from DEMDEC)MONO (from DEMDEC)SAP (from DEMDEC )

DAC1L,R

I2S1L,ROUT

I2S2L,ROUT

MAIN

SUB

C

S

AUX1,2

AUX3

2 equal channels for I2S

C IN

S IN

L,R L,R M/ST

C,S

DPL®

, VDS®

are trademarks of Dolby Labs

TruSurround®

, 3D Sound®

are trademarks of SRS

Labs

BBE ® is a trademark of BBE Sound Inc.

Ps. Hall/Matrix

Audio Monitor

AU

X3

Dig

ital I

nput

Cro

ssba

r (

SS

el, M

atrix

)

AU

X1,

2S

CM

AIN

DAFO1

DAFO2

to DAC2

L,R DPL

(L+

R)/

2

(L-R

)/2C

DPL,423

L,R

423,422

S

DPL

DV

B o

r D

BB

in L

,R o

r S

UB

CEql

MainEql

Silence

BBE ® or DBB or DVB can be used

Leve

l adj

.

PassiveMatrix

C,S

L,R

Eco

SU

B

The processing of the loudspeaker channels (MAIN, SW,C, S), the auxiliary channels AUX1 to AUX3 is nestedbetween the digital input crossbar and the digital outputcrossbar.

Inputs to the digital input crossbar are the sources

- DEC, with the four lines L/A, R/B, Mono, SAP,

- A_ADC 1,2, with L/A, R/B coming from the audio ADC,

- I2S 1 IN, from the I2S input.

All these signals pass the level adjust before entering thecrossbar. That adjust is needed to level the source signalsif they deviate from nominal setting.

The Noise/Silence Generator is a special source. It isneeded as noise source for Dolby® Pro Logic® speakertrim compliant to the Dolby requirements for a noisesequencer

The digital input crossbar provides source select andmatrixing for the channels MAIN (L, R), AUX1 to AUX3, butonly source select for centre (C), surround (S) becausethese are mono channels.

Although the selectors are all of the same type not allfacilities will be used in normal applications of UOCIII. E.g.the output of the centre and surround selectors can bepermanently connected to the Noise/Silence Generator.The AUX channels need not to be switched toNoise/Silence.

2003 Nov 11 145



CONFIDENTIAL

Setting of the digital matrix depends on the type of inputsignal. The type may be known from the identification inthe demodulator/decoder as stereo, dual language ormono. So the switching can be made dependent from theidentification. For dual language the preference forlanguage A or B can be set when automatrix is selected.In this case the matrix provides the language according tothe preference selected by the end-user.

If an external audio source (ADC, I2S) is chosen the signaltype is unknown or can only be seen from the label of atape etc. Thus the end-user needs to get a selection facilityin this case. It should include the choice betweenstereo/dual language (AB), mono (from stereo by (A+B)/2,also called forced mono), sound A or B and a swap (BA)for stereo if the source has interchanged L and R.

The processing channels are dedicated to loudspeakers(MAIN, SW, C, S), to I2S OUT (AUX1, AUX2) or DAC1(AUX3). AUX1 to AUX3 offer only volume and balancecontrol (Vol/Bal) and softmute (SM).

In the loudspeaker channels we can process mono,normal stereo or Dolby® Pro Logic® encoded signals. The

functions provided can be used according to these signaltypes. Some of them are dedicated to specific modesleading to constraints. The AVL and Pseudo Hall/Matrix((L+R)/2, (L-R)/2) can only be used with stereo or monosignals, VDS only with DPL decoded signals. ExtendedPseudo Stereo (EPS) or Extended Spatial Stereo (ESS)can be selected, but for DPL it has to be switched off tomeet the Dolby requirements. Other selections depend onthe speaker system, whether the set is equipped with 5speakers (L, R, SW, C, S) (only possible when externalDACs are applied) from which all are used or maybe thesurround speaker is disconnected or with just 2 speakers(L, R). Also important is the speaker size/bandwidth.

Some of the functions are set by SNDMODE according tothe Sound Mode Table. The rest needs to be controlled byindividual settings.

SOUND MODES OF THE LOUDSPEAKER CHANNELS

Appropriate sound modes are defined in the table 256:

Table 256 Sound Mode Table

The Sound Mode sets explicitly the functions AVL, DPL, VDS, Main MSel, C MSel, S MSel, Pseudo Hall/Matrix and itprovides a specific setting for noise sequencing.

The table 257 shows the setting of these functions for the loudspeaker channels by Sound Mode control. All otherfunctions have to be set by direct control via the related registers and bits.

Sound Mode FUNCTION

M/ST - Mono/Stereo in case of mono or stereo source signals

M/ST Hall - Mono/Stereo with pseudo Hall in case of mono or stereo source signals

M/ST Matrix - Mono/Stereo with pseudo Matrix in case of mono or stereo source signals

DPL N/W (normal centre) - DPL normal/wide in case of DPL decoded source signals

DPL PH (phantom centre) - DPL Phantom Centre in case of DPL decoded source signals

DPL 3ST (3 stereo) - DPL 3 Stereo in case of DPL decoded source signals

VDS423 - DPL+VDS(423) in case of Virtual Dolby® Surround 423

VDS422 - DPL+VDS(422) in case of Virtual Dolby® Surround 422

SRS® TruSurround - Passive matrix + TruSurround virtualizer (422)

DPL NSEQ - DPL speaker level Trim (noise sequencing)



2003 Nov 11 146

CONFIDENTIAL

Table 257 Sound Mode Settings

Notes

1. AVL active means that the set maker can use all facilities by direct control via related registers and bits

2. the noise/silence generator is active, MSel Centre is connected to CIN and MSel Surround is connected to SIN togive the set maker the facility to build a noise sequencer application of his choice with the M/ST sound mode.

3. (silence) means that the signal carries silence, no audio or noise.

SOUNDMODE

SETTING BY SOUND MODE OF FUNCTIONS

AVL DPLNOISE

/SILENCEGEN.

VIRTUALIZER

MSEL.MAIN

PSEUDOHALL

/MATRIX

MSEL.CENTRE

MSEL.SURROUND

M/ST active

(note 1)

not active active

(note 2)

not active connected to

L,R M/ST


CIN

connected to

SIN

M/ST Hall active

(note 1)

not active not active not active connected to

L,R M/ST

PseudoHall active

connected to

(L+R)/2

connected to

(L+R)/2

M/STMatrix

active

(note 1)

not active not active not active connected to

L,R M/ST

PseudoMatrixactive

connected to

(L+R)/2

connected to

(L-R)/2

DPL N/W(normalcentre)

not active DPL N/W not active not active connected to

L,R DPL


CDPL,423

connected to

SDPL

DPL PH(phantomcentre)

not active DPL PH not active not active connected to

L,R DPL


CDPL,423

(silence)

(note 3)

connected to

SDPL

DPL 3ST(3 stereo)

not active DPL 3ST not active not active connected to

L,R DPL


CDPL,423

connected to

SDPL

(silence)VDS423 not active DPL N/W not active VDS423 connected to

L,R 423,422


CDPL,423

connected to

SDPL

(silence)VDS422 not active DPL N/W not active VDS422 connected to

L,R 423,422


CDPL,423

(silence)

connected to

SDPL

(silence)SRS®TruSur-round

not active not active not active TruSurround (422)

connected to

L,R 423,422


CDPL,423

(silence)

connected to

SDPL

(silence)DPL NSEQ not active not active active not active connected to

L,R M/ST


CIN

connected to

SIN

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DESCRIPTION OF THE FUNCTIONS

Level Adjust

Level adjust in a range from +15dB to –15dB is providedfor input signals from the demodulator/decoder (DEC),ADC and I2S. A step of –16 is defined as mute.

Digital Input Crossbar

The digital input crossbar can connect any input with everyoutput channel for source selection. It also includes adigital matrix for each stereo output. For input signals Aand B this matrix can provide at the output AA, AB, BA, BB,(A+B)/2 and (A-B)/2. The specific modes Auto LanguageA and Auto Language B take care that either language Aor B is selected automatically when dual language isdetected by the TV sound processor.

AVL

The AVL reduces the audio input signal in the MAINchannel (L, R) to a selectable maximum output level if itexceeds this level at the input of the stage.

A detector creates the control signal from L and R. TheAVL provides a short attack time and decay times of 20ms,2s, 4s, 8s and 16s. A weighting filter can be chosen in thecontrol signal generation. The advantage is that basssignals and high frequency components have less impacton control.

The Dolby® Pro Logic® Function (DPL)

The Dolby® Pro Logic® Decoder is compliant to theDolby® Licensee Information Manual: Dolby® SurroundPro Logic®, Issue 6.

If the MAIN channel signal L, R is Dolby encoded thedecoder can generate appropriate L, R, C and S signals.

Auto Balance is always provided. The selection of DPLnormal/wide, Phantom Centre, 3 Stereo delivers outputsignals according to the Dolby requirements. Outputs notused in a specific mode carry digital Silence ‘—‘.

Surround delay is adjustable between 15ms and 30ms.

Noise Sequencer for DPL

The set maker has to provide a program to build a NoiseSequencer with the components available in the UOCIII.The procedure is described in the Dolby LicenseeInformation Manual: Dolby® Surround Pro Logic®, issue6. All channels L, C, R, S (only possible when externalDACs are applied) can be connected to the noise sourceof the noise/silence generator and by use of the soft-mute(SM) the noise can be cycled. It is recommended to mutethe sub-woofer output, while the noise sequence is active.

Virtual Dolby® Surround

Virtual Dolby® Surround gives a surround soundimpression with use of only two speakers (VDS422) orthree speakers (VDS423, only possible when externalDACs are applied). Input to VDS are the L, R, C and Soutputs of the DPL decoder. The surround signal S isvirtualised and redirected in both cases to the left and rightchannel whereas the centre signal is redirected to L, Ronly when VDS422 is selected. In VDS423 a centrechannel is provided.

The intensity of the effect can be controlled.

SRS® TruSurround

TruSurround is a virtualizer giving a surround sound effectwith only two speakers (422). It can be used alternativelyto VDS. TruSurround makes use of a passive matrix whichdelivers internally L, R, C and S signals. The virtualizerthen generates a new L, R stereo signal from it to achievea surround sound effect.

Pseudo Hall/Matrix

Because Dolby® Pro Logic® encoded signals aretransmitted not very often a Pseudo Hall and PseudoMatrix function is provided.

In case of Pseudo Hall the sum signal (L+R)/2 is passed tothe centre and to the surround channel whereas forPseudo Matrix the centre channel carries (L+R)/2 and thesurround channel (L-R)/2. The surround signal is delayedby 30ms in both cases.

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I-Mono or Extended Pseudo Stereo (EPS)

The Incredible Mono module (I-Mono) generates twochannels from one mono input signal. When the sound ofthe mono input signal is processed, the listener gets theimpression that the sound is essentially a stereo signal.The pseudo stereo effect is adjustable. Additionally theuser can switch this function ON or OFF.

I-Stereo or Extended Spatial Stereo (ESS)

The I-Stereo module is a Stereo Expander. The listenergets the impression of a sound reproduced by two virtualspeakers, positioned at a larger distance between eachother than between the actual speakers. So, the stereoimage is expanded by this widening sound effect.

The stereo widening effect is adjustable. Additionally thisfeature can be switched ON or OFF.

SRS® 3D Stereo

3D Stereo retrieves the spatial information from any stereosignal. It produces a larger sweet spot. A centre controland a space control is provided.

Bass/Treble

Bass and treble functions are implemented in all four mainsignal paths (L, R, C, S). The user is able to attenuate orboost the bass and high frequency signals independentlywithin a range of -16dB to +15dB. The external resolution(under user control) is defined to 1dB steps, whereas theinternal resolution (not under user control, 1/32dB steps) isused to avoid ‘pop noise’. The internally used 1/32dB perstep leads to a maximum speed of amplitude change,which is defined to 15.625dB/s. The corner frequency ofthe bass function is fixed to 40 Hz and for the treblefunction fixed to 12 kHz.

Loudness

The human ear listening curves (Fletcher-Munsonloudness contours) show, that the ears of a human areless sensitive for low and high frequencies at low soundpressure level (volume level). In general a loudnessfunction can be used to compensate the human earsensitivity loss at low volume levels.

Within a volume range of 30dB the loudness gain varieswith the total gain value of the volume stage. The loudnesscurves are automatically adjusted to the volume level,where the allowed input volume steps can be 1/8dB oreven smaller to avoid step-noise.

At high volume the resulting loudness curve is flat,because there is no need to boost high and lowfrequencies at high sound pressure level. The loudnessboost becomes active, if the input volume is reduced belowthe (adjustable) no attack threshold. The resulting gaindepends on the actual input volume level. Within a rangeof 30dB below the no attack threshold the loudnessfunction gives an increasing boost of low and highfrequencies. If the input volume is reduced more than30dB below the no attack threshold level then themaximum loudness gain is reached and the loudnesscurve for 30dB remains active. The maximum loudnessgain is +18dB at 20 Hz and + 4.5dB at 16 kHz.

The frequency where gain is not affected by the loudnessfunction is called no attack frequency. This no attackfrequency can be adjusted to 500 Hz or 1 kHz. This resultsin different loudness curves, but the maximum gain at 20Hz and 16 kHz remains the same.

Loudness is applied in the L, R and C channels.

BBE®

The BBE® sound process offers 2 primary functions. Firstit compensates the time delay over frequency of theloudspeaker. Secondly it provides a dynamic, programdriven augmentation at the high and low frequency range.Together it restores the transients of the studio signals.This improves the brilliance and clarity of sound. WhenBBE® is selected either DUB or DBE function is disabled.

Bass-ManagemenT (BMT)

Every DPL sound IC, which has to be licensed by DolbyLaboratories, must include a Bass ManagemenT (BMT,also called bass redirection). The UOCIII (TDA120xxH)bass redirection fulfils the different configuration modesrequired by Dolby Laboratories.

In general the bass redirection is used to redirect the lowfrequency components of the audio signal to loudspeakerswhich are able to cope with such power-full low signals(large speakers). In audio equipment all speakers may belarge, but in TV sets either the L and R speakers are largeor a sub-woofer is applied. Thus a bass redirection can bedone to the L and R large speakers or to the sub-woofer.The low frequency components are cut out of the audiosignals, which are directed to satellite loudspeakers (smallspeakers); on the other hand, the high frequencycomponents are cut out of the audio signals, which areredirected to the sub-woofer.

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The corner frequency of the high and complementary lowpass filters can be selected, to allow specific adjustmentswith respect to the used TV set loudspeakers. The cornerfrequency of the LP / HP- filters is adjustable within a rangefrom 50 Hz to 400 Hz. There are 16 different cornerfrequencies to choose from: 50Hz, 60Hz, 70Hz, 80Hz,90Hz, 100Hz, 110Hz, 120Hz, 130Hz, 140Hz, 150Hz,200Hz, 250Hz, 300Hz, 350Hz and 400Hz.

The bass redirection (BMT) covers three differentconfiguration modes:

As the bass redirection stage will be also used in otherapplications including Dolby® Digital the Dolby® Digitalimplementation of BMT is used within UOCIII as a basis.

BMT1 covers the bass management described asconfiguration 1 (see Dolby® Digital Specification Issue 3,Figure 4-21 Configuration 1). The BMT1 mode is used toredirect the low frequency components of all three frontchannels (left, right and centre) to a separate sub-wooferloudspeaker. As mentioned within the Dolby specificationfor Dolby® Pro Logic®, the surround channel is notredirected. This can be done because surround is alreadyfrequency band limited from 200 Hz to 7 kHz. If UOCIII isused in non-Dolby stereo in the pseudo hall (M/ST Hall) orpseudo matrix mode (M/ST Matrix), then also the surroundchannel is filtered and redirected.

BMT2 is equivalent to the bass management described asconfiguration 2 (see Dolby® Digital Specification Issue 3,Figure 4-22 Configuration 2). The BMT2 mode is used toredirect the low frequency components of the centrechannel to the full-range main loudspeakers (large left andright speakers). Additionally a separate sub-wooferloudspeaker can be used in this configuration. Like inBMT1 mode the surround channel is not redirected ifUOCIII is used in non-Dolby stereo in the pseudo hall(M/ST Hall) or pseudo matrix mode (M/ST Matrix), thenalso the surround channel is filtered and redirected.

The BMTOFF mode is used if no redirection of the lowfrequency components is needed, in case of all three frontloudspeakers (left, right and centre) are largeloudspeakers.

There is an option to switch off the low path filter, which islocated in the sub-woofer output path. This non-processedsub-woofer mode can be used with BMT1 and BMT2, andgives the possibility to use an external sub-woofer filter.

As recommended by Dolby Laboratories, the UOCIII

always uses the HP-filter located in the surround channelwhen DPL is active.

The figure 47 gives a general overview about the UOCIII

bass redirection (BMT).

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Fig.47 Overview of the UOCIII Bass-Redirection

gain/dB

a1a2a3a4

S1S2

filter

b1b2b3b4

BMT1

-10-10-10-10

ba

HPHPHPHP

BMT2

-100-100-4.5-4.5

ab

flatflatHPHP

BMOFF

-100-100-100-100

ba

flatflatflatflat

a1

a2

a3

a4

-10dB

b1

b2

b3

b4

L

R

C

S

SW’

L’

R’

C’

S’

BMT1, single woofer system with improved filtering : small speakers for L, R, C, S; extra SW(subwoofer)BMT2 , normal center mode with bass splitter (DPL) : large speakers for L, R; small speaker C, S ; SW optionalBMOFF , wide center mode (DPL) : large speakers for L, R, C ; small speaker S

a4* -100 -100 -100

*) If DPL is active a4* is used.

1) LP filter can be switched flat, to allowthe use of external sub-woofer filtering.

LP

a

b

S1

S2a

b

LP1)

Overview of the Hercules Bass-Redirection

Equaliser

A graphic equaliser is implemented in the L, R and Cchannel. It provides five bands at 100, 300 1000, 3000 and8000 Hz. For every band the gain is adjustable from -12 dBto +12 dB in steps of 1 dB.

Dynamic Ultra Bass ™(DUB) or Dynamic Bass Boost(DBB)

In general the DUB function is used in TV-Sets with smallspeakers that cannot reproduce deep bass signals. Theeffect is caused by producing harmonics of the lowfrequency content. It gives the impression of deep bassreproduction although the fundamentals are missing. Thelevel of harmonics added to the original signal is madedependent from the total signal level at the output. Thisdynamic behaviour allows a strong amplification of theharmonics for small volume signals, but only smallamplification for high volume signals. Maximum gain andthe target output level could be set.

The acoustical behaviour of this feature has to be tuned tothe TV internal loudspeaker set. Therefore a certain set offilter coefficients has to be found for each used TV set.This is done by use of the loudspeaker characteristics aswell as by listening tests. This coefficient set has to beloaded into the UOCIII once after power on reset. A methodto calculate the coefficients will be available.

DUB is normally applied to the left and right speakers.Alternatively it can be provided with different coefficients tothe sub-woofer signal to enhance the bass reproduction.When using DUB it is not possible to apply DBE or BBE®.

Dynamic Bass Enhancement (DBE) or Dynamic VirtualBass (DVB)

The DBE function is used in TV-sets equipped with largespeakers or sub-woofer system. This feature produces alevel depending bass boost. The dynamic behaviourallows a strong bass amplification for small volumesignals, but only small bass amplification for high volume

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CONFIDENTIAL

signals. Q-factor of the boosting filter, maximum gain andthe target output level can be set.

This function has to be tuned to the speakers used withina certain TV-set. The coefficients for the filters as well asthe parameters for the bass boost control have to bestored into the UOCIII once after power on reset. A methodto find the best coefficients and parameters for a certainTV-set will be available.

DBE is applied to the left and right speakers oralternatively with different coefficients to the sub-woofer.When using DBE it is not possible to provide DUB orBBE®.

EcoSUB (Economic Subwoofer Mode)

EcoSUB (Economic Subwoofer Mode) allows to drive asubwoofer without an additional power amplifier. Thesubwoofer signal will be added differentially to MAIN L, R.By the use of some passive filter components thesubwoofer can be driven differentially by the MAIN L, Rpower amplifier. This mode should be combined with theBass Redirection in Configuration 1.

Master Volume and Trim

Master volume control is applied to all speaker channels ina range from 24dB to –83dB gain. Step width is 1/8 dB. Amute step is available. Trim can be set in 1dB steps withinternal resolution (not under user control) of 1/8 dB. Therange is the same as for volume control. Maximum speedof change is 62.5dB/s.

The three-stage gain element per channel is controlled viathe common master volume register and the respectivetrim registers. The requested gain values are addedinternally. Total gain is limited to +24dB.

Volume and Balance

Stereo channels have separate gain elements in the leftand right branch. In the MAIN channel the L, R trims areused. Shift to the right is done by attenuation of the L trim,shift to the left by attenuation of the R trim.

In the AUX channels the same is performed by use ofvolume left and right.

This needs to be programmed by the set maker.

Soft Mute

When soft mute is activated/disabled the gain isreduced/increased any 2ms by one of totally 32 stepsaccording to a cosine function. Thus it takes 64ms frommaximum gain to mute or vice versa. When muted the

input signal of the stage is multiplied with zero. So theoutput carries digital silence.

Each channel has an independent soft mute stage.Additionally a MAINMUTE is available that provides acommon mute of the left and right signal of the mainchannel. It overrules when it is activated the MAINLMUTEand MAINRMUTE settings.

Beeper

The beeper is a sine wave generator for frequencies from200Hz to 12.5kHz at a sample rate of 32kHz. The level canbe set between 0dBFS and –83dBFS. A Mute/off step isavailable. The signal is mixed into the left and rightchannels for the main loudspeakers.

If the beeper is not used it needs to be set to the Mute/offstate.

Mono Signal (L+R)/2

The L and R signals of the MAIN channel are added at theend of the channel giving (L+R)/2. This signal can beprovided to outputs for specific applications.

Audio Monitor

The audio monitor is able to monitor the level of the sum(A+B)/2, the left or right signal of all input channels of thedigital input crossbar. A special setting is the (A-B)/2 modein the digital matrix that offers the possibility to identify asignal as a mono or stereo signal. Additionally a variety oftest points in the DEMDEC and audio processing areselectable.

The audio monitor provides three different modes:

• Last sample: in this mode the level of the last samplefrom the selected input is stored in the monitor register,

• Peak detection: in this mode the peak level after the lastread command is stored in the monitor register,

• Quasi peak detection: a quasi peak detector with anattack time of 4ms and a decay time of 1s is applied.

If the monitor is used for mono/stereo detection the quasipeak mode should be selected.

The read transfer rate via control bus is limited to about15kHz.

Digital Output Crossbar

The digital output crossbar provides 10 selectors ‘one outof 12’. That means each of the outputs e.g. DAFO1 orI2S1L can be connected to each of the inputs e.g. MAIN Lor C etc. By this the setmaker is free to assign the outputs

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DAFO1 to DAFO2 and I2S1L, I2S1R, I2S2L, I2S2R to anyof the L, R, SW, C, S speakers or other destinationsaccording to his specific application.

The channels AUX1 to AUX2 may be connected to the I2Soutputs. Channel AUX3 normally has to be passed tooutput DAC1. Each output can also be connected to asilence signal from the NOISE/SILENCE Generator.

Auxiliary Channels

The channels AUX1 to AUX3 have volume/balanceprocessing and soft mute and can be assigned to outputsI2S1, I2S2 or DAC1 respectively.

Clip Management

The clip management is a feature that should preventautomatically internal clipping. Internal clipping can takeplace if in combination bass, treble or equaliser settingsintroduce large amplification of the signal. To preventclipping different strategic ways are possible. Therefore 4different modes are defined.

"Static Volume Mode" - In this mode the master volume +trim gain is limited to a maximum gain of -30dB. The trimand the volume/balance in the Aux1-3 are not affected.

"Static Control Mode" - In this mode the bass, treble andequaliser gain is limited to a maximum of +8dB. TheVolume plus Trim setting is limited to -1dB.

"Dynamic Control Mode" - In this mode the master volumeand trim gain is limited to +3dB. If the master volume plustrim setting exceeds -12dB the bass and treble arereduced until the sum of amplification of bass and trebleplus master volume and trim is less then +3dB. If mastervolume and trim is in the controlrange between -12dB and+3dB every 1dB more master volume plus trim results in1dB less bass and treble.

"Dynamic Volume Mode" - In the dynamic volume modethe main left and right signal is measured. If the internalsignal exceeds a limit of -3dBFS for a longer time, themaster volume is reduced automatically until themeasured signal is lower -3dBFS.

Table 258 Clip Management

Power On / Reset Condition of the Sound DSP

After a power on or reset all DSP-RAM cells will be cleared. Afterwards all module defined memory spaces will be initialisedand the Control-Register values will be set to the default value. This value is called 'Default@INIT' in the control table.

CLIP MANAGEMENT MODE MASTER VOLUME + TRIM BASS TREBLE LOUDNESSStatic Volume Mode limited to -30dB not affected not affected not affectedStatic Control Mode limited to -1dB limited to +8dB limited to +8dB none attack level 0dBDynamic Control Mode limited to +3dB see Fig. 48 none attack level 0dBDynamic Volume Mode Reduced / limited until the signal

is smaller or equal -3dBFSnot affected not affected none attack level 0dB

Bass/Treble

selected

Bass/Treble

active

-16dB

-16dB

0dB +15dB

0dB

+15dB

+10dB

+5dB

-12dB Master Volume+Trim



+3dB Master Volume+Trim

Hercules Clip Management/ Dynamic Control Mode

Fig.48 Clip management / Dynamic Control Mode

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ANALOG AUDIO PROCESSING

Audio DAC

The TV Sound Processor contains four single DACs. Eachof the low-noise high-dynamic range DACs consists of aswitched resistor architecture with interpolation filter andnoise shaper at the input that runs at an oversamplingfrequency of 128fs. The outputs are fed into thevideoprocessor.

Audio ADC

TV Sound Processor contains two single audio ADCs. Thissingle ADC consists of one bitstream 3rd-ordersigma-delta audio ADC and a high -order decimation filter.Input is supplied from the videoprocessor.

DIGITAL AUDIO INTERFACE

General Description

The TV Sound Processor provides a digital stereo inputinterface and two stereo output interfaces.

• I2S-bus master input interfaces for one stereo channel ata sampling rate of Fs=32kHz.

• I2S-bus master output interfaces for two stereo channelsat a sampling rate of Fs=32kHz.

Three serial audio formats are supported at the Audio multichannel I2S interface:

Philips IIS format

Sony IIS format

Japanese LSB justified format 24-bits

The differences of the formats are illustrated in the figures49, 50 and 51.

In the Philips and Sony formats the left audio channel of astereo sample pair is output first and is placed on the serialdata line (SDI for input, SDO for output) when the wordselect line (WS) is LOW. Data is written at the trailing edgeof SCK and read at the leading edge of SCK. The mostsignificant bit is sent first.

In the Japanese LSB justified format the right audiochannel of a stereo sample pair is output first. The mostsignificant bit is sent first but data is LSB aligned to thefalling edge of the word select line (WS).

The following is only applicable for Japanese LSB justifiedformats:

The input circuitry is limited in handling the number ofSCK pulses per WS level. The maximum allowednumber of bitclocks per WS is 64(per mono audio word32 bitclocks). Also the number of bitclocks during the lowand high phase of WS must be equal or more than theselected format (24 bits).

When the output is enabled, the serial audio data can betaken from pin SDO. Depending on the signal source,switch and matrix positions, the output can be either mono,stereo or dual language sound on either output.

All inputs and the output work with the same samplingfrequency FS, formats and word sizes.

The number of significant bits is 24. The number ofsignificant bits on the output is 24.

The serial data inputs are active at all times, independentof the serial data outputs being on or off. When the serialdata outputs are off (either after power-up or via theappropriate I2C-bus command) serial data and clocks WSand SCK from a separate digital audio source can be fedinto the TV Sound Processor, be processed and output inaccordance with internal selector positions, provided thatthe following criteria are met:

The number of bitclock (SCK) pulses may vary in theapplication. When the applied word length is smaller than24 bits, the LSB bits will be set to 0 internally. When theapplied word length exceeds 24 bits, the LSBs areskipped.

The word select output is clocked with the audio samplefrequency at 32 kHz. The serial clock output (SCK) isclocked at a frequency of 2.048 MHz. This means, thatthere are 64 clock pulses per pair of stereo outputsamples, or 32 clock pulses per sample. Depending againon the signal source, the number of significant bits on theserial data output SDO is 24. The SCK and WS clocks willbe generated by the TV Sound Processor, which is theI2S-bus master.



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Possible Formats

PHILIPS IIS-FORMAT

SONY IIS-FORMAT

JAPANESE FORMAT

SCK

SD

MSB LSBWS

MSB first / MSB justified / Justification bit is one bitclock delayed

MSB LSB

: position fixed.

24.Left 24.Right

Fig.49 Philips IIS-Format

SCK

SD

MSB LSBWS

MSB first / MSB justified

MSB LSB

: position fixed.

24.Left 24.Right

Fig.50 Sony IIS-Format

SCK

SD

MSB LSBWS

MSB first / LSB justified

MSB LSB

: position fixed.

24.Left 24.Right

Fig.51 Japanese Format



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I2C-BUS USER INTERFACE DESCRIPTION

Introduction

The UOCIII series is fully controlled via the I2C-bus. Control is exercised by writing data to one or more internal registers.Status information can be read from a set of info registers to enable the controlling microcontroller determine whetherany action is required.

The TV sound processor has an own I2C-bus slave transceiver, which is independent from microcontroller I2C interface.The specification of this I2C interface is according to the fast-mode specification, with a maximum speed of 400 kbits/s.Information concerning the I2C-bus can be found in brochure “I2C-bus and how to use it” (order number9398 393 40011). One slave address is available (see Table 259).

Table 259 Slave address

In standby mode the clock for the soundpart will be switched off and the soundpart of UOCIII is not functional. So it cannotbe addressed via I2C.

The device will not respond to a ‘general call’ on the I2C-bus, i.e. when a slave address of 0000000 is sent by a master.

Each address of the address space (see below) will be acknowledged, but in case of an illegal address the following datawill not be acknowledged and the transmission will be aborted. Sound function is not guaranteed if not released registersare addressed!

Overview address space

The TV sound processor has 64k addresses, a space of 52 XRAM addresses is available for controlling purpose. Theseregisters are fully DSP software controlled. Other address space is used by internal processing and cannot be used viaI2C.

Here the overview, which addresses are available.

Table 260 Overview full address range

SLAVE ADDRESS A6 TO A0

1 0 1 1 0 0 0

ADDRESS WORDS WORDLENGTH Description

$0000 to $0033 52 words 3 bytes I2C addresses enabled andusable

$0034 to $003F 12 words 3 bytes I2C addresses enabled butreserved. Not usable

$0040 to $FFFF - - always disabled

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Power-up state

At power-up or after a ‘sleep awake’ the device is in thefollowing state:

• All outputs muted

No sound carrier frequency loaded

General-purpose I/O pins ready for input (HIGH)

All level adjusts are set to 0 dB (flat).

All volumes are set to 0 dB and all outputs are muted.

All tone control (bass, treble, equalizer..) settings areflat.

Source selectors of all audio channels are set to DECoutput.

All effects (incredible sound, DPL, AVL) are off.

Demodulator outputs are muted

IIS outputs are disabled

Beeper off

Monitoring of carrier 1 FM demodulator output.

After power-up a device initialization has to be performedvia the I2C-bus to put the UOCIII series into the propermode of operation. All reserved bits (i.e. not defined for thisIC) must be set to zero for the I2C protocol, to assurecompatibility to other ICs of the family.

Overview Control Register Table

The cluster name gives additional information in whichcontext the register will be used.

Table 261 Overview UOCIII I2C SSD Control Register Table

Read/Write

Address Register Cluster

R $001 INF_DEV_STA_REG INFO

R $002 INF_NIC_STA_REG INFO

R $003 INF_NIC_ADD_REG INFO

R $004 INF_LEV_MON_REG INFO

R $005 INF_MPX_LEVEL_REG INFO

R $006 INF_DC1_REG INFO

R $007 INF_SUBMAGN_REG INFO

R $008 INF_NOISELEVEL_REG INFO

R $009 INF_REVISION_ID_REG INFO

W/R $00A DEM_CFG_REG DEMDEC

W/R $00B DEM_CA1_REG DEMDEC

W/R $00C DEM_CA2_REG DEMDEC

W/R $00D DEM_MPXCFG_REG DEMDEC

W/R $00E DEM_FMSUBCFG_REG DEMDEC

W/R $00F DEM_OUT_CFG_REG DEMDEC

W/R $010 MAGDET_THR_REG DEMDEC

W/R $011 NMUTE_FMA2_SAP_REG DEMDEC

W/R $012 NMUTE_MPX_REG DEMDEC

W/R $013 NMUTE_EIAJ_REG DEMDEC

W/R $014 NICAM_CFG_REG DEMDEC

W/R $015 DDEP_CONTROL_REG DEMDEC



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Slave receiver mode

As a slave receiver, the UOCIII series provides 42 XRAM registers for storing commands and data. Each register containsup to 24 bit and can be accessed via so-called subaddresses. A subaddress is 16 bit long and can be thought of as apointer to an internal memory location. Due to the I2C-protocol subaddresses and data are transferred bytewise, so asubaddress needs 2 and a data word 3 byte packets

Not used bits must be set to 0!!

W/R $016 LEV_ADJ_DEM_REG LEVEL ADJUST

W/R $017 LEV_ADJ_IO_REG LEVEL ADJUST

W/R $018 ASW_MA_C_S_REG AUDIO SWITCHING

W/R $019 ASW_A1_A2_A3_REG AUDIO SWITCHING

W/R $01A ASW_DAFO1_2_REG AUDIO SWITCHING

W/R $01B ASW_DAC_I2S_OCO_REG AUDIO SWITCHING

W/R $01C ASW_MUT_CON_REG AUDIO SWITCHING

W/R $01D SOU_APP_MOD_REG SOUND PROCESSING MODE

W/R $01E SOU_EFF_REG SOUND EFFECTS

W/R $01F MAIN_SOU_EFF_REG SOUND EFFECTS

W/R $020 DBE_COEF_DOWNL_REG SOUND EFFECTS

W/R $021 DUB_COEF_DOWNL_REG SOUND EFFECTS

W/R $022 DOL_CON_REG SOUND EFFECTS

W/R $023 MASTER_VOL_REG SOUND

W/R $024 MAI_VOL_REG SOUND

W/R $025 SW_C_S_VOL_REG SOUND

W/R $026 AUX1_VOL_REG SOUND



W/R $029 MAI_TON_CON_REG SOUND

W/R $02A CENTER_TON_CON_REG SOUND

W/R $02B SUR_TON_CON_REG SOUND

W/R $02C EQMAIN1_TON_CON_REG SOUND

W/R $02D EQMAIN2_TON_CON_REG SOUND

W/R $02E EQCENTER1_TON_CON_REG SOUND

W/R $02F EQCENTER2_TON_CON_REG SOUND

W/R $030 MON_SEL_REG MONITOR

W/R $031 GEN_CTRL_REG GENERAL CONTROL

W/R $032 DCXO_CTRL_REG DEMDEC

W/R $033 DDEP_OPTIONS1_REG DEMDEC

Read/Write

Address Register Cluster



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2 modes are possible:

autoincrement: only first address must be transmitted from the master, following addresses will be internally calculatedby incrementing the start address

not autoincrement: every single address must be provided by the master

Table 262 Format for a transmission employing auto-increment of subaddresses

Note

1. DATA...: n data bytes with auto-increment of subaddresses. 3 bytes are 1 dataword. After 3 bytes a new datawordstarts

Table 263 Explanation of previous table

It is allowed to send more than one data word per transmission to the UOCIII series. In this event, the subaddress isautomatically incremented after each data word, resulting in storing the sequence of data words at successive registerlocations, starting at SUBADDRESS. A transmission can start at any valid subaddress. Each byte is acknowledged withA (acknowledge) if address is valid and data byte is properly stored, otherwise a NA (not acknowledge) occurs and abortsthe transmission.

There is no ‘wrap-around’ of subaddresses.

Commands and data are processed as soon as a data word has been completely received. If the transmission isterminated (STOP condition) before all bytes of a word have been received, the incomplete data for that function areignored.

Data patterns sent to the various subaddresses are not checked for being illegal or not at that address.

S SLAVEADDR

0 A SUBADDR1 A SUBADDR0 A DATA... A DATA... A DATA... A DATA... A P

BIT FUNCTION

S START condition

SLAVE ADDRESS 7-bit device address

0 data direction bit (write to device)

A acknowledge by slave

SUBADDR1 Byte 1 (MSB) of write register address

SUBADDR0 Byte 0 (LSB) of write register address

DATA2 Byte2 (MSB) of data word to be written into register

DATA1 Byte1 of data word to be written into register

DATA0 Byte0 (LSB) of data word to be written into register

P STOP condition



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Detection of a STOP condition without a preceding acknowledge bit is regarded as a bus error. The last operation willnot then be executed.

For each address the data word starts with the most significant byte->most significant bit.

Slave transmitter mode

As a slave transmitter, the UOCIII series provides 9 registers with status information and data. These registers can beaccessed by means of subaddresses.

Besides these read registers all write registers are readable too.

The autoincrement mode is also applicable.

Table 264 General format for reading data from the SSD part of the UOCIII series

Table 265Explanation of previous table

Reading of data can start at any valid subaddress. It is allowed to read more than 1 data word per transmission from theUOCIII series. In this situation, the subaddress is automatically incremented after each data word, which results inreading the sequence of data bytes from successive register locations, starting at SUBADDRESS.

Each data byte in a read sequence, except for the last one, is acknowledged with Am (acknowledge by the master).If an attempt is made to read from a non-existing subaddress, the device will send a data pattern of all ones, i.e. FF inhexadecimal notation.

S SLAVE ADDR 0 A SUBADDR1 A SUBADDR0 A Sr SLAVE ADDR 1

DATA2 A DATA1 A DATA0 NAm P

BIT FUNCTION

S START condition

SLAVE ADDRESS 7-bit device address

0 data direction bit (write to device)

A acknowledge by slave

SUBADDR1 Byte 1 (MSB) of read register address

SUBADDR0 Byte 0 (LSB) of read register address

Sr repeated START condition

1 data direction bit (read from device)

DATA2 Byte2 (MSB) of data word to be read from register

DATA1 Byte1 of data word to be read from register

DATA0 Byte0 (LSB) of data word to be read from register

NAm not acknowledge (by the master)

Am acknowledge (by the master)

P STOP condition



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Detailed Control Register Table

Each absolute HEX address is mapped to one register name. The register name gives some information in mnemo likemanner. The cluster name is omitted as column but occurs as header in the column ‘REGISTER’ in the detailed table,(see overview table). Not mentioned bit indices are reserved and must be zero.

Table 266 Detailed SSD I2C read + write control register table

ABS.ADDR.HEX

REGISTER R/W Bitfield Name Data bits Resetvalue DETAILLED INFO($= HEX values)

INFO

$001 INF_DEV_STA_REG R STDRES [4..0] standard detection result (ASD mode), or selectedstandard in SSS mode 0 = failed to find any standard 1 = B/G (still searching, SC2 not (yet) found) 2 = D/K (still searching, SC2 not (yet) found) 3 = M (still searching, no ident or pilot found) 4 = B/G A2 5 = B/G NICAM 6 = D/K A2 (1) 7 = D/K A2 (2) 8 = D/K A2 (3) 9 = D/K NICAM10 = L NICAM11 = I NICAM12 = M Korea13 = M BTSC14 = M EIAJ15 = FM Radio, IF = 10.7 MHz, 50 us deemphasis16 = FM Radio, IF = 10.7 MHz, 75 us deemphasis17 = FM Radio, selectable IF, 50 us deemphasis18 = FM Radio, selectable IF, 75 us deemphasis31 = still searching for a standard (can occur onlyduring a few milliseconds)

GST [5] general stereo flag (ident source determined bycurrently detected or selected standard)$0 = No stereo mode$1 = Stereo mode detected

GDU [6] general dual flag$0 = No dual mode$1 = Dual mode detected

APILOT [7] A2 or EIAJ pilot tone detected$0 = False$1 = True

ADU [8] A2 or EIAJ ident dual flag$0 = False$1 = True

AST [9] A2 or EIAJ ident stereo flag$0 = False$1 = True

AAMUT [10] SC2 (if A2 mode) or EIAJ subchannel muted dueto noise$0 = False$1 = True



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BPILOT [11] BTSC or FM radio pilot tone detected (stereo indi-cator)$0 = False$1 = True

SAPDET [12] SAP carrier detected$0 = False$1 = True

BAMUT [13] BTSC stereo muted due to noise (if noise detectorenabled)$0 = False$1 = True

SAMUT [14] SAP muted due to noise (if noise detectorenabled)$0 = False$1 = True

VDSP_C [15] NICAM decoder VDSP flag$0 = DATA or undefined format$1 = SOUND

NICST_C [16] NICAM decoder stereo flag$0 = False$1 = True

NICDU_C [17] NICAM decoder dual flag$0 = False$1 = True

NAMUT [18] NICAM automute flag$0 = not muted$1 = muted (fallback to analog sound carrier)

RSSF [19] NICAM reserve sound switching flag (=C4), seeNICAM specification$0 = analog sound carrier conveys different con-tents than NICAM carrier$1 = analog sound carrier conveys same contentsas NICAM carrier (M1 if DUAL)

INITSTAT [20] initialization status (set to 0 upon read access)$0 = no reset performed$1 = reset has been applied to DSP and init rou-tine has been executed

- [23..21] reserved

$002 INF_NIC_STA_REG R ERR_OUT [7..0] NICAM error counter: number of parity errorsfound in the last 128ms period

CFC [8] NICAM ConFiguration Change$0 = No configuration change$1 = Configuration change at the 16 frame (CO)boundary

CO_LOCKED [9] NICAM frame and CO synchronization$0 = Audio output from NICAM part is digitalsilence$1 = Device has both frame and CO (16 frames)synchronization

NACB [13..10] NICAM application control bits (see C1..C4 inNICAM transmission)

VDSP [14] Identification of NICAM sound$0 = DATA or undefined format$1 = SOUND

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NICST [15] NICAM stereo flag$0 = No NICAM stereo mode (= Mono mode ifNICDU = $0)$1 = NICAM stereo mode

NICDU [16] NICAM dual mono mode$0 = No NICAM dual mono mode (= Mono mode ifNICST = $0)$1 = NICAM dual mono mode

- [23..17] reserved

$003 INF_NIC_ADD_REG R ADW [10..0] NICAM additional data word (11 bit per frame)

- [16..11] reserved, must be written as 0

DCXOCAPS [23..17] DCXO capacitor bank control signal (not yet imple-mented in PICASSO-100 N1)

$004 INF_LEV_MON_REG R MONLEVEL [23..0] monitor level

$005 INF_MPX_LEVEL_REG R - [5..0] reserved

MPXPLEV [23..6] MPX pilot level

$006 INF_DC1_REG R SC1_DC [23..0] DC offset from FM demodulator channel 1

$007 INF_SUBMAGN_REG R SUBMAGN [23..0] magnitude of FM subchannel

$008 INF_NOISELEVEL_REG R NDETCH_STAT [0] status noise detector channel0 = channel 11 = channel 2

NDETPB_STAT [1] status noise detector passband0 = low (2.5 fh)1 = high (7.5 fh)

NOISELEVEL [23..2] noise detector output

$009 INF_REVISION_ID_REG

R MAJOR_VERSION_NR

[3..0] major version number.

MINOR_VERSION_NR

[7..4] minor version number.incremented number means: control interface mayhave extensions for additional functions or func-tionality may have changed slightly; driver updaterecommended.

PATCH_LEVEL [11..8] patch level number.incremented number indicates bugfixes of theembedded software without any change of controlinterface or functionality.no driver update needed.

DEVICE_TYPE [15..12] device type ID (internal use)

ROM_ID [23..16] ROM identification code. Unique number for everyROM code ever released.

ABS.ADDR.HEX




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DEMDEC

$00A DEM_CFG_REG R/W DECPATH [2..0] $0 decoder path selection$0 = FM A2$1 = FM SAT with adaptive deemphasis$2= FM Radio$3 = NICAM + FM mono$4 = BTSC stereo + SAP with 150 us demphasis$5= BTSC mono + SAP with dbx$6 = EIAJ stereo$7= BTSC stereo flat & SAP flat (test mode)

FMDEEM [5..3] $0 fixed deemphasis for analog sound signals (notNICAM, not BTSC)$0 = 50 us (Europe)$1 = 60 us$2 = 75 us (M standard)$3 = J17$4 = OFF (flat)

CH2MOD [7..6] $0 operating mode of demodulator channel 2$0 = FM mode$1 = AM mode$2 = NICAM$3 = not used

CH1MOD [8] $0 operating mode of demodulator channel 1$0 = FM mode$1 = AM mode

INITLPF [9] $0 initialize loop filters in demodulator$0 = mormal operation$1 = initialize (reset states to 0)

- [10] $0 reserved, must be written as 0

FILTBW_M [12..11] $0 FM/AM demodulator filter bandwidth$0 = narrow$1 = extra wide (only ch. 1 active)$2 = medium$3 = wide

IDMOD_M [14..13] $0 FM ident speed$0 = slow$1 = medium$2 = fast$3 = off (reset)

IDAREA [16..15] $0 Area/regional code for FM-ident: Europe, Korea,Japan$0 = Europe$1 = Korea$2 = Japan$3 = Japan

BPILCAN [17] $0 MPX pilot cancellation$0 = False$1 = True

FM_MPX [18] $0 input from demodulator hardware at 4*fs$0 = FM / AM output$1 = MPX demodulator output (for BTSC and FMRADIO)

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ID_DC_LEVEL [20..19] $0 DC level for IDENT pilot detection$0 = Level > 3$1 = Level > 4$2 = Level > 5$3 = Level > 6

ID_BYBPF [21] $0 bypass bandpass filter level detector$0 = off$1 = on (reduced IDENT sensitivity)

ID_PGAIN [22] $00 IDENT pilot bandpass gain$0 = no gain$1 = +6 dB gain for EIAJ


$00B DEM_CA1_REG R/W CARRIER1 [23..0] $000000 sound carrier 1 (mixer 1) frequency$5DC000 = 4.5 MHz$729555 = 5.5 MHz$7D0000 = 6.0 MHz$876AAB= 6.5 MHz$DEEAAB = 10.7 MHz

$00C DEM_CA2_REG R/W CARRIER2 [23..0] $000000 sound carrier 2 (mixer 2) frequency$626AAB = 4.724 MHz$77A100 = 5.742 MHz$825F00 = 6.258 MHz$79E000 = 5.85 MHz$888000 = 6.552 MHz$8C7665 = 6.742 MHz$5DC000 = 4.5 MHz$729555 = 5.5 MHz

$00D DEM_MPXCFG_REG R/W - [0] $0 reserved, must be written as 0

MPX_PLL_BW [1] $0 MPX demodulator pilot PLL bandwidth$0 = 5Hz (default)$1 = 10Hz

MPX_FREQ [23..2] $000000 MPX pilot frequency$29F54 =15734 Hz (standard NTSC line fre-quency)$29AAA = 15625 Hz (PAL line frequency)$32AAA = 19000 Hz (FM radio)

$00E DEM_FMSUBCFG_REG R/W FMSUB_BW [0] $000000 FM subchannel and EIAJ MAIN filter bandwidth$0 = narrow$1 = wide

EIAJ_DELAY [2..1] $000000 delay fine adjustment in MAIN path for EIAJ stereo

NDETCH [3] $000000 noise detector channel$0 = channel 1$1 = channel 2

NDETPB [4] $000000 noise detector passband$0 = low (2.5 fh)$1 = high (7.5 fh)

- [7..5] $0 reserved, must be written as 0

FMSUB_FREQ [23..8] $000000 FM subchannel frequency (SAP or Japan)$3437 = 5 fh for SAP$14FB = 2 fh for EIAJ

$00F DEM_OUT_CFG_REG R/W DECSEL [1..0] $0 source for DEC output$0 = MONO output$1 = FM dematrix output$2 = NICAM decoder output

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FMDEMAT [4..2] $0 FM dematrix$0 = mono CH1$1 = mono CH2$2 = dual (identity matrix)$3 = stereo Europe$4 = stereo M standards (BTSC, Korea, Japan)and FM Radio

MONOSEL [5] $0 source for MONO output$0 = demod. channel 1$1 = ADC ch.1 = left (external demodulator)

MUTE_DEC_MONO

[6] $1 mute DEC and MONO outputs (softmute)$0 = no mute$1 = mute

MUTE_SAP [7] $1 mute SAP output (softmute)$0 = no mute$1 = mute


FM_SCALE [11..10] $0 scaling of FM and FM A2 signals$0 = 27 kHz nominal FM deviation (Europe)$1 = 15 kHz nominal FM deviation (M standards)$2 = 0 dB gain (BTSC, EIAJ, FM Radio)

ANLG_SCALE [23..12] $400 expert mode: internal scaling coefficient for allanalog demodulator signals. 1024 means 0 dB.

$010 MAGDET_THR_REG R/W MPX_PILOT_THR_UP

[3..0] $3 upper threshold for MPX pilot detection (BTSC, FMRADIO) in dB below nominal level

MPX_PILOT_THR_LO

[7..4] $9 lower threshold for MPX pilot detection (BTSC, FMRADIO) in dB below nominal level

SAP_CAR_THR_UP

[11..8] $3 upper threshold for SAP carrier detection in dBbelow nominal level

SAP_CAR_THR_LO

[15..12] $6 lower threshold for SAP carrier detection in dBbelow nominal level


ASD_SC1_THR [22..18] $0 threshold for detection of first sound carrier (SC1)during ASD first step, relative to -30 dBFS. -16 pre-vents ASD "failure" to produce output regardless ofcarrier level.


$011 NMUTE_FMA2_SAP_REG

R/W NMUTE_SAP_THR

[4..0] $0 noise threshold for automute of SAP (-16 meansautomute off)

NMUTE_SAP_HYST

[8..5] $4 hysteresis size [dB] for automute of SAP

NMUTE_SC2_THR

[13..9] $0 noise threshold for automute of SC2 in FM A2standards (-16 means automute off)

NMUTE_SC2_HYST

[17..14] $4 hysteresis size [dB] for automute of SC2 in FM A2standards


$012 NMUTE_MPX_REG R/W NMUTE_BTSC_THR

[4..0] $0 noise threshold for automute of BTSC stereo car-rier (-16 means automute off)

NMUTE_BTSC_HYST

[8..5] $4 hysteresis size [dB] for automute of BTSC stereo

NMUTE_FMRA_THR

[13..9] $0 noise threshold for automute of FM RADIO stereocarrier (-16 means automute off)

ABS.ADDR.HEX




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NMUTE_FMRA_HYST

[17..14] $4 hysteresis size [dB] for automute of FM RADIOstereo


$013 NMUTE_EIAJ_REG R/W NMUTE_EIAJ_THR

[4..0] $0 noise threshold for automute of EIAJ FM subcar-rier (-16 means automute off)

NMUTE_EIAJ_HYST

[8..5] $4 hysteresis size [dB] for automute of EIAJ FM sub-carrier

EIAJ_CAR_THR_UP

[12..9] 8 upper threshold for EIAJ SUB carrier detection indB below nominal level

EIAJ_CAR_THR_LO

[16..13] 12 lower threshold for EIAJ SUB carrier detection indB below nominal level

EIAJ_CAR_DETECT

[17] 1 enable EIAJ SUB carrier detector0 = sub carrier detector disabled1 = sub carrier detector enabled


$014 NICAM_CFG_REG R/W ONLY_RELATED

[0] $0 reproduce only related NICAM on DEC output(DDEP only)$0 = false (NICAM whenever possible)$1 = true (NICAM suppressed if RSSF=0)


EXTAM [2] $0 fall back source in case of automute in standard L(DDEP only)$0 = channel 1 output (AM)$1 = ADC output (external AM demodulator)

NICDEEM [3] $0 NICAM deemphasis (J17) (all modes)$0 = ON$1 = OFF

NIC_AMUTE [4] $0 NICAM auto mute function depending on bit errorrate (DDEP only)$0 = ON$1 = OFF

NICLOERRLIM [12..5] $64 NICAM lower error limit (DDEP only)

NICUPERRLIM [20..13] $C8 NICAM upper error limit (DDEP only)


$015 DDEP_CONTROL_REG R/W EPMODE [1..0] $0 DEMDEC Easy Programming (DDEP) mode$0 = 'AUTOSTANDARD' (ASD). STDSEL[4:0]defines the set of 'allowed' standards.$1 = 'STATIC STANDARD SELECT' (SSS). STD-SEL[4:0] contains standard code.$2 = Reserved$3 = DEMDEC expert mode (fully manual mode)

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STDSEL [6..2] $0 Bits multiplexed for ASD and SSS modes.In ASD mode (EPMODE=0): flags for allowedstandards B/G | D/K | L/L' | I | M (LSB to MSB).In SSS mode (EPMODE=1): standard code asdefined in status register STDRES, e.g. code 4selects B/G A2.For details please consult the documentation.

4 = B/G A2 5 = B/G NICAM 6 = D/K A2 (1) 7 = D/K A2 (2) 8 = D/K A2 (3) 9 = D/K NICAM10 = L NICAM / L'11 = I NICAM12 = M Korea13 = M BTSC14 = M EIAJ15 = FM Radio, IF = 10.7 MHz, 50 us deemphasis16 = FM Radio, IF = 10.7 MHz, 75 us deemphasis17 = FM Radio, selectable IF, 50 us deemphasis18 = FM Radio, selectable IF, 75 us deemphasis

REST [7] $0 RESTART decoder and initialize DEMDEC afterchannel switch, if changed from 0 to 1.

OVMADAPT [8] $1 FM overmodulation adaptation (avoids distortion,filter bandwidth and gain is chosen adaptively)$0 = disabled$1 = enabled (recommended)

DDMUTE [9] $0 mute DEMDEC output signals (softmute)$0 = no mute$1 = mute

FILTBW [11..10] $0 FM/AM demodulator filter bandwidth (likeFILTBW_M). NOT effective if BTSC, EIAJ, FMRA-DIO active, or if OVMADAPT=1$0 = narrow (recommended)$2 = medium$3 = wide$1 = extra wide (only ch. 1 active)

IDMOD [13..12] $0 FM ident speed in SSS mode (otherwise not effec-tive)$0 = slow$1 = medium$2 = fast$3 = off (reset)



SAPDBX [16] $0 SAP decompression mode$0 = dbx used for BTSC stereo decoding, fixedcompromise deemphasis for SAP (recommended)$1 = dbx used for SAP, BTSC stereo forced tomono

FHPAL [17] $0 line frequency for BTSC decoding$0 = NTSC line frequency (15.734 kHz) used inSSS, or preferred in ASD mode$1 = PAL line frequency (15.625 kHz) used inSSS, or preferred in ASD mode

ABS.ADDR.HEX




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OVMTHR [19..18] $1 overmodulation level threshold relative to nominal(applies if OVMADAPT=1)$0 = +3 dB = -12 dBFS$1 = +6 dB = - 9 dBFS (recommended)$2 = +9 dB = -6 dBFS$3 = +12 dB= -3 dBFS


LEVEL ADJUST

$016 LEV_ADJ_DEM_REG R/W DECLEV [4..0] $00 level adjust DEC ( +15..-15dB)(-16 = MUTE)

MONOLEV [9..5] $00 level adjust MONO ( +15..-15dB)(-16 = MUTE)

NICLEV [14..10] $00 extra gain for NICAM ( +15..-15dB)(-16 = MUTE)"

SAPLEV [19..15] $00 Level adjust SAP ( +15..-15dB)(-16 = MUTE)


$017 LEV_ADJ_IO_REG R/W ADCLEV [4..0] $00 level adjust ADC ( +15..-15dB)(-16 = MUTE)

IISLEV [9..5] $00 level adjust IIS ( +15..-15dB)(-16 = MUTE)


AUDIO SWITCHING

$018 ASW_MA_C_S_REG R/W MAINSS [4..0] $00 SIGNAL SOURCE MAIN$00 = DEC$01 = MONO$02 = SAP$03 = ADC$04 = IIS$05 = Noise Generator$06 = Silence Generator

MAINDM [7..5] $0 DIGITAL MATRIX MAIN$0 = AB [Stereo] (automatrix off)$1 = (A+B)/2 [Mono] (automatrix off)$2 = AA [Lang. A] (automatrix off)$3 = BB [Lang. B] (automatrix off)$4 = BA [Swap] (automatrix off)$5 = not used$6 = Language A (automatrix on)$7 = Language B (automatrix on)

CENTERSS [12..8] $06 SIGNAL SOURCE CENTER$00 = DEC$01 = MONO$02 = SAP$03 = ADC$04 = IIS$05 = Noise Generator$06 = Silence Generator

ABS.ADDR.HEX




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SURROUNDSS [17..13] $06 SIGNAL SOURCE SURROUND$00 = DEC$01 = MONO$02 = SAP$03 = ADC$04 = IIS$05 = Noise Generator$06 = Silence Generator


$019 ASW_A1_A2_A3_REG R/W AUX1SS [4..0] $00 SIGNAL SOURCE AUX1$00 = DEC$01 = MONO$02 = SAP$03 = ADC$04 = IIS$05 = Noise Generator$06 = Silence Generator

AUX1DM [7..5] $0 DIGITAL MATRIX AUX1$0 = AB [Stereo] (automatrix off)$1 = (A+B)/2 [Mono] (automatrix off)$2 = AA [Lang. A] (automatrix off)$3 = BB [Lang. B] (automatrix off)$4 = BA [Swap] (automatrix off)$5 = not used$6 = Language A (automatrix on)$7 = Language B (automatrix on)

AUX2SS [12..8] $00 SIGNAL SOURCE AUX2$00 = DEC$01 = MONO$02 = SAP$03 = ADC$04 = IIS$05 = Noise Generator$06 = Silence Generator


AUX3SS [20..16] $0 SIGNAL SOURCE AUX3$00 = DEC$01 = MONO$02 = SAP$03 = ADC$04 = IIS$05 = Noise Generator$06 = Silence Generator

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$01A ASW_DAFO1_2_REG R/W ASAFO1 [3..0] $0 OUTPUT SELECTION for DAFO1 to DAC2L$0 = MAIN/L$1 = MAIN/R$2 = SUBWOOFER$3 = CENTER$4 = SURROUND$5 = AUX1/L$6 = AUX1/R$7 = AUX2/L$8 = AUX2/R$9 = AUX3/L$A = AUX3/R$B = MAIN SUM$C = digital silence

ASAFO2 [7..4] $1 OUTPUT SELECTION for DAFO2 to DAC2R$0 = MAIN/L$1 = MAIN/R$2 = SUBWOOFER$3 = CENTER$4 = SURROUND$5 = AUX1/L$6 = AUX1/R$7 = AUX2/L$8 = AUX2/R$9 = AUX3/L$A = AUX3/R$B = MAIN SUM$C = digital silence


$01B ASW_DAC_I2S_OCO_REG

R/W ASDAC1L [3..0] $0 OUTPUT SELECTION for DAC1L$0 = MAIN/L$1 = MAIN/R$2 = SUBWOOFER$3 = CENTER$4 = SURROUND$5 = AUX1/L$6 = AUX1/R$7 = AUX2/L$8 = AUX2/R$9 = AUX3/L$A = AUX3/R$B = MAIN SUM$C = digital silence

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ASDAC1R [7..4] $1 OUTPUT SELECTION for DAC1R$0 = MAIN/L$1 = MAIN/R$2 = SUBWOOFER$3 = CENTER$4 = SURROUND$5 = AUX1/L$6 = AUX1/R$7 = AUX2/L$8 = AUX2/R$9 = AUX3/L$A = AUX3/R$B = MAIN SUM$C = digital silence

ASI2S1L [11..8] $0 OUTPUT SELECTION for I2S1L$0 = MAIN/L$1 = MAIN/R$2 = SUBWOOFER$3 = CENTER$4 = SURROUND$5 = AUX1/L$6 = AUX1/R$7 = AUX2/L$8 = AUX2/R$9 = AUX3/L$A = AUX3/R$B = MAIN SUM$C = digital silence

ASI2S1R [15..12] $1 OUTPUT SELECTION for I2S1R$0 = MAIN/L$1 = MAIN/R$2 = SUBWOOFER$3 = CENTER$4 = SURROUND$5 = AUX1/L$6 = AUX1/R$7 = AUX2/L$8 = AUX2/R$9 = AUX3/L$A = AUX3/R$B = MAIN SUM$C = digital silence

ASI2S2L [19..16] $0 OUTPUT SELECTION for I2S2L$0 = MAIN/L$1 = MAIN/R$2 = SUBWOOFER$3 = CENTER$4 = SURROUND$5 = AUX1/L$6 = AUX1/R$7 = AUX2/L$8 = AUX2/R$9 = AUX3/L$A = AUX3/R$B = MAIN SUM$C = digital silence

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ASI2S2R [23..20] $1 OUTPUT SELECTION for I2S2R$0 = MAIN/L$1 = MAIN/R$2 = SUBWOOFER$3 = CENTER$4 = SURROUND$5 = AUX1/L$6 = AUX1/R$7 = AUX2/L$8 = AUX2/R$9 = AUX3/L$A = AUX3/R$B = MAIN SUM$C = digital silence

$01C ASW_MUT_CON_REG R/W MAINMUT [0] $1 Softmute MAIN/L,R output$0 = OFF$1 = ON

MAINLMUT [1] $0 Softmute MAIN/L output$0 = OFF$1 = ON

MAINRMUT [2] $0 Softmute MAIN/R output$0 = OFF$1 = ON

SUBWMUT [3] $1 Softmute SUBWOOFER output$0 = OFF$1 = ON

CENTERMUT [4] $1 Softmute CENTER output$0 = OFF$1 = ON

SURROUND-MUT

[5] $1 Softmute SURROUND output$0 = OFF$1 = ON

AUX1MUT [6] $1 Softmute AUX1 output$0 = OFF$1 = ON




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SOUND PROCESSINGMODE

$01D SOU_APP_MOD_REG R/W EXEMODTAB [0] $0 Execute 'Mode Table'

After a transition from '0' to '1' the selected 'ModeTable' is executed once. Afterwards it should becleared again.(If ControlMode='0')

SNDMOD [5..1] $00 Sound Modes$0 = Mono/Stereo (default)$1 = Mono/Stereo (HALL)$2 = Mono/Stereo (MATRIX)$3 = DPL (normal Centre)$4 = DPL (3 Stereo)$5 = DPL (Phantom Centre)$6 = VDS422$7 = VDS423$8 = SRS TruSurround (DPL)$9 = Noise Sequencing$A = SRS TruSurround (Passive Matrix)

CLIPMANAGE [8..6] $0 Clip Management$0 = Clip management OFF (default)$1 = Static Volume Mode$2 = Static Control Mode$3 = Dynamic Control Mode$4 = Dynamic Volume Mode$5 = Reserved$6 = Reserved$7 = Reserved

MAINSUBCTRL [9] $0 Main/Subwoofer signal output control$0 = Normal Subwoofer Mode$1 = Economic Subwoofer Mode

EQBYPASS [10] $0 EQ enable for Main and Center channel$0 = EQ bypass off$1 = EQ bypass on


SOUND EFFECTS

$01E SOU_EFF_REG R/W BBECONTOUR [3..0] $0 BBE Contour value

$0 = Min. bass boost$F = Max. bass boost

BBEPROCESS [7..4] $0 BBE Process value

$0 = Min. process$F = Max. process

MAINLOUD [8] $0 MAIN loudness$0 = OFF$1 = ON

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MAINLONA [11..9] $0 MAIN loudness none attack volume level$0 = -15dB Volume$1 = -12dB Volume$2 = -9dB Volume$3 = -6dB Volume$4 = -3dB Volume$5 = 0dB Volume$6 = +3dB Volume$7 = +6dB Volume

MAINLOCH [13..12] $0 MAIN loudness filter characteristic (bass/treble indB)$0 = standard (500Hz)$1 = extra bass (1000Hz)

bass: 20 Hz -> max. 18.3 dBtreble: 16 kHz -> max. 4.3 dB

BASSFEA-TURECTRL

[16..14] $0 DBE, DUB and BBE control$0 = DBE, DUB and BBE Off$1 = DBE main channel On$2 = DUB main channel On$3 = DBE subwoofer channel On$4 = DUB subwoofer channel On$5 = BBE On


$01F MAIN_SOU_EFF_REG R/W SOMOCTRL [1..0] $0 Spatializer sound effect0 = OFF1 = I-Stereo2 = I-Mono3 = 3D Sound

INSOEF [4..2] $3 I-Mono or I-Stereo Effect: Min..Max (6 steps)$0 = 1 (Min)$1 = 2$2 = 3$3 = 4$4 = 5$5 = 6 (Max)

AVLMOD [7..5] $0 AVL mode$0 = OFF$1 = very short decay (20 ms)$2 = short decay (2 sec)$3 = medium decay (4 sec)$4 = long decay (8 sec)$5 = very long decay (16 sec)

AVLWEIGHT [8] $1 AVL weighting filter$0 = OFF$1 = ON (recommended)

AVLLEV [12..9] $7 AVL reference level (16 steps: -6,-8,... -36 dBFS)$2 = high threshold (-10 dBFS), small reduction("daytime mode")$7 = medium threshold (-20 dBFS), mediumreduction ("evening mode")$C = low threshold (-30 dBFS), strong reduction("night mode")

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SRS3DCENTER

[16..13] $1 SRS 3D Sound Center$0 = -9dB$1 = -14dB$2 = -15dB$3 = -16dB$4 = -17dB$5 = -18dB$6 = -19dB$7 = -20dB$8 = -21dB$9 = -22dB$A = -23dB$B = -24dB$C = -25dB$D = -26dB$E = -27dB$F = off

SRS3DSPACE [20..17] $0 SRS 3D Sound Space$0 = -4dB$1 = -5dB$2 = -6dB$3 = -7dB$4 = -8dB$5 = -9dB$6 = -10dB$7 = -11dB$8 = -12dB$9 = -13dB$A = -14dB$B = -15dB$C = -16dB$D = -17dB$E = -18dB$F = off

SRS3DBYPASS

[21] $0 SRS 3D Sound bypass mode switch for test pur-pose$0 = 3D Sound active$1 = Bypass active


$020 DBE_COEF_DOWNL_REG

R/W DBEADR [5..0] $0 DBE coefficient address


DBECOEF [23..12] $0 DBE coefficients

$021 DUB_COEF_DOWNL_REG

R/W DUBADR [7..0] $0 DUB coefficient address


DUBCOEF [23..12] $0 DUB coefficients

$022 DOL_CON_REG R/W VDSMIXLEV [2..0] $0 VDS mix level: 0..100% (5 steps)$0 = 0%$1 = 20%$2 = 40%$3 = 60%$4 = 80%$5 = 100%

>$5 = reserved

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DPLDEL [7..3] $00 Dolby Prologic : Delayline values: 15..30 ms in 32steps.

$00 = No delay$01 = min. delay$1F = max. delay

BAMAMO [9..8] $0 Bass management mode$0 = OFF (Wide Centre Mode)$1 = TYP1 configuration (Normal Centre Mode)$2 = TYP2 configuration (Normal Centre Mode)

BAMASUB [10] $0 Bass Management subwoofer filter control$0 = Subwoofer filter Off$1 = Subwoofer filter On

BAMAFC [14..11] $0 Bass management lowpass filtercharacteristics:50 - 400Hz (in 4 Bit resolution)) cornerfrequency.Highpass filter is 1/lowpass.$0 = 50 Hz$1 = 60 Hz$2 = 70 Hz$3 = 80 Hz$4 = 90 Hz$5 = 100 Hz$6 = 110 Hz$7 = 120 Hz$8 = 130 Hz$9 = 140 Hz$A = 150 Hz$B = 200 Hz$C = 250 Hz$D = 300 Hz$E = 350 Hz$F = 400 Hz

FLAT_7KHZ_FILTER

[15] $0 Dolby Surround ProLogic filter for test purpose$0 = OFF$1 = ON

B_TYPE_FLAT [16] $0 Dolby Surround ProLogic filter for test purpose$0 = OFF$1 = ON

ABALCFG [17] $1 Dolby Surround ProLogic autobalance for test pur-pose$0 = OFF$1 = ON


Delay-LineSwitch

[23] $00 Shift the delay from the DLU to the XMEM$0 = XMEM$1 = DLU

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SOUND

$023 MASTER_VOL_REG R/W MASTERVOL [10..0] $0 Master volume: (+24..-83.875dB, mute ), controlsMAIN, SW, C and S in 1/8dB steps

192 = +24.000 dB191 = +23.875 dB..184 = +23.000 dB.. 0 = 0.000 dB -1 = -0.125 dB..-671 = -83.875 dB-672 = mute

BEEPVOL [18..11] $AC Beeper volume: (0..-83dB, mute)

0 = 0 dB-1 = -1 dB..-84 = mute

BEEPFREQ [21..19] $0 Beeper frequency: 200..12500 Hz$0 = 200 Hz$1 = 400 Hz$2 = 1000 Hz$3 = 2000 Hz$4 = 3000 Hz$5 = 5000 Hz$6 = 8000 Hz$7 = 12500 Hz


$024 MAI_VOL_REG R/W MAINVOLL [7..0] $00 MAIN volume left: (+24..-83dB, mute)

24 = +24 dB23 = +23 dB..-84 = mute

MAINVOLR [15..8] $00 MAIN volume right: (+24..-83dB, mute)

24 = +24 dB23 = +23 dB..-84 = mute


$025 SW_C_S_VOL_REG R/W SUBWVOL [7..0] $0 SUBWOOFER volume: (+24..-83dB, mute)

24 = +24 dB23 = +23 dB..-84 = mute

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CENTERVOL [15..8] $0 CENTER volume: (+24..-83dB, mute)

24 = +24 dB23 = +23 dB..-84 = mute

SURROUND-VOL

[23..16] $0 SURROUND volume: (+24..-83dB, mute)

24 = +24 dB23 = +23 dB..-84 = mute

$026 AUX1_VOL_REG R/W AUX1VOLL [7..0] $00 AUX1 volume left: (+24..-83dB, mute)

24 = +24 dB23 = +23 dB..-84 = mute

AUX1VOLR [15..8] $00 AUX1 volume rigth: (+24..-83dB, mute)

24 = +24 dB23 = +23 dB..-84 = mute



24 = +24 dB23 = +23 dB..-84 = mute


24 = +24 dB23 = +23 dB..-84 = mute



24 = +24 dB23 = +23 dB..-84 = mute


24 = +24 dB23 = +23 dB..-84 = mute


$029 MAI_TON_CON_REG R/W MAINBASS [4..0] $00 MAIN bass: (+15..-16dB, 1 dB steps)

15 = +15 dB..-16 = -16 dB

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MAINTREB [9..5] $00 MAIN treble: (+15..-16dB, 1 dB steps)

15 = +15 dB..-16 = -16 dB


$02A CENTER_TON_CON_REG

R/W CENTERBASS [4..0] $0 CENTERbass: (+15..-16dB, 1 dB steps)

15 = +15 dB..-16 = -16 dB

CENTERTREB [9..5] $0 CENTERtreble: (+15..-16dB, 1 dB steps)

15 = +15 dB..-16 = -16 dB


$02B SUR_TON_CON_REG R/W SURROUND-BASS

[4..0] $0 SURROUNDbass: (+15..-16dB, 1 dB steps)

15 = +15 dB..-16 = -16 dB

SUR-ROUNDTREB

[9..5] $0 SURROUNDtreble: (+15..-16dB, 1 dB steps)

15 = +15 dB..-16 = -16 dB


$02C EQMAIN1_TON_CON_REG

R/W EQCHM1 [4..0] $0 Equalizer MAIN Channel Band 1 (100 Hz)

12 = +12dB..-12 = -12dB

EQCHM2 [9..5] $0 Equalizer MAIN Channel Band 2 (300 Hz)

12 = +12dB..-12 = -12dB


12 = +12dB..-12 = -12dB


$02D EQMAIN2_TON_CON_REG

R/W EQCHM4 [4..0] $0 Equalizer MAIN Channel Band 4 (3000 Hz)

12 = +12dB..-12 = -12dB


12 = +12dB..-12 = -12dB


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$02E EQCENTER1_TON_CON_REG

R/W EQCHC1 [4..0] $0 Equalizer CENTER Channel Band 1 (100 Hz)

12 = +12dB..-12 = -12dB

EQCHC2 [9..5] $0 Equalizer CENTER Channel Band 2 (300 Hz)

12 = +12dB..-12 = -12dB


12 = +12dB..-12 = -12dB


$02F EQCENTER2_TON_CON_REG

R/W EQCHC4 [4..0] $0 Equalizer CENTER Channel Band 4 (3000 Hz)

12 = +12dB..-12 = -12dB


12 = +12dB..-12 = -12dB


MONITOR

$030 MON_SEL_REG R/W MON_SRC [4..0] $00 source for monitor function$00 = FM,AM,MPX (1 fs) input$01 = FM,AM,MPX (4 fs) input$02 = FM/AM/BTSC/EIAJ DC$03 = FM dematrix output (at DECSEL switch)$04 = NICAM (at DECSEL switch)$05 = MONO (at DECSEL switch)$06 = DEC (at dig. input crossbar)$07 = MONO (at dig. input crossbar)$08 = SAP (at dig. input crossbar)$09 = ADC (at dig. input crossbar)$0A = IIS (at dig. input crossbar)$0B = Noise / silence generator (at dig. inputcrossbar)$0C = MAIN (at dig. output crossbar)$0D = SUBWOOFER (at dig. output crossbar)$0E = CENTER (at dig. output crossbar)$0F = SURROUND (at dig. output crossbar)$10 = AUX1 (at dig. output crossbar)$11 = AUX2 (at dig. output crossbar)$12 = AUX3 (at dig. output crossbar)$13 = MAIN SUM (at dig. output crossbar)$14 = MAIN (after Bass Management)$15 = SUBWOOFER (after Bass Management)$16 = CENTER (after Bass Management)$17 = SURROUND (after Bass Management)

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MON_DET [6..5] $3 detection type for monitor function$0 = random samples$1 = absolute value peak detection$2 = quasi peak detection$3 = off / reset peak detector

MON_MAT [9..7] $0 matrix for monitor source$0 = A$1 = (A+B)/2$2 = B$3 = (A-B)/2 (2-ch. sources only)


GENERAL CONTROL

$031 GEN_CTRL_REG R/W I2S_FORMAT [1..0] $0 IIS format control$0 = Philips format$1 = Sony format$2 = Japanese 24 bit$3 = Japanese 24 bit

DAC_DWA [2] $00 DAC: data weighted averaging$0 = uni-directional, better THD at low levels$1 = bi-directional


DEMDEC

$032 DCXO_CTRL_REG R/W NICLPINV [0] 1 DCXO scaling control inverter0 = not inverted1 = inverted

NICLPSCALE [3..1] 3 DCXO scaling control gain0 = 1.01 = 0.1252 = 0.2503 = 0.3754 = 0.5005 = 0.6256 = 0.7507 = 0.875

NICLPLIM [12..4] 511 DCXO scaling control limit (+/- limit), no clipping ofcontrol signal if >= 256*scalefactor

NICLPCENTER [22..13] 0 DCXO scaling control center

- [23] 0 reserved, must be written as 0

$033 DDEP_OPTIONS1_REG R/W - [3..0] 0 reserved, must be written as 0

IDMOD_SLOW_EUR

[5..4] 0 in ASD mode, IDMOD setting when European A2standards (B/G, D/K) are detected0 = slow1 = medium2 = fast

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Refresh cycle

Minimum refresh cycle period (worst case) can be calculated as follows:

Max 42 write registers with 3 datawords each. Each dataword consists of 8 databits + acknowledge bit. If auto incrementis applied 1 deviceaddress + 1 subaddress (2 Bytes) is additionally needed. So in total 43* 3 * 9 = 1161 Bits are neededfor one transfer. Assuming max. I2C speed (400 kbits/sec) a total time of 1/400k * 1161 = 2.9 msec is needed. So thenext transfer cycle (=refresh) cannot start earlier.

The following table is an extract of the full address range. Refresh procedure depends on automatic feature(autostandard detection).

Table 267 Overview SSD I2C address range wrt. refresh cycle

IDMOD_SLOW_KOR

[7..6] 0 in ASD mode, IDMOD setting when M Korea stan-dard detected0 = slow1 = medium2 = fast

IDMOD_SLOW_JAP

[9..8] 1 in ASD mode, IDMOD setting when EIAJ standarddetected0 = slow1 = medium2 = fast

- [18..10] 0 reserved, must be written as 0

SAP_BW [19] 0 SAP filter bandwidth selection0 = narrow filter1 = wide filter

- [23..20] 0 reserved, must be written as 0

Addressspace

Refresh with DDEP mode Refresh without DDEP

$0001-$0009 Read only Read only

$000A-$000F - Yes

$0010-$0015 Yes Yes

$0016-$0033 End refresh cycle End refresh cycle

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LIMITING VALUESIn accordance with the Absolute Maximum Rating System (IEC 134).

Notes

1. This maximum value has an absolute maximum of 5.5 V independent of VDD.

2. All pins are protected against ESD by means of internal clamping diodes.

3. Human Body Model (HBM): R = 1.5 kΩ; C = 100 pF.

4. Machine Model (MM): R = 0 Ω; C = 200 pF.

5. All pins meet this requirement except pin 68 (VSScomb) which can handle a stress voltage of ±150 V.

THERMAL CHARACTERISTICS

QUALITY SPECIFICATION

In accordance with “SNW-FQ-611E”.

Latch-up

At an ambient temperature of 70 °C all pins meet the following specification:

• Itrigger ≥ 100 mA or ≥1.5VDD(max)

• Itrigger ≤ −100 mA or ≤−0.5VDD(max).

Note:

The SDA pin (pin 109 of the “standard version” or pin 20 of the “face down version) does not meet this specification andhas a maximum trigger current of −20 mA. For the positive current it meets the requirement of 100 mA.

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

VP supply voltage − 5.5 V

VDDA supply voltage (analogue) −0.5 3.6 V

VDDP supply voltage (periphery) −0.5 3.6 V

VDDC supply voltage (core) −0.5 1.95 V

VI digital inputs note 1 −0.5 VDD+ 0.5 V

VO digital outputs note 1 −0.5 VDD+ 0.5 V

IO output current (each output) − ±10 mA

Tstg storage temperature −25 +150 °CTamb operating ambient temperature 0 70 °CTsol soldering temperature for 5 s − 260 °CTj operating junction temperature − 150 °CVes electrostatic handling HBM; all pins; notes 2 and 3 −2000 +2000 V

MM; all pins; notes 2, 4 and 5 −200 +200 V

SYMBOL PARAMETER VALUE UNIT

Rth j-a thermal resistance from junction to ambient in free air (QFP-128) tbf K/W

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CHARACTERISTICS OF MICRO-COMPUTER AND TEXT DECODERVDD = 3.3 V ± 10%; VSS = 0 V; Tamb = 0 to +70 °C; unless otherwise specified

NUMBER PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

VM.1.1 supply voltage (VDDA) 3.0 3.3 3.6 V

VM.1.2 supply voltage (VDDP) 3.0 3.3 3.6 V

VM.1.3 supply voltage (VDDC) 1.65 1.8 1.95 V

VM.1.4 periphery supply current (IDDP) note 1 1 − − mA

VM.1.5 core supply current (IDDC) normal mode − 440 tbf mA

VM.1.6 supply current IDDA + IDDP normal mode − 28 tbf mA

VM.1.7 supply current IDDA + IDDP stand-by mode − 15 tbf mA

VM.1.8 supply current IDDA + IDDP idle mode − 9 tbf mA

VM.1.9 supply current IDDA + IDDP power down mode − 7.5 tbf mA

Digital input/outputs

P0.0 TO P0.5, P1.0 TO P1.5, P2.0 TO P2.5 AND P3.0 TO P3.3

IO.1.1 low level input voltage − − 0.8 V

IO.1.2 high level input voltage 2 − − V

IO.1.3 hysteresis of Schmitt Triggerinput

0.4 − − V

IO.1.4 low level output voltage IOL = 4 mA − − 0.4 V

IO.1.5 high level output voltage open drain − − 3.3 V

IO.1.6 high level output voltage IOH = 4 mA; push pull VDDE − 0.4 − − V

IO.1.7 output rise time (push-pull only)10% to 90%

load 40 pF − 5 − ns

IO.1.8 output fall time 10% to 90% load 40 pF − 5 − ns

IO.1.9 load capacitance − − 100 pF

IO.1.10 capacitance of input pin − − 1 pF

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Note

1. Peripheral current is dependent on external components and voltage levels on I/Os

2. The simplified circuit diagram of the oscillator is given in Fig.52.

A suitable crystal for this oscillator is the Saronix type 9922 520 20264.

P1.6 AND P1.7 (OPEN DRAIN)

IO.2.1 low level input voltage (VIL) − − 0.8 V

IO.2.2 high level input voltage (VIH) 2 − − V

IO.2.3 hysteresis of Schmitt-triggerinput

0.4 − − V

IO.2.4 low level output voltage sink current 4 mA − − 0.4 V

IO.2.5 high level output voltage − − 3.3 V

IO.2.6 output fall time 10% to 90% P1.6; load 160 pF − 180 − ns

IO.2.7 output fall time 10% to 90% P1.7; load 400 pF − 140 − ns

IO.2.8 bus load capacitance − − 400 pF

IO.2.9 capacitance of IO pin − − 1 pF

Crystal oscillator

OSCIN; NOTE 2

X.1.1 resonator frequency − 24.576 − MHz

X.1.2 input capacitance (Ci) − tbf − pF

X.1.3 output capacitance (Co) − tbf − pF

X.1.4 Ri (crystal) − − 100 ΩX1.5 maximum load capacitance Cx1 or Cx2 in Fig 52 − − 25 pF


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CHARACTERISTICS OF STEREO DECODER AND DIGITAL AUDIO PROCESSORVSIF(p-p) = 300 mV; AGCOFF = 0; AGCSLOW = 0; AGCLEV = 0; level and gain setting in accordance with note tbn;VDD1,2,3 = 3.3 V;VDDA5 = 5.0 V; Tamb = 25 °C; settings in accordance with B/G standard; FM deviation ±50 kHz;fmod = 1 kHz; FM sound parameters in accordance with system A2; NICAM in accordance with EBU specification; 1 kΩmeasurement source resistance for AF inputs; unless otherwise specified;

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

VSSC4 digital supply ground forAudio-DAC

- 0.0 - V

VDDC4 digital supply voltage forAudio-DAC

1.65 1.8 1.95 V

VDDA3 analogue supply voltage forAudio-DAC

VREF_POS

-0.253.3 3.6 V

VDDA analogue supply voltage forAudio-ADC

1.6 1.8 2.0 V

GNDA analogue supply ground forAudio-ADC

- 0.0 - V

VDDA2 analogue supply voltage forAudio-ADC

3.0 3.3 3.6 V

VDDC2 digital supply voltage forSIF-ADC

1.6 1.8 2.0 V

VSSC2 digital supply ground forSIF-ADC

- 0.0 - V

VDDC3 digital supply voltage forAudio-ADC

1.6 1.8 2.0 V

VSSC3 digital supply ground forAudio-ADC

- 0.0 - V

References

VREF_POS_LSL

positive analog referencevoltage for SDAC “LSL”

0.8 3.3 3.6 V

VREF_NEG_LSL+LSR

negative analog referencevoltage for SDAC “LSL+LSR”

- 0.0 - V

VREF_POS_LSR+HPL

positive analog referencevoltage for SDAC “LSR+HPL”

0.8 3.3 3.6 V

VREF_NEG_HPL+HPR

negative analog referencevoltage for SDAC “HPL+HPR”

- 0.0 - V

VREF_POS_HPR

positive analog referencevoltage for SDAC “HPR”

0.8 3.3 3.6 V

VREFAD_POS

positive analog referencevoltage for Audio-ADC

3.0 3.3 3.6 V

VREFAD_NEG

negative analog referencevoltage for Audio-ADC

- 0.0 - V

VREFAD analog reference voltage forAudio-ADC

VDDA2/2 V

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Demodulator performance;

THD + N total harmonic distortion plusnoise

from FM source to anyoutput; Vo = 1 V (rms) withlow-pass filter

− 0.35 0.5 %

from NICAM source to anyoutput; Vo = 1 V (rms) withlow-pass filter

− 0.1 0.3 %

S/N signal-to-noise ratio SC1 from FM source to anyoutput; Vo = 1 V (rms);CCIR468; quasi peak

64 70 − dB

SC2 from FM source to anyoutput; Vo = 1 V (rms);CCIR468; quasi peak

60 66 − dB

NICAM source;Vo = 1 V (rms)

NICAM in accordance withEBU specification; note tbn

B−3 −3 dB bandwidth from FM source to anyoutput

14.5 15 − kHz

from NICAM source to anyoutput

14.5 15 − kHz

FR frequency response20 Hz to 14 kHz

from FM or NICAM to anyoutput; fref = 1 kHz;inclusive pre-emphasis andde-emphasis

− ±2 − dB

αcs(dual) dual signal channel separation 65 70 − dBαcs(stereo) stereo channel separation 40 45 − dBαAM AM suppression for FM AM: 1 kHz,

30% modulation; reference:1 kHz, 50 kHz deviation

50 − − dB

S/NAM AM demodulation 2ndSIF level 100 mV (rms);54% AM; 1 kHz AF;CCIR468; quasi peak

36 45 − dB

IDENTIFICATION FOR FM SYSTEMS

modp pilot modulation foridentification

25 50 75 %

C/Np pilot sideband C/N foridentification start

− 27 −

fident identification window B/G stereoslow mode 116.85 − 118.12 Hzmedium mode 116.11 − 118.89 Hzfast mode 114.65 − 120.46 Hz

B/G dualslow mode 273.44 − 274.81 Hzmedium mode 272.07 − 276.20 Hzfast mode 270.73 − 277.60 Hz


dBcHz----------

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tident total identification time ON orOFF

slow mode − − 2 smedium mode − − 1 sfast mode − − 0.5 s

Audio performance (D/A)

THD + N total harmonic distortion plusnoise

output voltage at 0dBFS;Vo = 1.0 V (rms); fi = 1 kHz;bandwidth20 Hz to 14 kHz;

− 0.1 0.3 %

S/N signal-to-noise ratio output reference levelVo = 1.0 V (rms); fi = 1 kHz;CCIR468; RMS; from I2S toD/A;

- 80 − dB

αct crosstalk attenuation between any analog audiosignal pairs; fi = 1 kHz

70 − − dB

αcs channel separation between left and right ofany analog audio signalpair

65 − − dB


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CHARACTERISTICS OF TV-PROCESSORVP = 5 V; Tamb = 25 °C; unless otherwise specified.


Supplies

MAIN SUPPLY; NOTE 1

V.1.1 main supply voltage note 2 4.7 5.0 5.3 V

V.1.2 digital supply voltage 3.0 3.3 3.6 V

V.1.3 audio supply voltage note 3 4.7 8.0 8.4 V

V.1.4 main supply current (5 V) − 190 − mA

V.1.5 digital supply current (3.3 V) − 8 − mA

V.1.6 audio supply current (5.0/8.0 V) − 0.5 − mA

V.1.7 total power dissipation − 980 − mW

IF circuit

VISION IF AMPLIFIER INPUTS

input sensitivity (RMS value) note 4

M.1.1 fi = 38.90 MHz − 75 150 µV

M.1.2 fi = 45.75 MHz − 75 150 µV

M.1.3 fi = 58.75 MHz − 75 150 µV

M.1.4 input resistance (differential) note 5 − 2 − kΩM.1.5 input capacitance (differential) note 5 − 3 − pF

M.1.6 gain control range 64 − − dB

M.1.7 maximum input signal(RMS value)

150 − − mV

PLL DEMODULATOR; NOTES 6 AND 7

M.2.1 Free-running frequency of VCO PLL not locked, deviationfrom nominal setting

−500 − +500 kHz

M.2.2 Catching range PLL without SAW filter − ±1 − MHz

M.2.3 delay time of identification via LOCK bit − − 20 ms

VIDEO AMPLIFIER OUTPUT (IFOUT); NOTE 8

M.3.1 zero signal output level negative modulation; note 9 − 3.6 − V

M.3.2 positive modulation; note 9 − 1.4 − V

M.3.3 top sync level negative modulation 1.3 1.4 1.5 V

M.3.4 white level positive modulation − 3.4 − V

M.3.5 difference in amplitude betweennegative and positive modulation

− 0 15 %

M.3.6 video output impedance − 50 − ΩM.3.7 internal bias current of NPN

emitter follower output transistor1.0 − − mA

M.3.8 maximum source current − − 5 mA

M.3.9 bandwidth of demodulatedoutput signal

at −3 dB 6 7 − MHz

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VIDEO AMPLIFIER (CONTINUED)

M.3.10 differential gain note 10 − 2 5 %

M.3.11 differential phase notes 10 and 11 − − 5 deg

M.3.12 video non-linearity note 12 − − 5 %

M.3.13 white spot clamp level − 3.8 − V

M.3.14 noise inverter clamping level note 13 − 1.2 − V

M.3.15 noise inverter insertion level(identical to black level)

note 13 − 2.3 − V

intermodulation notes 11 and 14

M.3.16 blue Vo = 0.92 or 1.1 MHz 60 66 − dB

M.3.17 Vo = 2.66 or 3.3 MHz 60 66 − dB

M.3.18 yellow Vo = 0.92 or 1.1 MHz 56 62 − dB

M.3.19 Vo = 2.66 or 3.3 MHz 60 66 − dB

signal-to-noise ratio notes 11 and 15

M.3.20 weighted 56 60 − dB

M.3.21 unweighted 49 53 − dB

M.3.22 residual carrier signal note 11 − 5.5 − mV

M.3.23 residual 2nd harmonic of carriersignal

note 11 − 2.5 − mV

VIDEO OUTPUT/INPUT (IFVO/SVO/CVBSI), CONTROLLED BY THE SVO1/SVO0 BITS; SEE NOTE 16

M.3.24 output signal amplitude(peak-to-peak value)

SVO1/SVO0 = 0/0 or 0/1 − 2.0 − V

M.3.25 top sync level SVO1/SVO0 = 0/0 or 0/1 − 0.5 − V

M.3.26 output impedance SVO1/SVO0 = 0/0 or 0/1 − − 50 ΩM.3.27 CVBS input voltage

(peak-to-peak value)SVO1/SVO0 = 1/0 − 1.0 1.4 V

M.3.28 input current SVO1/SVO0 = 1/0 − 2 − µA

GROUP DELAY CORRECTION, SEE FIGURES 63 AND 64; NOTE 17

M.3.29 group delay sound trap only at f=4.43MHz; sound trapfrequency 5.5 MHz

− 180 − ns

M.3.30 group delay sound trap plusgroup delay correction filter

at f=4.43MHz; sound trapfrequency 5.5 MHz

− 170 − ns

SOUND TRAP

M.3.31 -3 dB video bandwidth (soundtrap + group delay)

fSC1=4.5MHz 3.90 4.00 − MHz

fSC1=5.5MHz 4.80 4.90 − MHz

fSC1=6.0MHz 5.25 5.35 − MHz

fSC1=6.5MHz 5.70 5.80 − MHz

M.3.32 Attenuation at first sound carrierfSC1

4.5 and 5.5MHz 30 36 − dB

6.0 and 6.5MHz 26 32 − dB


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CONFIDENTIAL

SOUND TRAP (CONTINUED)

M.3.33 Attenuation at second soundcarrier fSC2

f=4.726Mhz; fSC1=4.5MHz 21 27 − dB

f=5.742MHz; fSC1=5.5MHz 21 27 − dB

f=6.55Mhz; fSC1=6.0MHz 12 18 − dB

f=6.742MHz; fSC1=6.5MHz 18 24 − dB

M.3.34 amplitude response at the coloursubcarrier frequency

f=3.58 MHz; fSC1=4.5 MHz − 1.0 2.0 dB

f=4.43 MHz; fSC1=5.5 MHz − 1.0 2.0 dB

f=4.43 MHz; fSC1=6.0 MHz − 1.0 2.0 dB

f=4.28 MHz; fSC1=6.5 MHz − 1.0 2.0 dB

IF AND TUNER AGC; NOTE 18

Timing of IF-AGC

M.4.1 modulated video interference 30% AM for 1 mV to 100 mV;0 to 200 Hz (system B/G)

− − 10 %

M.4.2 response time to IF input signalamplitude increase of 52 dB

positive and negativemodulation

− 2 − ms

M.4.3 response to an IF input signalamplitude decrease of 52 dB

negative modulation − 50 − ms

M.4.4 positive modulation − 100 − ms

Tuner take-over adjustment (via I2C-bus)

M.5.1 minimum starting level for tunertake-over (RMS value)

− 0.4 0.8 mV

M.5.2 maximum starting level for tunertake-over (RMS value)

50 150 − mV

Tuner control output

M.6.1 max. tuner AGC output voltage maximum tuner gain; note 5 − − 5 V

M.6.2 output saturation voltage minimum tuner gain; IO=2 mA − − 300 mV

M.6.3 maximum tuner AGC outputswing

1.0 − − mA

M.6.4 leakage current RF AGC − − 1 µA

M.6.5 input signal variation forcomplete tuner control

0.5 2 4 dB

AFC OUTPUT (VIA I2C-BUS); NOTE 19

M.7.1 AFC resolution − 2 − bits

M.7.2 window sensitivity − 125 − kHz

M.7.3 window sensitivity in largewindow mode

− 275 − kHz

VIDEO IDENTIFICATION OUTPUT (VIA IFI BIT IN OUTPUT BYTE 00)

M.8.1 delay time of identification afterthe AGC has stabilized on a newtransmitter

− − 10 ms


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CONFIDENTIAL

DVB IF, note 20

DVB IF AMPLIFIER INPUTS

VS.1.1 input sensitivity (RMS value) fi = 36/44 MHz − 75 150 µV

VS.1.2 input resistance (differential) note 5 − 2 − kΩVS.1.3 input capacitance (differential) note 5 − 3 − pF

VS.1.4 gain control range 64 − − dB

VS.1.5 maximum input signal(RMS value)

150 − − mV

I-MIXER, NOTE 21

VS.2.1 oscillator frequency; note OFDM application − 43.008 − MHz

VS.2.11 VSB application − 49.152 − MHz

VS.2.2 maximum oscillator phase noise −106 − − dB

VS.2.5 lower limit passband − − 1.0 MHz

VS.2.6 upper limit passband 7.0 − − MHz

VS.2.7 passband ripple − − 0.5 dB

VS.2.8 stopband − 29 − MHz

VS.2.9 stopband attenuation 40 − − dB

EXTERNAL AGC CONTROL

VS.3.1 voltage range for full control ofthe amplifier

1 − 3 V

VS.3.2 input impedance 1 − − MΩ

MIXED DOWN OUTPUT SIGNAL

VS.4.1 output voltage (peak-to-peakvalue)

− 1 − V

VS.4.2 output impedance − 25 − ΩVS.4.3 dc output level − 2.0 − V

QSS Sound IF circuit

SOUND IF AMPLIFIER

Q.1.1 input sensitivity (RMS value) −3 dB − 45 tbf dBµV

Q.1.3 maximum input signal tbf 100 − dBµV

Q.1.5 input resistance (differential) note 5 − 2 − kΩQ.1.6 input capacitance (differential) note 5 − 3 − pF

Q.1.7 gain control range − 55 − dB

Q.1.8 crosstalk attenuation betweenSIF and VIF input

50 − − dB


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CONFIDENTIAL

SOUND IF INTERCARRIER OUTPUT; WITH AM = 0

Q.2.1 output signal amplitude (RMSvalue)

SC-1; sound carrier 2 off 75 100 125 mV

Q.2.2 bandwidth (-3 dB) 7.5 10 − MHz

Q.2.3 residual IF sound carrier (RMSvalue)

− 2 − mV

Q.2.4 output resistance − 300 − ΩQ.2.5 DC output voltage − 2.0 − V

Q.2.6 internal bias current of emitterfollower

− 1.0 − mA

Q.2.7 maximum AC and DC sinkcurrent

− 1.0 − mA

Q.2.8 maximum AC and DC sourcecurrent

− 1.0 − mA

Q.2.9 weighted S/N ratio (SC1/SC2).Ratio of PC/SC1 at vision IFinput of 40 dB or higher, note 22

black picture 53/48 58/55 − dB

Q.2.10 white picture 52/47 55/53 − dB

Q.2.11 6 kHz sinewave(black-to-white modulation)

44/42 48/46 − dB

Q.2.12 250 kHz sine wave(black-to-white modulation)

44/25 48/30 − dB

Q.2.13 sound carrier subharmonics(f=2.75 MHz ± 3 kHz)

45/44 51/50 − dB

Q.2.14 sound carrier subharmonics(f=2.87 MHz ± 3 kHz)

46/45 52/51 − dB

AM SOUND OUTPUT; DEPENDING ON SETTING OF CMB0/CMB1 AND AM BITS

Q.3.1 AF output signal amplitude(RMS value)

54% modulation 200 250 300 mV

Q.3.2 total harmonic distortion 54% modulation − 1.0 2.0 %

Q.3.21 total harmonic distortion 80% modulation − 2.0 5.0 %

Q.3.3 AF bandwidth −3 dB 100 125 − kHz

Q.3.4 weighted signal-to-noise ratio 54% modulation, weightedwith CCIR-1k filter, RMS SIFlevel @ 80 dBµV

− 45 − dB

Q.3.5 DC output voltage − 2.5 − V

Q.3.6 power supply ripple rejection − 20 − dB

2nd Sound IF AGC circuit

2ND SOUND IF EXTERNAL INPUT, NOTE 23

Q.4.1 input voltage range 17 − 300 mVRMS

Q.4.2 input frequency range note 24 4.5 − 10.7 MHz

Q.4.3 input resistance note 5 − 25 − kΩQ.4.4 input capacitance note 5 − 3 − pF


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CONFIDENTIAL

2ND SOUND IF AGC

Q.5.1 gain control range − 24 − dB

Q.5.2 charge current AGC pin FM mode − − 12.5 µA

Q.5.3 discharge current AGC pin FM mode − − 50 µA

Q.5.4 charge current AGC pin AM mode − − 2.5 µA

Q.5.5 discharge current AGC pin AM mode − − 2.5 µA

Q.5.6 discharge current AGC pin overload condition − 1 − mA

FM demodulator and audio pre-amplifier

FM-PLL DEMODULATOR

G.1.2 gain control range AGC amplifier 26 30 − dB

G.1.7 AM rejection note 25 40 46 − dB

EXTERNAL SOUND IF INPUT (SSIF, WHEN SELECTED)

G.1.8 input limiting for lock-in of PLL(RMS value)

− 1 2 mV

G.1.9 input resistance note 5 − 50 − kΩG.1.10 input capacitance note 5 − − 1.0 pF

DE-EMPHASIS OUTPUT

G.2.1 output signal amplitude (RMSvalue)

notes 26 and 27 − 125 − mV

G.2.2 output resistance − 15 − kΩG.2.3 DC output voltage − 2.5 − V

G.2.31 signal-to-noise ratio (RMS value) note 28 − 50 − dB

AUDIO INPUT VIA DEEMPHASIS OUTPUT; NOTE 29

G.2.4 input signal amplitude (RMSvalue)

− 125 − mV

G.2.5 input resistance − 15 − kΩG.2.6 voltage gain between input and

output− −3 − dB

Audio Selectors and Volume control

EXTERNAL AUDIO INPUTS; NOTE 30

A.1.1 maximum input voltage (RMSvalue)

5V audio supply − 1.0 1.3 Vrms

A.1.11 8V audio supply − 1.0 1.4 Vrms

A.1.2 input resistance 24 32 − kΩA.1.3 gain from audio inputs to fixed

audio outputs (stereo versions)DSG = 0 − 0 − dB

A.1.31 DSG = 1 − 6 − dB

A.1.4 gain from audio inputs toAUDOUT output at maximumvolume (mono versions)

DSG = 0 − 6 − dB

A.1.41 DSG = 1 − 12 − dB

A.1.5 crosstalk between channels 5 V audio supply − tbf − dB

A.1.6 crosstalk between left and right 5 V audio supply − tbf − dB


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CONFIDENTIAL

FIXED AUDIO OUTPUTS (STEREO AND AV STEREO VERSIONS)

A.2.1 maximum output signalamplitude (RMS value)

5V audio supply 1.0 − − Vrms

A.2.2 8V audio supply 2.0 − − Vrms

A.2.3 output impedance − 500 650 ΩA.2.4 total harmonic distortion at +6 dBV − tbf − dB

A.2.5 at -54 dBV; A-weighted − tbf − dB

A.2.6 signal-to-noise ratio referred to +6dBV outputlevel; A-weighted

− tbf − dB

A.2.7 frequency range 20 − 15.000 Hz

ANALOGUE VOLUME CONTROLLED AUDIO OUTPUT(S)

A.3.1 controlled output signalamplitude (RMS value)

5 V audio supply; note 31 250 350 450 mV

A.3.11 8 V audio supply; note 31 500 700 900 mV

A.3.2 output resistance − 500 − ΩA.3.3 DC output voltage 5 V audio supply − 2.2 − V

A.3.31 8 V audio supply − 3.3 − V

A.3.4 total harmonic distortion note 32 − − 0.5 %

A.3.5 power supply rejection note 11 − 20 − dB

A.3.6 internal signal-to-noise ratio note 11 + 28 + 33 − 50 − dB

A.3.7 external signal-to-noise ratio note 11 + 33 − 60 − dB

A.3.8 control range see also Fig.53 − 70 − dB

A.3.9 suppression of output signalwhen mute is active

− 70 − dB

A.3.10 DC shift output during muting − 10 50 mV

ANALOGUE AUTOMATIC VOLUME LEVELLING; NOTE 34

A.4.1 gain at maximum boost − +6 − dB

A.4.2 gain at minimum boost − -14 − dB

A.4.3 charge (attack) current − 1 − mA

A.4.4 discharge (decay) current − 200 − nA

A.4.5 control voltage at maximumboost

− 1 − V

A.4.6 control voltage at minimum boost − 3 − V


2003 Nov 11 196



CONFIDENTIAL

CVBS, Y/C and RGB/YUV/YP RPB INPUTS

CVBS-Y/C SWITCH

S.1.1 CVBS or Y input voltage(peak-to-peak value)

note 35 − 1.0 1.4 V

S.1.2 CVBS or Y input current − 2 − µA

S.1.3 suppression of non-selectedCVBS input signal

notes 11 and 36 50 − − dB

S.1.4 chrominance input voltage (burstamplitude)

note 5 and 37 − 0.3 1.0 V

S.1.5 chrominance input impedance − 50 − kΩ

CVBS OUTPUT ON CVBSO

S.1.9 output signal amplitude(peak-to-peak value)

− 2.0 − V

S.1.10 top sync level − 0.5 − V

S.1.11 output impedance − − 50 Ω

EXTERNAL RGB / YUV / YPBPR INPUT

S.2.1 RGB input signal amplitude foran output signal of 1.2 V(black-to-white) (peak-to-peakvalue)

note 38 − 0.7 0.8 V

S.2.2 RGB input signal amplitudebefore clipping occurs(peak-to-peak value)

note 11 1.0 − − V

S.2.3 Y input signal amplitude(peak-to-peak value)

input signal amplitude for anoutput signal of 1.2 V(black-to-white); whenactivated via the YUV2-YUV0bits; note 39

− 1.4/1.0 2.0 V

S.2.4 U/PB input signal amplitude(peak-to-peak value)

− −1.33/+0.7

2.0 V

S.2.5 V/PR input signal amplitude(peak-to-peak value)

− −1.05/+0.7

1.5 V

S.2.6 difference between black level ofinternal and external signals atthe outputs

− − 20 mV

S.2.7 input currents no clamping; note 5 − 0.1 1 µA

S.2.8 delay difference for the threechannels

note 11 − 0 20 ns

BASE-BAND TINT CONTROL

S2.9 tint control range 63 steps; see Fig.56 − ±30 − deg


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CONFIDENTIAL

FAST INSERTION

S.3.1 input voltage no insertion − − 0.4 V

S.3.2 insertion 0.9 − − V

S.3.3 maximum input pulse insertion − − 5.0 V

S.3.4 delay time from RGB in toRGB out

insertion; note 11 − − 20 ns

S.3.5 delay difference betweeninsertion to RGB out and RGB into RGB out

insertion; note 11 − − 20 ns

S.3.6 input impedance − 500 − kΩS.3.7 suppression of internal RGB

signalsnotes 11 and 36; insertion;fi = 0 to 5 MHz

− 55 − dB

S.3.8 suppression of external RGBsignals

notes 11 and 36; noinsertion; fi = 0 to 5 MHz

− 55 − dB

YUV INTERFACE (COLOUR DIFFERENCE OUTPUT AND INPUT SIGNALS); NOTE 40

S.4.1 signal amplitude (R−Y)(peak-to-peak value)

INTF = 1, note 5 0.94 1.05 1.16 V

S.4.2 signal amplitude (B−Y)(peak-to-peak value)

INTF = 1, note 5 1.19 1.33 1.47 V

S.4.3 signal amplitude (PR)(peak-to-peak value)

INTF = 0, note 5 0.63 0.7 0.77 V

S.4.4 signal amplitude (PB)(peak-to-peak value)

INTF = 0, note 5 0.63 0.7 0.77 V

S.4.5 output impedance − 500 − Ω

YUV INTERFACE (LUMINANCE OUTPUT AND INPUT SIGNAL); NOTE 40


top sync-white, INTF=0 tbf 1.0 tbf V


top sync-white, INTF=1 tbf 1.4 tbf V

S.5.3 top sync level INTF=0 − 1.5 − V

S.5.4 top sync level INTF=1 − 1.4 − V

S.5.5 output impedance INTF=0 − 250 − ΩS.5.6 output impedance INTF=1 − 250 − Ω


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CONFIDENTIAL

PAL / NTSC Comb Filter

LUMINANCE SIGNAL

F.1.1 luminance gain error −1 0 +1 dB

F.1.2 -3 dB luminance bandwidth COMB mode, fSC = 4.43 MHz 6 − − MHz

F.1.3 COMB mode, fSC = 3.58 MHz 5 − − MHz

F.1.4 YC mode, fSC = 4.43 MHz 6 − − MHz

F.1.5 YC mode, fSC = 3.58 MHz 5 − − MHz

residues of clock frequencies inthe luminance signal (Vrms/1V)

COMB mode

F.1.6 f = 4 x fSC − − −30 dB

F.1.7 f = 2 x fSC − − −30 dB

F.1.8 f = 1.33 x fSC − − −30 dB

F.1.9 f = fSC − − −40 dB

F.1.10 cross talk suppression at verticaltransient black ↔ multi-burst(1V/V (p-p))

see note 41, verticaltransition active video ↔

vertical blanking, see thefigures 68 and 69.

26 − − dB

suppression (comb depth) withrespect to luminance band passnearest to fSC

fSC = 4.43 MHz; see Fig.70

F.1.11 f = fSC 30 − − dB

F.1.12 f = ((283.75-74)/283.75)x fSC − 10 − dB

F.1.13 f = ((283.75+74)/283.75)x fSC − 10 − dB

PAL-M; see Fig.70

F.1.14 f = fSC 30 − − dB

F.1.15 f = ((227.25-59)/227.25)x fSC − 10 − dB

F.1.16 f = ((227.25+59)/227.25)x fSC − 10 − dB

PAL N; see Fig.70

F.1.17 f = fSC 30 − − dB

F.1.18 f = ((229.25-59)/229.25)x fSC − 10 − dB

F.1.19 f = ((229.25+59)/229.25)x fSC − 10 − dB

NTSC M, see Fig.70

F.1.20 f = fSC 30 − − dB

F.1.21 f = ((227.5-59)/227.5) x fSC − 10 − dB

F.1.22 f = ((227.5+59)/227.5) x fSC − 10 − dB

NTSC 4.4 MHz, see Fig.70

F.1.23 f = fSC 30 − − dB

F.1.24 f = ((281.75-74)/281.75) x fSC − 10 − dB

F.1.25 f = ((281.75+74)/281.75) x fSC − 10 − dB

Y DELAY ADJUSTMENT (VALID FOR PAL, NTSC AND SECAM)

F.1.26 tuning range delay time 8 steps; note 42 −150 − +150 ns


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CONFIDENTIAL

CHROMINANCE SIGNAL

F.2.1 chrominance gain error −1 0 +1 dB

F.2.2 -3 dB chrominance bandwidth COMB mode, around fSC, 1.5 − − MHz

F.2.3 chrominance signal-to-noiseratio (0.7V/Vrms noise)

unweighted; fSC±0.3fSC 56 − − dB

residues of clock frequencies inthe chrominance signal(Vrms/0.7V)

COMB mode

F.2.4 f = 4 x fSC − − −30 dB

F.2.5 f = 2 x fSC − − −30 dB

F.2.6 f = 1.33 x fSC − − −40 dB

F.2.7 f = fSC − − −50 dB

F.2.8 cross talk suppression at verticaltransient no-colour ↔ colour(0.7V/V (p-p))

see note 43, verticaltransition active video ↔

vertical blanking, see thefigures 68 and 69

26 − − dB

suppression (comb depth) withrespect to chrominance bandpass at f = fSC

fSC = 4,43 MHz; see Fig.71

F.2.9 f = (284/283.75) x fSC 30 − − dB

F.2.10 f = ((284-74)/283.75) x fSC 30 − − dB

F.2.11 f = ((284+74)/283.75) x fSC 30 − − dB

PAL M, see Fig.71

F.2.12 f = (227/227.25) x fSC 30 − − dB

F.2.13 f = ((227-59)/227.25) x fSC 30 − − dB

F.2.14 f = ((227+59)/227.25) x fSC 30 − − dB

PAL N, see Fig.71

F.2.15 f = (229/229.25) x fSC 30 − − dB

F.2.16 f = ((229-59)/229.25) x fSC 30 − − dB

F.2.17 f = ((229+59)/229.25) x fSC 30 − − dB

NTSC M, see Fig.71

F.2.18 f = (227/227.5) x fSC 30 − − dB

F.2.19 f = ((227-59)/227.5) x fSC 30 − − dB

F.2.20 f = ((227+59)/227.5) x fSC 30 − − dB

NTSC 4.4 MHz, see Fig.71

F.2.21 f = (282/281.75) x fSC 30 − − dB

F.2.22 f = ((282-74)/281.75) x fSC 30 − − dB

F.2.23 f = ((282+74)/281.75) x fSC 30 − − dB


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CONFIDENTIAL

Chrominance and Luminance filters

CHROMINANCE TRAP CIRCUIT; NOTE 44

F.3.1 trap frequency − fsc − MHz

F.3.2 Bandwidth at fSC = 3.58 MHz −3 dB − 2.7 − MHz

F.3.3 Bandwidth at fSC = 4.43 MHz −3 dB − 3.3 − MHz

F.3.4 colour subcarrier rejection 24 26 − dB

F.3.5 trap frequency during SECAMreception

− 4.3 − MHz

CHROMINANCE BANDPASS CIRCUIT

F.4.1 centre frequency (CB = 0) − fsc − MHz

F.4.2 centre frequency (CB = 1) − 1.1×fsc − MHz

F.4.3 bandpass quality factor − 3 −

CLOCHE FILTER

F.5.1 centre frequency CLO = 0 4.26 4.29 4.31 MHz

F.5.2 Bandwidth 241 268 295 kHz

Picture Improvement Features

PEAKING CONTROL; NOTE 45

P.1.1 width of preshoot or overshoot setting PF1/PF0 = 0/0 − 190 − ns

setting PF1/PF0 = 0/1 − 160 − ns



P.1.2 peaking signal compressionthreshold

− 50 − IRE

P.1.3 overshoot at maximum peaking positive, direction “white” − 45 − %

P.1.4 negative − 75 − %

P.1.5 Ratio negative/positiveovershoot; note 46

− 1.7 −

P.1.6 peaking control curve 63 steps see Fig.54

P.1.7 peaking centre frequency setting PF1/PF0 = 0/0 − 2.7 − MHz

P.1.8 setting PF1/PF0 = 0/1 − 3.1 − MHz



CORING STAGE; NOTE 47

P.1.10 coring range − 10 − IRE


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CONFIDENTIAL

BLACK LEVEL STRETCHER; NOTE 48

P.2.1 Maximum black level shift BSD = 0 25 30 35 IRE

P.2.11 Maximum black level shift BSD = 1 10 15 20 IRE

P.2.2 level shift at 100% peak white −1 0 1 IRE

P.2.3 level shift at 50% peak white −1 − 3 IRE

P.2.4 level shift at 15% peak white BSD = 0 10 12 14 IRE

P.2.5 level shift at 15% peak white BSD = 1 4 6 8 IRE

DYNAMIC SKIN TONE (FLESH) CONTROL; NOTE 49

P.4.1 control angle − 123 − deg

P.4.32 correction range (angle) − 45 − deg

GAMMA CONTROL; NOTE 50

P.6.1 break point of characteristic maximum white is 100% 40 50 60 %

P.6.2 maximum expansion set by the bits WS1/WS0 6 8 12 %

P.6.3 mismatch for YIN = 100 IRE at maximum expansion −2 − +8 IRE

P.6.4 mismatch for YIN = 0 IRE at maximum expansion −2 − +4 IRE

BLUE STRETCH; NOTE 51

P.7.1 increase of small signal gain forthe blue channel

BLS = 1 − 20 − %

P.7.2 decrease of small signal gain forthe red channel

BLS = 1 − 20 − %

DC TRANSFER RATIO OF LUMINANCE SIGNAL; NOTE 52

P.8.1 reduction of black level for whitepicture (100 IRE)

TFR = 1 − 10 − IRE

SCAN VELOCITY MODULATION OUTPUT; NOTES 53 AND 54

P.9.1 output signal amplitude(peak-to-peak value

VMA1/VMA0 = 1/1

SMD1/SMD0 = 0/1

− 1.5 − V

P.9.11 output signal amplitude(peak-to-peak value

VMA1/VMA0 = 1/1

SMD1/SMD0 = 1/0

− 1.8 − V

P.9.2 delay of RGB output signal withrespect to SVM output

SVM2-SVM0 = 000,PF1-PF0= 01 (peaking frequency of3.1 MHz) and 50% inputsignal amplitude

− 170 − ns

P.9.3 coring range CRA0 = 0 − 8 − %

P.9.4 maximum DC-current throughthe SVM output

VMA1/VMA0 = 0/0 − 100 − µA


2003 Nov 11 202



CONFIDENTIAL

Horizontal and vertical synchronization and drive circuits

SYNC VIDEO INPUT

H.1.1 sync pulse amplitude note 5 50 300 350 mV

H.1.2 slicing level for horizontal sync note 55 − 45 − %

H.1.3 slicing level for vertical sync note 55 − 35 − %

HORIZONTAL OSCILLATOR

H.2.1 free running frequency − 15625 − Hz

H.2.2 spread free running frequency − − ±2 %

H.2.3 frequency variation with respectto the supply voltage

VP = 8.0 V ±10%; note 11 − 0.2 0.5 %

H.2.4 frequency variation withtemperature

Tamb = 0 to 70 °C; note 11 − − 80 Hz

FIRST CONTROL LOOP; NOTE 56

H.3.1 holding range PLL − ±0.8 ±1.1 kHz

H.3.2 catching range PLL note 11 ±0.5 ±0.8 − kHz

H.3.3 S/N ratio video input signal toswitch the time constant

− 24 − dB

H.3.4 hysteresis at the switching point − 3 − dB

SECOND CONTROL LOOP

H.4.1 control sensitivity − 150 − µs/µs

H.4.2 control range from start ofhorizontal output to flyback atnominal shift position

− 19 − µs

H.4.3 horizontal shift range 63 steps ±2 − − µs

H.4.4 control sensitivity for dynamiccompensation

− 13 − µs/V

H.4.5 Voltage to switch-on the ‘flash’protection

note 57 4.0 − − V

H.4.6 Input current during protection − − 1 mA

H.4.7 control range parallelogramcorrection

note 58 − ±0.75 − µs

H.4.8 control range bow correction note 58 − ±1.0 − µs

HORIZONTAL OUTPUT; NOTE 59

H.5.1 LOW level output voltage IO = 10 mA − − 0.3 V

H.5.2 maximum allowed output current 10 − − mA

H.5.3 maximum allowed output voltage − − VP V

H.5.4 duty factor VOUT = LOW (TON); SDC = 0 − 55 − %

H.5.41 duty factor VOUT = LOW (TON); SDC = 1 − 60 − %

H.5.5 switch-on time horizontal drivepulse

− 1175 − ms

H.5.6 switch-off time horizontal drivepulse

− 43 − ms


2003 Nov 11 203



CONFIDENTIAL

FLYBACK PULSE INPUT AND SANDCASTLE OUTPUT

H.6.1 required input current duringflyback pulse

note 5 100 − 300 µA

H.6.2 output voltage during burst key 4.5 5.0 5.5 V

during blanking 2.8 3.0 3.2 V

H.6.3 clamped input voltage duringflyback

1.7 2.0 2.3 V

H.6.4 pulse width burst key pulse 3.3 3.5 3.7 µs

H.6.5 vertical blanking, note 60 − 14/9.5 − lines

H.6.6 delay of start of burst key to startof sync

4.8 5.0 5.2 µs

H.6.7 output voltage of H/V timingsignal

CSY = 1 − tbf − V

VERTICAL OSCILLATOR; NOTE 61

H.7.1 free running frequency − 50/60 − Hz

H.7.2 locking range 45 − 64.5/72 Hz

H.7.3 divider value not locked − 625/525 − lines

H.7.4 locking range 434/488 − 722 lines/frame

VERTICAL RAMP GENERATOR

H.8.1 sawtooth amplitude(peak-to-peak value)

VS = 1FH;C = 150 nF; R = 39 kΩ

− 1.8 − V

H.8.2 discharge current − 1 − mA

H.8.3 charge current set by externalresistor

note 62 − 14 − µA

H.8.4 vertical slope 63 steps; see Fig. 88 −20 − +20 %

H.8.5 charge current increase f = 60 Hz − 19 − %

H.8.6 LOW level of ramp − 1.5 − V

VERTICAL DRIVE OUTPUTS

H.9.1 differential output current(peak-to-peak value)

VA = 1FH − 1.0 − mA

H.9.2 common mode current − 400 − µA

H.9.3 output voltage range 0 − 2.5 V

EHT TRACKING/OVERVOLTAGE PROTECTION

H.10.1 input voltage 1.2 − 2.8 V

H.10.2 scan modulation range −5 − +5 %

H.10.3 vertical sensitivity − 6.3 − %/V

H.10.4 EW sensitivity when switched-on − −6.3 − %/V

H.10.5 EW equivalent output current +120 − −120 µA

H.10.6 overvoltage detection level note 57 − 3.9 − V


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CONFIDENTIAL

DE-INTERLACE

H.11.1 first field delay − 0.5H −

EW WIDTH; NOTE 63

H.12.1 control range 63 steps; see Fig. 91 100 − 65 %

H.12.2 equivalent output current 0 − 700 µA

H.12.3 EW output voltage range 1.0 − 5.0 V

H.12.4 EW output current range 0 − 1200 µA

EW PARABOLA/WIDTH


H.13.2 equivalent output current EW=3FH; CP=11H; TC=1FH 0 − 460 µA

EW UPPER/LOWER CORNER/PARABOLA

H.14.1 control range 63 steps; see Fig. 93 −55 − +55 %

H.14.2 equivalent output current PW=3FH; EW=3FH; TC=1FH −262 − +262 µA

EW TRAPEZIUM


H.15.2 equivalent output current EW=1FH; CP=11H; PW=1FH −100 − +100 µA

VERTICAL AMPLITUDE


H.16.2 equivalent differential verticaldrive output current(peak-to-peak value)

SC = 0EH 800 − 1200 µA

VERTICAL SHIFT


H.17.2 equivalent differential verticaldrive output current(peak-to-peak value)

−50 − +50 µA

S-CORRECTION

H.18.1 control range 63 steps; see Fig. 90 −10 − 25 %

VERTICAL LINEARITY

H.18.2 control range, ratio bottom/top ofscreen (full screen linearitysetting)

63 steps; see Fig. 95;VSH=1FH; SC=0;VL1/VL0=0/0

85 − 117 %

VERTICAL ZOOM MODE (OUTPUT CURRENT VARIATION WITH RESPECT TO NOMINAL SCAN); NOTE 64

H.19.1 vertical expand factor 0.75 − 1.38

H.19.2 output current limiting and RGBblanking

− 1.05 −

VERTICAL SCROLL

H.20.1 Control range (percentage ofnominal visible pictureamplitude)

vertical zoom setting at 3FH −18 − 19 %


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Colour demodulation part

CHROMINANCE AMPLIFIER

D.1.1 ACC control range note 65 26 − − dB

D.1.2 change in amplitude of theoutput signals over the ACCrange

− − 2 dB

D.1.3 threshold colour killer ON CHSE1/CHSE0 = 0/0 −30 − − dB

D.1.4 hysteresis colour killer OFF strong signal conditions;S/N ≥ 40 dB; note 11

− +3 − dB

D.1.5 noisy input signals; note 11 − +1 − dB

ACL CIRCUIT; NOTE 66

D.2.1 chrominance burst ratio at whichthe ACL starts to operate

− 3.0 −

REFERENCE PART

Phase-locked loop

D.3.1 catching range all standards ±500 − − Hz

D.3.2 phase shift for a ±400 Hzdeviation of the oscillatorfrequency

note 11 − − 2 deg

HUE CONTROL

D.5.1 hue control range 63 steps; see Fig.55 ±35 ±40 − deg

D.5.2 hue variation for ±10% VP note 11 − 0 − deg

D.5.3 hue variation with temperature Tamb = 0 to 70 °C; note 11 − 0 − deg

DEMODULATORS

General

D.6.3 spread of signal amplitude ratiobetween standards

note 11 −1 − +1 dB

D.6.5 bandwidth of demodulators −3 dB; note 67 − 650 − kHz

PAL/NTSC demodulator

D.6.6 gain between both demodulatorsG(B−Y) and G(R−Y)

INTF = 0 1.26 1.41 1.58

D.6.12 change of output signalamplitude with temperature

note 11 − 0.1 − %/K

D.6.13 change of output signalamplitude with supply voltage

note 11 − − ±0.1 dB

D.6.14 phase error in the demodulatedsignals

note 11 − − ±5 deg


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SECAM demodulator

D.7.1 black level off-set SBO1/SBO0 = 1/0 − − 7 kHz

D.7.2 pole frequency of deemphasis 77 85 93 kHz

D.7.3 ratio pole and zero frequency − 3 −D.7.4 non linearity − − 3 %

D.7.5 calibration voltage 1.8 2.3 2.8 V

Base-band delay line

D.8.1 variation of output signal foradjacent time samples atconstant input signals

−0.1 − 0.1 dB

D.8.2 residual clock signal(peak-to-peak value)

− − 5 mV

D.8.3 delay of delayed signal 63.94 64.0 64.06 µs

D.8.4 delay of non-delayed signal 40 60 80 ns

D.8.5 difference in output amplitudewith delay on or off

− − 5 %

COLOUR DIFFERENCE MATRICES (IN CONTROL CIRCUIT)

PAL/SECAM mode; (R−Y) and (B−Y) not affected

D.9.1 ratio of demodulated signals(G−Y)/(R−Y)

− −0.51±10%

−

D.9.2 ratio of demodulated signals(G−Y)/(B−Y)

− −0.19±25%

−

NTSC mode; the matrix results in the following signals (nominal hue setting)

MUS-bit = 0

D.9.6 (B−Y) signal: 2.03/0° 2.03UR

D.9.7 (R−Y) signal: 1.59/95° −0.14UR + 1.58VR

D.9.8 (G−Y) signal: 0.61/240° −0.31UR − 0.53VR

MUS-bit = 1

D.9.9 (B−Y) signal: 2.03/0° 2.03UR

D.9.10 (R−Y) signal: 1.59/102° −0.24UR + 1.55VR

D.9.11 (G−Y) signal: 0.61/236° −0.31UR − 0.51VR

REFERENCE SIGNAL OUTPUT/SWITCH OUTPUT; NOTE 68

D.10.1 reference frequency CMB1/CMB0 = 01 3.58/4.43 MHz

D.10.2 output signal amplitude(peak-to-peak value)

CMB1/CMB0 = 01 0.2 0.25 0.3 V

D.10.3 output level (mid position) CMB1/CMB0 = 01 1.9 2.1 2.3 V

D.10.4 SWO output level LOW CMB1/CMB0 = 10 − − 0.8 V

D.10.5 SWO output level HIGH CMB1/CMB0 = 11 4.5 − − V


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Control part

SATURATION CONTROL; NOTE 38

C.1.1 saturation control range 63 steps; see Fig.57 52 − − dB

CONTRAST CONTROL; NOTE 38

C.2.1 contrast control range 63 steps; see Fig.58 − 20 − dB

C.2.2 tracking between the threechannels over a control range of10 dB

− − 0.5 dB

C.2.6 contrast reduction − 10 − dB

BRIGHTNESS CONTROL

C.3.1 brightness control range 63 steps; see Fig.59 − ±0.4 − V

RGB AMPLIFIERS

C.4.1 output signal amplitude(peak-to-peak value)

at nominal luminance inputsignal, nominal settings forcontrast, white-pointadjustment and cathode drivelevel(CL3-CL0 = 7H)

− 1.2 − V

C.4.101 output signal control range dueto the CCC gain loop

0.5 − 2.5 V

C.4.2 maximum signal amplitude(black-to-white)

note 69 − 3.0 − V

C.4.3 maximum peak white level − 4.0 − V

C.4.4 output signal amplitude for the‘red’ channel (peak-to-peakvalue)

at nominal settings forcontrast and saturationcontrol and no luminancesignal to the input (R−Y, PAL)

− 1.26 − V

C.4.41 output impedance − 300 − ΩC.4.5 nominal black level voltage − 1.65 − V

C.4.6 black level voltage when black level stabilisationis switched-off (via AKB bit)

− 1.65 − V

C.4.61 black level voltage control range AVG bit active; note 70 1.0 1.65 2.3 V

C.4.71 timing of wide blanking withrespect to mid sync (HBL = 1);note 71

start of blanking; WBI = 0 3.5 − 5.9 µs

C.4.72 end of blanking; WBI = 0 7.8 − 10.2 µs

C.4.73 start of blanking; WBI = 1 9.7 − 12.1 µs

C.4.74 end of blanking; WBI = 1 14.0 − 16.4 µs

C.4.8 control range of the black-currentstabilisation

− ±0.65 − V

C.4.81 RGB output level when RGBL=1 − 0.8 − V


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C.4.9 blanking level difference with black level,note 69

− −0.3 − V

C.4.91 blanking level when RBL = 1 − −1.1 − V

C.4.10 level during leakage test − −0.07 − V

C.4.11 level ‘low’ measuring pulse − 0.15 − V

C.4.12 level ‘high’ measuring pulse(current setting 220 µA); note 72

− 0.6 − V

C.4.13 adjustment range of the cathodedrive level

note 69 − ±3 − dB

C.4.14 variation of black level withtemperature

note 11 − − 1.0 mV/K

C.4.141 black level off-set adjustment onthe Red and Green channel

63 steps − ±100 − mV

C.4.21 signal-to-noise ratio of the outputsignals

RGB input; note 73 60 − − dB

C.4.22 CVBS input; note 73 50 − − dB

C.4.23 residual voltage at the RGBoutputs (peak-to-peak value)

at fosc − − 15 mV

C.4.24 at 2fosc plus higher harmonics − − 15 mV

C.4.25 bandwidth of output signals RGB input; at −3 dB − 7 − MHz

C.4.26 CVBS input; at −3 dB;fosc = 3.58 MHz

− 2.8 − MHz

C.4.27 CVBS input; at −3 dB;fosc = 4.43 MHz

− 3.4 − MHz

C.4.28 S-VHS input; at −3 dB 5 − − MHz

WHITE-POINT ADJUSTMENT

C.5.1 I2C-bus setting for nominal gain HEX code − 20H −C.5.2 adjustment range of the relative

R, G and B drive levels− ±3 − dB

2-POINT BLACK-CURRENT STABILIZATION, NOTES 74

C.6.1 amplitude of ‘low’ referencecurrent

− 10 − µA

C.6.2 amplitude of ‘high’ referencecurrent; note 72

SLG0/SLG1 = 0/0 − 220 − µA

C.6.3 acceptable leakage current − ±75 − µA

C.6.4 input impedance during scan − 500 − kΩ

BEAM CURRENT LIMITING

C.7.1 contrast reduction startingvoltage

− 2.8 − V

C.7.2 voltage difference for full contrastreduction

− 1.8 − V

C.7.3 brightness reduction startingvoltage

CBS = 0 − 1.7 − V


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Notes

1. When the 3.3 V supply is present and the µ-Controller is active a ‘low-power start-up’ mode can be activated. Whenall subaddress bytes have been sent and the POR and XPR flags have been cleared the horizontal output can beswitched-on via the STB-bit (subaddress 3DH). In this condition the horizontal drive signal has the nominal TOFF andthe TON grows gradually from zero to the nominal value. As soon as the 5 V supply is present the switch-on procedure(e.g. closing of the second loop) is continued.

2. The various parameters in this specification are guaranteed for a supply voltage range between 4.75 V and 5.5 V.For supply voltages between 4.5 V and 4.75 v some output signals may be distorted or clipped, however, theoperation of the circuit is not affected at these supply voltages.

3. The supply voltage of the analogue audio part may have a value between 5V and 8V. For a supply voltage of 5V themaximum amplitude of the output signals is 1Vrms. For a supply voltage of 8V the maximum amplitude of the outputsignals is 2Vrms.

4. On set AGC.

5. This parameter is not tested during production and is just given as application information for the designer of thetelevision receiver.

C.7.31 brightness reduction startingvoltage

CBS = 1 − 2.4 − V

C.7.4 voltage difference for fullbrightness reduction

− 0.9 − V

C.7.5 internal bias voltage − 3.3 − V

C.7.8 maximum allowable current − 1 − mA

FIXED BEAM CURRENT SWITCH-OFF; NOTE 75

C.8.1 discharge current duringswitch-off

0.85 1.0 1.15 mA

C.8.2 discharge time of picture tube − 38 − ms

PEAK WHITE LIMITER AND SOFT CLIPPING; NOTES 76 AND 77

C.9.1 CVBS signal amplitude at whichpeak white limiter is activated(black-to-white value)

PWL range (15 steps); atmax. contrast

0.40 − 0.60 V

C.9.2 soft clipper gain reduction maximum contrast; note 77,see Fig.84

− 8 − dB

General purpose switch output SWO1 (controlled by SWO1 bit)

O.1.1 output voltage HIGH 3.5 5.0 5.5 V

O.1.2 output voltage LOW − 0.2 0.4 V

O.1.3 sink current 2 − − mA

O.1.4 source current 2 − − mA

Vertical guard input and LED drive output; note 78

I/O.1.1 output voltage HIGH vertical guard activated − 3.3 − V

I/O.1.2 output voltage HIGH vertical guard not activated − − 5.5 V

I/O.1.3 output voltage LOW − 0.2 0.4 V

I/O.1.4 sink current 2 − − mA

I/O.1.5 detection level for vertical guardand input port

tbf 3.6 tbf V


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6. Loop bandwidth BL = 60 kHz (natural frequency fN = 15 kHz; damping factor d = 2; calculated with top sync level asFPLL input signal level).

7. The IF-PLL demodulator uses an internal VCO (no external LC-circuit required) which is calibrated by means of adigital control circuit which uses the clock frequency of the µ-Controller as a reference. The required IF frequency forthe various standards is set via the IFA-IFC bits in subaddress 2FH. When the system is locked the resulting IFfrequency is very accurate with a deviation from the nominal value of less than 25 kHz.

8. Measured at 10 mV (RMS) top sync input signal.

9. So called projected zero point, i.e. with switched demodulator.

10. Measured in accordance with the test line given in Fig.60. For the differential phase test the peak white setting isreduced to 87%.

The differential gain is expressed as a percentage of the difference in peak amplitudes between the largest andsmallest value relative to the subcarrier amplitude at blanking level.

The phase difference is defined as the difference in degrees between the largest and smallest phase angle.

11. This parameter is not tested during production but is guaranteed by the design and qualified by means of matrixbatches which are made in the pilot production period.

12. This figure is valid for the complete video signal amplitude (peak white-to-black), see Fig.61.

13. The noise inverter is only active in the ‘strong signal mode’ (no noise detected in the incoming signal)

14. The test set-up and input conditions are given in Fig.62. The figures are measured with an input signal of10 mV RMS. This test can only be carried out in a test set-up in which the test options of the IC can be activated.This because the IF-AGC control input is not available in this IC.

15. Measured at an input signal of 10 mVRMS. The S/N is the ratio of black-to-white amplitude to the black level noisevoltage (RMS value). B = 5 MHz. Weighted in accordance with CCIR 567.

16. Via this pin both the demodulated IF signal and the selected CVBS (or Y+C) signal can be supplied to the output.The pin can also be used as CVBS input. The selection between both signals is realised by means of the SVO bitsin subaddress 39H.

17. The cascade of sound trap and group delay correction filter compensates for the group delay pre-distortion of the BGstandard, curve A (see “Rec. ITU-R BT.470-4”). The indicated values are the difference between the group delay at4.43 MHz and the group delay at 10 kHz.

18. The time-constant of the IF-AGC is internal and the speed of the AGC can be set via the bits AGC1 and AGC0 insubaddress 30H. The AGC response time is also dependent on the acquisition time of the PLL demodulator. Thevalues given are valid for the ‘norm’ setting (AGC1-AGC0 = 0-1) and when the PLL is in lock.

19. The AFC control voltage is generated by the digital tuning system of the PLL demodulator. This system uses theclock frequency of the TCG µ-Controller as a reference and is therefore very accurate. For this reason no maximumand minimum values are given for the window sensitivity figures (parameters M.7.2 and M.7.3). The tuninginformation is supplied to the tuning system via the AFC bits in output byte 04H. The AFC value is valid only whenthe LOCK-bit is 1.

20. The QSS IF circuit can also be used for the preprocessing of digital TV signals. The modulated signal has to besupplied to the sound IF input (via a suitable filter) and the mixed down I-signal is available at the DVB outputs.

The AGC has two modes of operation: the internal mode in which the IC sets the gain with its own reference and anexternal mode in which the gain can be controlled with an external circuit. In the second case the QSS-IF AGC pinis used as an input to control the IF gain with an external circuit.

21. The reference signal for the I-mixer (frequency 43.008 or 49.152 MHz) is internally generated. It is also possible tosupply an external reference signal to the mixer. This external mode is activated by means of the CMB2-CMB0 andIFD bits. The signal has to be supplied to the pin which is normally used as the reference signal output of the colourdecoder (REFO).

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22. The weighted S/N ratio is measured under the following conditions:

a) The vision IF modulator must meet the following specifications:

Incidental phase modulation for black-to-white jumps less than 0.5 degrees.

QSS AF performance, measured with the television-demodulator AMF2 (audio output, weighted S/N ratio) betterthan 60 dB (deviation 27 kHz) for 6 kHz sine wave black-to-white modulation.

Picture-to-sound carrier ratio: PC/SC1 = 13 dB (transmitter).

b) The measurements must be carried out with the Siemens SAW filters G3962 for vision IF and G9350 for soundIF. Input level for sound IF 10 mVRMS with 27 kHz deviation.

c) The PC/SC ratio at the vision IF input is calculated as the addition of the TV transmitter ratio and the SAW filterPC/SC ratio. This PC/SC ratio is necessary to achieve the S/N(W) values as indicated.

23. The input should be shunted with a resistor of 470 Ω - 10 kΩ24. If a 10.7MHz FM radio IF signal is supplied to the external 2nd SIF input, an external 10.7MHz bandpass filter must

be used.

25. f = 4.5/5.5 MHz; FM: 70 Hz, ± 50 kHz deviation; AM: 1.0 kHz, 30% modulation.

26. f = 5.5 MHz; modulation frequency: 1 kHz, ∆f = ± 27 kHz.

27. Depending on the application (FM or AM reception) the amplitude of the output signal can be increased with 6 dB bythe AGN bit in subaddress 33H (FM reception) or AMLOW bit in subaddress 35H (AM reception). The resulting outputsignal amplitudes are given in Table 268.

28. The signal-to-noise ratio is measured under the following conditions:

a) Input signal to the SSIF pin (activated via the CMB2-CMB0 bits) with an amplitude of 100mVRMS, fMOD = 1 kHzand ∆f = 27 kHz

b) Output signal measured at the AUDEEM pin. The noise (RMS value) is measured according to the CCIR 468definition.

29. In the “Mono” versions the deemphasis pin can also be used as additional audio input. In that case the internal(demodulated FM signal) must be switched off. This can be realised by means of the SM (sound mute) bit. When thevision IF amplifier is switched to positive modulation the signal from the FM demodulator is automatically switchedoff. The external signal must be switched off when the internal signal is selected.

30. The “Stereo” and “AV Stereo” versions have 4 stereo inputs. The maximum output signal amplitude of the selector(1.0 VRMS or 2.0 VRMS) is dependent on the supply voltage (5 V or 8 V) of the audio selector supply pin (VCC8V).

31. Audio attenuator at −6 dB, input signal 500 mVRMS

32. Audio input signal 200 mVRMS. Measured with a bandwidth of 15 kHz and the audio attenuator at −6 dB.

33. Unweighted RMS value, audio input signal 500 mVRMS, audio attenuator at −6 dB.

34. In versions without stereo decoder and digital sound processing circuits an analogue Automatic Volume Levelling(AVL) function can be activated. The pin to which the external capacitor has to be connected can be chosen bymeans of the AVLE bit (subaddress 34H). When the East-West output is not used (90° picture tubes) the capacitorcan be connected to the EW output pin. In 110° applications a choice has to be made between the AVL function anda sub-carrier output / general purpose switch output. The selection must be made by means of the CMB0 to CMB2bit in subaddress 4AH. More details about the sub-carrier output are given in the parameters D.10.

The Automatic Volume Levelling (AVL) circuit stabilises automatically the audio output signal to a certain level whichcan be set by means of the volume control. This AVL function prevents big audio output fluctuations due to variationof the modulation depth of the transmitter. The AVL can be switched on and off via the AVL bit in subaddress 34H.

The AVL is active over an input voltage range (measured at the deemphasis output) of 50 to 1500 mVRMS. The AVLcontrol curve is given in Fig.65. The control range of +6 dB to −14 dB is valid for input signals with 50% of themaximum frequency deviation.

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35. Signal with negative-going sync. Amplitude includes sync pulse amplitude.

36. This parameter is measured at nominal settings of the various controls.

37. Indicated is a signal for a colour bar with 75% saturation (chroma : burst ratio = 2.2 : 1).

38. The contrast and saturation control is active on the internal signal (YUV) and on the external RGB/YUV/YPRPB input.The Text/OSD input can be controlled on brightness only. Nominal contrast is specified with the DAC in position 20HEX. Nominal saturation as maximum −10 dB.

39. The YUV/YPBPR input signal amplitudes are based on a colour bar signal with 75/100% saturation.

40. Depending on the setting of the INTF bit (subaddress 42H) the saturation of the output signal is 75% (YUV signal)or 100% (YPRPB signal). The luminance and colour difference out- and inputs can directly be connected. Whenadditional picture improvement ICs (like the TDA 9178) are applied the inputs of these ICs must be ac coupledbecause of the black level clamp requirement. The output signal of the picture improvement IC can directly becoupled to the luminance and colour difference inputs as long as the dc level of these signals have a value between1 and 4 V (for the luminance signal) or between 1 and 4 V (for the UV signals). When the dc level of the input signalsexceed these levels the signals must be ac coupled and biased to a voltage level within these limits.

41. Test signal:For PAL B, G, H, D, I and N: CCIR-18 multi-burst (see Fig. 66).For PAL M and NTSC M: 100% amplitude FCC multi-burst (see Fig. 67).

42. This control range is valid for a colour carrier frequency of 4.43 MHz. For a colour carrier frequency of 3.58 MHz thecontrol range has a value of ± 190 µs (see also Table 132).

43. Test signal:For PAL B, G, H, D, I and N: 100/0/75/0 EBU colour bar.For PAL M and NTSC M: 100% white 75% amplitude FCC colour bar.

44. When the decoder is forced to a fixed subcarrier frequency (via the CM-bits) the chroma trap is always switched-on,also when no colour signal is identified. In the automatic mode the chroma trap is switched-off when no colour signalis identified.

45. Valid for a signal amplitude on the Y-input of 0.7 V black-to-white (100 IRE) with a rise time (10% to 90%) of 70 nsand the video switch in the Y/C mode. During production the peaking function is not tested by measuring theovershoots but by measuring the frequency response of the Y output.

46. The ratio between the positive and negative peaks can be varied by means of the bits RPO1 and RPO0 insubaddress 47H. For ratios which are smaller than 1.7 the positive peak is not affected and the negative peak isreduced.

47. The coring can be activated in the low-light part of the picture. This effectively reduces the noise while havingmaximum peaking in the bright parts of the picture. The setting the video content at which the coring is active can beadapted by means of the COR1/COR0 bits in subaddress 47H.

48. For video signals with a black level which deviates from the back-porch blanking level the signal is “stretched” to theblanking level. The amount of correction depends on the IRE value of the signal (see Fig.72). The black level isdetected by means of an internal capacitor. The black level stretcher can be switched on and off via the BKS bit insubaddress 45H. The values given in the specification are valid only when the luminance input signal has anamplitude of 1 Vp-p.

49. The Dynamic Skin Tone Correction circuit is designed such that it corrects (instantaneously and locally) the hue ofthose colours which are located in the area in the UV plane that matches to skin tones. The correction is dependenton the luminance, saturation and distance to the preferred axis. Because the amount of correction is dependent onthe parameters of the incoming YUV signal it is not possible to give exact figures for the correction angle. Thecorrection angle of 45 (±22.5) degrees is just given as an indication and is valid for an input signal with a luminancesignal amplitude of 75% and a colour saturation of 50%. A graphical representation of the control behaviour is givenin Figure 73 on page 229.

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50. The gamma control is realised by inserting a non-linear transfer characteristic in the luminance path. The shape ofthe curve can be adapted by means of the WS1/WS0 bits in subaddress 45H. The control curves are given in Fig. 74.It is possible to make the gamma control dependent on the Average Picture Level (APL). This function is identical tothe previous white stretch function. Then the GAM bit (subaddress 44H) must be set to “0”. The control curve canagain be adapted by means of the WS1/WS0 bits (see also Fig. 75). When the gamma control is active the coloursaturation is adapted to the variation of the luminance linearity.

51. Via the ‘blue stretch’ (BLS bit) function the colour temperature of the bright scenes (amplitudes which exceed a valueof 80% of the nominal amplitude) can be increased. This effect is obtained by increasing the small signal gain of theblue channel and decreasing the small signal gain for the red channel for signals which exceed the 80% level. Theeffect is illustrated in Figure 76 on page 230.

52. When this function is activated (TFR = 1) the black level of the RGB output signals is dependent on the averagepicture information. For a ‘black’ picture the black level is unaffected and the maximum black level shift for a complete‘white’ picture (100 IRE) is 10 IRE in the direction ‘black’. The black level shift is linearly dependent on the picturecontent.

53. The SVM is specified for a 2T-pulse input signal with an amplitude (100%) of 700 mVP-P. The coring system on theSVM output signal has to levels. The SVM output signal amplitude is dependent on the setting of the coring and onSVMA (see Fig. 77).

54. The delay between the RGB output signals and the SVM output signal can be adjusted (by means of theSVM2-SVM0 bits in subaddress 48H) so that an optimum picture performance can be obtained. Furthermore a videodependent coring function can be activated. Another feature is that the SVM output signal can be made dependenton the horizontal position on the screen (parabola on the SVM output). The screen is equally divided into 6 parts (seeFig. 78). By multiplying a gain factor with the SVM output signal as a function of the horizontal position severaldiscrete curves can be made. The shape of the curve can be programmed by means of the SPR2-SPR0 bits (insubaddress 48H).

55. The slicing level is independent of sync pulse amplitude. The given percentage is the distance between the slicinglevel and the top sync level. When the amplitude of the sync pulse exceeds the value of 350 mV the sync separatorwill slice the sync pulse at a level of 175 mV above top sync. The maximum sync pulse amplitude is 0.4 Vp-p. Bymeans of the SSL bit (subaddress 3FH) the slicing level can be changed to 30% (SSL = 1).

The vertical slicing level is dependent on the S/N ratio of the incoming video signal. For a S/N ≤ 24 dB the slicinglevel is 35%, for a S/N ≥ 24 dB the slicing level is 60%. With the bit FSL (Forced Slicing Level) the vertical slicinglevel can be forced to 60%.

56. To obtain a good performance for both weak signal and VCR playback the time constant of the first control loop isswitched depending on the input signal condition and the condition of the POC, FOA, FOB and VID bits insubaddress 3DH. The circuit contains a noise detector and the time constant is switched to ‘slow’ when too muchnoise is present in the signal. In the ‘fast’ mode during the vertical retrace time the phase detector current is increased50% so that phase errors due to head-switching of the VCR are corrected as soon as possible. Switching of the timeconstant can be automatically or can be set by means of the control bits.

The circuit contains a video identification circuit which is independent of the first loop. This identification circuit canbe used to close or open the first control loop when a video signal is present or not present on the input. This enablesa stable On Screen Display (OSD) when just noise is present at the input.

To prevent that the horizontal synchronisation is disturbed by anti copy signals like Macrovision the phase detectoris gated during the vertical retrace period so that pulses during scan have no effect on the output voltage. The widthof the gate pulse is about 22 µs. During weak signal conditions (noise detector active) the gating is active during thecomplete scan period and the width of the gate pulse is reduced to 5.7 µs so that the effect of noise is reduced to aminimum.

The output current of the phase detector in the various conditions are shown in Table 269.

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57. The ICs have 2 protection inputs. The protection on the second phase detector pin is intended to be used as ‘flash’protection. When this protection is activated the horizontal drive is switched-off immediately and then switched-onagain via the slow start procedure.

The protection on the EHT input is intended for overvoltage (X-ray) protection. When this protection is activated thehorizontal drive is directly switched-off (via the slow stop procedure).

The EHT protection input can also be used to switch-off the TV receiver in a correct way when it is switched off viathe mains power switch or when the power supply is interrupted by pulling the mains plug. This can be realised bymeans of a detection circuit which monitors the main supply voltage of the receiver. When this voltage suddenlydecreases the EHT protection input must be pulled HIGH and then the horizontal drive is switched off via the slowstop procedure. Whether the EHT capacitor is discharged in the overscan or not during the switch-off period dependson the setting of the OSO bit (subaddress 3EH, D4). See also note 75.

58. The control range indicates the maximum phase difference at the top and the bottom of the screen. Compared withthe phase position at the centre of the screen the maximum phase difference at the top and the bottom of the screenis ±0.75 µs for the parallelogram and ±1.0 µs for the bow correction.

59. During switch-on the horizontal drive starts-up in a soft-start mode. The horizontal drive starts with a very short TONtime of the horizontal output transistor, the ‘off time’ of the transistor is identical to the ‘off time’ in normal operation.The starting frequency during switch-on is therefore about 2 times higher than the normal value. The ‘on time’ isslowly increased to the nominal value in a time of about 1175 ms (see Fig.81). The rather slow rise of the TONbetween 75% and 100% of TON is introduced to obtain a sufficiently slow rise of the EHT for picture tubes withDynamic Astigmatic Focus (DAF) guns. When the nominal frequency is reached the PLL is closed in such a way thatonly very small phase corrections are necessary. This ensures a safe operation of the output stage.

During switch-off the soft-stop function is active. This is realised by doubling the frequency of the horizontal outputpulse. The switch-off time is about 43 ms (see Fig.81). When the ‘switch off command’ is received the soft-stopprocedure is started after a delay of about 2 ms. During the switch-off time the EHT capacitor of the picture tube isdischarged with a fixed beam current which is forced by the black current loop (see also note 75). The discharge timeis about 38 ms.

The horizontal output is gated with the flyback pulse so that the horizontal output transistor cannot be switched-onduring the flyback time.

60. The vertical blanking pulse in the RGB outputs has a width of 27 or 22 lines (50 or 60 Hz system). The vertical pulsein the sandcastle pulse has a width of 14 or 9.5 lines (50 or 60 Hz system). This to prevent a phase distortion on topof the picture due to a timing modulation of the incoming flyback pulse.

61. The timing pulses for the vertical ramp generator are obtained from the horizontal oscillator via a divider circuit.During TV reception this divider circuit has 3 modes of operation:

a) Search mode ‘large window’.

This mode is switched on when the circuit is not synchronized or when a non-standard signal (number of linesper frame outside the range between 311 and 314(50 Hz mode) or between 261 and 264 (60 Hz mode) isreceived). In the search mode the divider can be triggered between line 244 and line 361 (approximately45 to 64.5 Hz).

b) Standard mode ‘narrow window’.

This mode is switched on when more than 15 succeeding vertical sync pulses are detected in the narrow window.The IVWF bit in output byte 03 is set to “1” when 7 succeeding vertical sync pulses are detected in the narrowwindow. When the circuit is in the standard mode and a vertical sync pulse is missing the retrace of the verticalramp generator is started at the end of the window. Consequently, the disturbance of the picture is very small.The circuit will switch back to the search window when, for 6 successive vertical periods, no sync pulses are foundwithin the window.

2003 Nov 11 215



CONFIDENTIAL

c) Standard TV-norm (divider ratio 525 (60 Hz) or 625 (50 Hz).

When the system is switched to the narrow window it is checked whether the incoming vertical sync pulses arein accordance with the TV-norm. When 15 standard TV-norm pulses are counted the divider system is switchedto the standard divider ratio mode. In this mode the divider is always reset at the standard value even if the verticalsync pulse is missing.

When 3 vertical sync pulses are missed the system switches back to the narrow window and when also in thiswindow no sync pulses are found (condition 3 missing pulses) the system switches over to the search window.

The vertical divider needs some waiting time during channel-switching of the tuner. When a fast reaction of thedivider is required during channel-switching the system can be forced to the search window by means of the NCIN bitin subaddress 3EH.

When RGB signals are inserted the maximum vertical frequency is increased to 72 Hz. This has the consequencethat the circuit can also be synchronised by signals with a higher vertical frequency like VGA.

62. Conditions: frequency is 50 Hz; normal mode; VS = 1F.

63. The output range percentages mentioned for E-W control parameters are based on the assumption that 400 µAvariation in E-W output current is equivalent to 20% variation in picture width.

64. The ICs have a zoom adjustment possibility for the horizontal and vertical deflection. For this reason an extra DAChas been added in the vertical amplitude control which controls the vertical scan amplitude between 0.75 and 1.38of the nominal scan. At an amplitude of 1.06 of the nominal scan the output current is limited and the blanking of theRGB outputs is activated. This is illustrated in Fig. 79.

When the vertical amplitude is compressed (zoom factor <1) it is still possible to display the black-current measuringlines in the vertical overscan. The feature is activated by means of the OSVE-bit in subaddress 40H. Because thevertical deflection output stage needs some time for the excursion from the top of the picture to the required positionon the screen the vertical blanking is increased when the OSVE-bit is activated. The shape of the vertical deflectioncurrent for a zoom factor of 0.75 with OSVE activated is given in Fig. 80. The exact timing of the measuring pulsesand vertical blanking for the various conditions is given in Fig. 82.

The nominal scan height must be adjusted at a position of 19 HEX of the vertical ‘zoom’ DAC.

65. At a chrominance input voltage of 660 mV (p-p) (colour bar with 75% saturation i.e. burst signal amplitude300 mV (p-p)) the dynamic range of the ACC is +6 and −20 dB.

66. The ACL function can be activated by via the ACL bit in the subaddress 3BH. The ACL circuit reduces the gain ofthe chroma amplifier for input signals with a chroma-to-burst ratio which exceeds a value of 3.0.

67. This parameter indicates the bandwidth of the complete chrominance circuit including the chrominance bandpassfilter. The bandwidth of the low-pass filter of the demodulator is approximately 1 MHz.

68. The subcarrier output is combined with a 3-level switch output which can be used to switch external circuits likesound traps etc. This output is controlled by the CMB1 and CMB0 bits in control byte 22H. The subcarrier signal isavailable when CMB1/0 are set to 0/1. During the demodulation of SECAM signals the subcarrier signal is onlyavailable during the vertical retrace period. The frequency is 4.43 MHz in this condition.

69. Because of the 2-point black current stabilization circuit both the black level and the amplitude of the RGB outputsignals depend on the drive characteristic of the picture tube. The system checks whether the returning measuringcurrents meet the requirement and adapts the output level and gain of the circuit when necessary. Therefore thetypical value of the black level and amplitude at the output are just given as an indication for the design of the RGBoutput stage.

The 2-point black level system adapts the drive voltage for each cathode in such a way that the 2 measuring currentshave the right value. This has the consequence that a change in the gain of the output stage will be compensatedby a gain change of the RGB control circuit. Because different picture tubes may require different drive voltageamplitudes the ratio between the output signal amplitude and the inserted measuring pulses can be adapted via theI2C-bus. This is indicated in the parameter C.4.13.

Because of the dependence of the output signal amplitude on the application the soft clipping limiting has beenrelated to the input signal amplitude.

2003 Nov 11 216



CONFIDENTIAL

70. The alignment system for the Vg2 voltage of the picture tube can be activated by means of the AVG bit. In thatcondition a certain black level is inserted at the RGB outputs during a few lines. The value of this level can beadjusted by means of the brightness control DAC. An automatic adjustment of the Vg2 of the picture tube can berealised by using the WBC and HBC bits in output byte 01. These bits indicate whether the black level feedbackcurrent is inside or outside the window between 12 and 20 µA. The indication of these bits can be made visible onthe screen via OSD so that this alignment procedure can also be used for service purposes. Because the gain loopis digital quantization steps may occur in the read-out of the WBC and HBC bits.

71. When the reproduction of 4 : 3 pictures on a 16 : 9 picture tube is realised by means of a reduction of the horizontalscan amplitude the edges of the picture may slightly be disturbed. This effect can be prevented by adding anadditional blanking to the RGB signals. The blanking pulse is derived form the horizontal oscillator and is directlyrelated to the incoming video signal (independent of the flyback pulse). This blanking is activated with the HBL bit.The width of the blanking can be set by means of the bits WBF3-WBF0 (start of blanking) and WBR3-WBR0 (end ofblanking) in subaddress 26H (see Fig.85).

When the Double Window feature is activated it may be necessary to increase the width of the wide blanking. Thiscan be realised by means of the WBI bit (subaddress 3EH).

72. This parameter is valid only when the CCC loop is active.

73. Signal-to-noise ratio (S/N) is specified as peak-to-peak signal with respect to RMS noise (bandwidth 5 MHz).

74. This is a current input. The timing of the measuring pulses and the vertical blanking for the 50/60 Hz standard aregiven in Fig.82

The start-up procedure is as follows.

When the TV receiver is switched-on the RGB outputs are blanked and the black-current loop will try to adjust thepicture tube to the right bias levels. The RGB drive signals are switched-on as soon as the black current loop isstabilised. This results in the shortest switch-on time.

When this switch-on system results in a visible disturbance of the picture it is possible to add a further switch-on delayvia a software routine. In that case the RGB outputs must be blanked by means of the RBL bit. The condition of thegain loop and the total black current loop can be read from the GLOK and BCF bits. This information can be used toswitch-on the RGB outputs after some additional delay.

75. During switch-off the magnitude of the discharge current of the picture tube is controlled by the black current loop.Dependent on the setting of the OSO bit the vertical scan can be stopped in an overscan position during that time sothat the discharge is not visible on the screen. The switch-off procedure is as follows:

a) When the switch-off command is received the RGB outputs are blanked for a time of about 2 ms.

b) If OSO = 1 the vertical scan is placed in an overscan position

c) If OSO = 0 the vertical deflection will keep running during the switch-off time

d) The soft-stop procedure is started by doubling the frequency of the horizontal output pulse

e) The fixed beam current is forced via the black current loop

f) The soft-stop time has a value of 43 ms, the fixed beam current is flowing during a time of 38 ms.

76. The control circuit contains a Peak White Limiting (PWL) circuit and a soft clipper.

a) The detection level of the PWL is adjustable via the I2C-bus and has a control range between 0.4 and 0.6 VBL-WH(this amplitude is related to the CVBS/Y input signal (typical amplitude 0.7 VBL-WH) at maximum contrast setting).The high frequency components of the video signal are suppressed so that they do not activate the limiting action.The contrast reduction of the PWL is obtained by discharging the capacitor of the beam current limiting input.

b) In addition to the PWL circuit the IC contains a soft clipper function which limits the high frequency signals whenthey exceed the peak white limiting level. The difference between the peak white limiting level and the soft clippinglevel is adjustable via the I2C-bus and can be varied between 0 and 10% in 3 steps (soft clipping level equal orhigher than the PWL level). It is also possible to switch-off the soft clipping function.

2003 Nov 11 217



CONFIDENTIAL

77. The soft clipper gain reduction is measured by applying a sawtooth signal with rising slope and 0.7 VBL-WH at theCVBS input. To prevent the beam current limiter from operating a DC voltage of 3.5V must be applied to BCLIN pin.The contrast is set at the maximum value, the PWL (peak white limiting) level at the minimum value, and the softclipping level is set at 0% above the PWL level (SOC10=00). The tangents of the sawtooth waveform at one of theRGB outputs is now determined at begin and end of the sawtooth. The soft clipper gain reduction is defined as theratio of the slopes of the tangents for black and white, see Fig.84.

78. The VGUARD/SWIO pin can be used for various purposes. The various combinations are given below.

a) Just vertical guard input.

b) Combination of vertical guard and LED drive output. In this condition the output is high-ohmic during the verticalretrace (1 ms) so that the vertical guard pulse can be detected.

c) Single ended output switch

d) Input port

The functionality of this pin is controlled by the VGM1/0 and LED bits.

Table 268 Output signal amplitude of deemphasis pin as function of AGN and AMLOW bits; note 1

Note

1. The indicated values are valid for a modulation index of 54% for both the FM and AM signal

Table 269 Output current of the phase detector in the various conditions

Note

1. Gating is active during vertical retrace, the width is 22 µs. This gating prevents disturbance due to Macro Vision AntiCopy signals.

2. Gating is continuously active and is 5.7 µs wide

AGN AMLOWOUTPUT LEVEL DURING FM

RECEPTIONOUTPUT LEVEL DURING AM

RECEPTION

0 0 125 mVRMS 250 mVRMS




I2C-BUS COMMANDS IC CONDITIONS ϕ-1 CURRENT/MODE

VID POC FOA FOB IFI SL NOISE SCAN V-RETR GATING MODE

− 0 0 0 yes yes no 200 300 yes (1) normal

− 0 0 0 yes yes yes 30 30 yes(2) normal

− 0 0 0 yes no − 200 300 no normal

− 0 0 1 yes yes − 30 30 yes(2) slow

− 0 0 1 yes no − 200 300 no slow

− 0 1 0 yes yes − 6 6 no OSD

− − 1 1 − − − 200 300 yes(1) fast

0 0 − − no − − 6 6 no OSD

− 1 − − − − − − − − off

2003 Nov 11 218



CONFIDENTIAL

handbook, halfpage

MGR447

100 kΩ

XTALI XTALO

crystalor

ceramicresonator

RiLi CiCi

gm

Cp

Ca Cb

Fig.52 Simplified diagram crystal oscillator.

fosc1

Li

Ci Ctot×Ci Ctot+----------------------×2π

-----------------------------------------=

Ctot Cp

Ca Cb×Ca Cb+--------------------+=

Ca = Ci + Cx1

Cb = Co + Cx2

276

XTALIN XTALOUT

Cx2Cx1

CoCi

Fig. 53 Volume control curve

0

-20

-40

-60

-80

0 20 40 60 80DAC (HEX)

dB

Fig. 54 Peaking control curve.

Overshoot in direction ‘black’.

0 10 20 30 40DAC (HEX)

20

40

60

80

%

−20

0

2003 Nov 11 219



CONFIDENTIAL

Fig.55 Hue control curve.

+50

+30

+10

−10

−30

−50

(deg)

0 10 20 30 40DAC(HEX)

Fig.56 Base-band tint control curve.

+50

+30

+10

−10

−30

−50

(deg)

0 10 20 30 40DAC(HEX)

MLA740 - 1

250

25

0

(%)

0 10 20 30 40DAC (HEX)

50

75

100

125

150

175

200

225

Fig. 57 Saturation control curve.

300

250

200

150

100

50

0

%

MLA741 - 1

90

50

10

(%)

0 10 20 30 40DAC (HEX)

20

30

40

60

70

80

100

Fig. 58 Contrast control curve.

2003 Nov 11 220



CONFIDENTIAL

Fig. 59 Brightness control curve.

MLA742 - 1

0.7

0.35

0

0.35

0.7

0

(V)

0 10 20 30 40DAC (HEX)

+0.4

+0.2

0

-0.2

-0.4

(V)

MBC212

100%92%

30%

16 %

for negative modulation100% = 10% rest carrier

Fig. 60 Video output signal.

MBC211

100%

86%

72%

58%

44%

30%

646056524844403632221210 26 µs

Fig. 61 Test signal waveform.

2003 Nov 11 221



CONFIDENTIAL

MBC213SC CC PC

30 dB

13.2 dB

3.2 dB

SC CC PC

30 dB

13.2 dB

10 dB

BLUE YELLOW

MBC210

ATTENUATORSPECTRUMANALYZER

TESTCIRCUIT

CC

PC

SC Σ

gain settingadjusted for blue

Fig. 62 Test set-up intermodulation.

Input signal conditions: SC = sound carrier; CC = colour carrier; PC = picture carrier.All amplitudes with respect to top sync level.

Value at 0.92 or 1.1 MHz 20 logVO at 3.58 or 4.4 MHz

VO at 0.92 or 1.1 MHz------------------------------------------------------------ 3.6 dB+=

Value at 2.66 or 3.3 MHz 20 logVO at 3.58 or 4.4 MHz

VO at 2.66 or 3.3 MHz------------------------------------------------------------=

2003 Nov 11 222



CONFIDENTIAL

0.0500.0k

1.0M1.5M

2.0M2.5M

3.0M3.5M

4.0M4.5M

5.0M

(LIN)

-25.0n

0.0

25.0n

50.0n

75.0n

100.0n

125.0n

150.0n

175.0n

200.0n

225.0n (LIN)

Apr 16, 200218:39:04

Analysis: AC

User: nyoudees Simulation date: 16-04-2002, 16:54:30

File: /user/nyoudees/kn10241d/simulation/kn10241d_sndgrp_sim/sndgrp_sim1/Pstar/schematic/netlist/sndgrp_sim1.c.sdif

F

- y1-axis -

grp_55

- Subvar -GD: 0.0ST1: 0.0ST0: 0.0FILCON: 1.962

_4.43M 197.853n

Fig.63 Group delay characteristic without group delay correction (sound trap: 5.5 MHz)

0.0500.0k

1.0M1.5M

2.0M2.5M

3.0M3.5M

4.0M4.5M

5.0M

(LIN)

-100.0n

-50.0n

0.0

50.0n

100.0n

150.0n

200.0n

250.0n

300.0n

350.0n

400.0n (LIN)

Apr 16, 200218:51:44

Analysis: AC

User: nyoudees Simulation date: 16-04-2002, 16:54:30

File: /user/nyoudees/kn10241d/simulation/kn10241d_sndgrp_sim/sndgrp_sim1/Pstar/schematic/netlist/sndgrp_sim1.c.sdif

F

- y1-axis -

grp_gd

- Subvar -GD: 1.0ST1: 0.0ST0: 0.0FILCON: 1.962

_2.42M -60.205n

_3.74M 406.163p

_4.43M 177.613n

Fig.64 Group delay characteristic with group delay correction (sound trap: 5.5 MHz)

2003 Nov 11 223



CONFIDENTIAL

CHARACTERISTIC POINTS AVL A B C D UNIT

Deemphasis voltage 60 125 250 600 mVRMS

Fig. 65 AVL characteristic

A B C D

1.8 V

1.0 V

0.1 V

10 mV 100 mV 1 V

Out

put v

olta

ge

Deemphasis voltage

These curves are valid for an audio supply voltage of 5 V. When the supply voltage is increased to 8 V the audiooutput signal is increased with 6 dB.

2003 Nov 11 224



CONFIDENTIAL

Fig.66 CCIR-18 multi-burst

(V)

1.0

0.3

0.0

0.15

0.45

0.65

0.5 1.0 2.0 3.8 4.8 5.8 MHz

0.44

0.86

Fig.67 100% amplitude FCC multi-burst

(V)

1.0

0.3

0.0

0.15

0.45

0.65

0.5 1.5 2.0 3.0 3.58 4.1 MHz

2003 Nov 11 225



CONFIDENTIAL

Fig.68 Vertical transitions active video ↔ vertical blanking from line to line, PAL systems.

Transition at top of field:

line n-2 line n-1 line n line n+1 line n+2 line n+3

input:

output:

line n-2line n

line n+1 line n+2 line n+3

Transition at bottom of field:

input:

line n+3line n+2line n+1line nline n-1line n-2

output:

line n+3line n+1line nline n-1line n-2

cross talk

cross talk

line n-1

cross talk

line n+2

cross talk

Fig.69 Vertical transitions active video ↔ vertical blanking from line to line, NTSC system

Transition at top of field:

line n-2 line n-1 line n line n+1 line n+2 line n+3

input:

output:

line n-2 line n-1line n

line n+1 line n+2 line n+3

Transition at bottom of field:

input:


output:


cross talk

cross talk

2003 Nov 11 226



CONFIDENTIAL

1 fsc 2 fsc0

1

0.5

0

Comb depth at f = f SC

Detailed view:

1

0.5

0

Luminance

Fig.70 Luminance transfer characteristic

UVVU U

Y Y

2003 Nov 11 227



CONFIDENTIAL

1 fsc 2 fsc0

1

0.5

0

Comb depth at f = (284/283.75)f SCDetailed view:

1

0.5

0

Chrominance

Fig.71 Chrominance transfer characteristic

Y Y

VUVU

2003 Nov 11 228



CONFIDENTIAL

Fig. 72 I/O relation of the black level stretch circuit (BSD = 0)

OUTPUT (IRE)

100

80

60

40

20

0

-20

A

A

B

B

20 40 60 80 100

INPUT (IRE)

A-A: MAXIMUM BLACK LEVEL SHIFT

B-B: LEVEL SHIFT AT 15% OF PEAK WHITE

2003 Nov 11 229



CONFIDENTIAL

Fig.73 Skin tone correction range for the correction angle of 123 deg.

I-axis

V

U

red

yellow

fully saturated colours

YIN 100%0%

YOUT

100%

0%

maximumexpansion

Fig.74 Gamma control characteristic

Expansion is dependent on thesetting of the WS1/WS0 bits

2003 Nov 11 230



CONFIDENTIAL

10%

5%

Gainincrease

10 20 30 40 50APL-level

Fig.75 Gamma control (white stretch) characteristic; Gain increase as function of APL level and WS1/WS0 setting

WS1/WS0 = 1/1

WS1/WS0 = 1/0

WS1/WS0 = 0/1

Fig.76 Blue stretch characteristicPeak white level (%)

Out

put (

%)

80 85 90 95 100

85

90

95

100

BLUE (BLS=1)

GREEN (BLS=1)

RED (BLS=1)

104

RGB (BLS=0)

2003 Nov 11 231



CONFIDENTIAL

Fig.77 SVM Gain-curve

050% 100%

input-amplitude

1.8Vp-p

(% of nominal input)

output-amplitude

coring

gain

soft-clipping

CRA0=1

CRA0=0

050% 100%

input-amplitude

1.8Vp-p

(% of nominal input)

output-amplitude

coring

gain

SVMA = 1

CRA0=0 CRA0=1

SVMA = 0

Horizontal position

SVM gain

0dB

-6dB

-3dB

A B C C B A

*

* Depending on VMA0, VMA1

curve at SPR2=1, SPR1=0 and SPR0=1

Fig.78 Parabola on the SVM output

2003 Nov 11 232



CONFIDENTIAL

TOP

PICTURE

BOTTOMPICTURE

138%

100%

75%

T/2 T

60

50

40

30

20

10

0

-10

-20

-30

-40

-50

-60

VE

RT

ICA

L P

OS

ITIO

N

TIME

BLANKING FOR EXPANSION OF 138%

Fig. 79 Vertical position and blanking pulse for 110° types

%

2003 Nov 11 233



CONFIDENTIAL

Fig.80 Measuring lines in vertical overscan for vertical compressed scan

V-DRIVE

I-COIL

Measuring lines

Vertical blanking

2003 Nov 11

234

Philips S

emiconductors

Prelim

inary specification


- andm

id-range TV

applicationsU

OC

III series

CO

NF

IDE

NT

IAL

TON

(%)

50

100

Fig. 81 Soft start and soft stop behaviour of horizontal output and timing picture tube discharge current

57 73 1045 50

38

Discharge currentpicture tube

Time (ms)

Soft start

Soft stop

75

12

FrequencyHOUT = 2xFH

25

2003 Nov 11 235



CONFIDENTIAL

Fig

.82

Tim

ing

of v

ertic

al b

lank

ing

and

blac

k cu

rren

t mea

surin

g pu

lses

Res

et V

ert.

Saw

Ver

t. B

lank

Bla

ck c

urre

nt p

ulse

s

Vid

eo62

523

Vid

eo31

233

6

Bla

ck c

urre

nt p

ulse

s

Ver

t. B

lank

RE

SE

T L

INE

CO

UN

TE

R

Res

et V

ert.

Saw

Ver

t. B

lank

Bla

ck c

urre

nt p

ulse

s

inte

rnal

LR

GB

50H

z

60H

z

1ST

2ND

1ST

2ND

sign

al

sign

al

inte

rnal

FIE

LD

FIE

LD

FIE

LD

FIE

LD

2fH c

lock

Ver

t. B

lank

Bla

ck c

urre

nt p

ulse

s

2fH c

lock

LR

GB

4.5

lines

(O

SV

E a

nd E

VB

= 0

)12

.5 li

nes

(OS

VE

= 1

)

4.5

lines

(O

SV

E a

nd E

VB

= 0

)12

line

s (O

SV

E =

1)

14 li

nes

1718

1920

329

330

331

332

end

line

23 (

OS

VE

and

EV

B =

0)

end

line

33 (

OS

VE

= 1

)

line

335.

5 (O

SV

E a

nd E

VB

= 0

)en

d lin

e 34

5 (O

SV

E =

1)

LR

GB

LR

GB

1718

1920

279

280

281

282

end

line

20 (

OS

VE

and

EV

B =

0)

end

line

30 (

OS

VE

= 1

)

line

282.

5 (O

SV

E a

nd E

VB

= 0

)en

d lin

e 29

2 (O

SV

E =

1)

4 lin

es (

OS

VE

and

EV

B =

0)

14.5

line

s (O

SV

E =

1)

4 lin

es (

OS

VE

and

EV

B =

0)

14 li

nes

(OS

VE

= 1

)

9.5

lines

9.5

lines

(E

VB

= 1

)

9.5

lines

(E

VB

= 1

)

9 lin

es (

EV

B =

1)

9 lin

es (

EV

B =

1)

line

27.5

(E

VB

= 1

)

end

line

340

(EV

B =

1)

end

line

23 (

EV

B =

1)

line

285.

5 (E

VB

= 1

)

Not

e 1:

Whe

n O

SV

E a

nd E

VB

are

‘1’ t

he O

SV

E b

lank

ing

valu

e is

val

id

Vid

eo52

5

281

RE

SE

T L

INE

CO

UN

TE

R

sign

al

19

Vid

eo26

2R

ES

ET

LIN

E C

OU

NT

ER

sign

al

Not

e 2:

The

ver

tical

bla

nkin

g is

als

o de

pend

ent o

n th

e ve

rtic

al “

Zoo

m”

and

“Scr

oll”

setti

ng

2003 Nov 11 236



CONFIDENTIAL

SY

NC

1st F

IELD RE

Fφ-

1 SY

NC

2nd

FIE

LD

RE

Fφ-

1

14 li

nes

CS

Y

14 li

nes

CS

Y

Fig

.83

H/V

tim

ing

outp

ut (

CS

Y)

on th

e fly

back

inpu

t pin

(F

BIS

O)

in th

e “L

CD

/100

Hz”

mod

e

2003 Nov 11 237



CONFIDENTIAL

Fig.84 Peak White Limiting / Soft clipper characteristic.

20 40 60 80 100

1.2

1.8

CVBS IN (IRE)

clipper off

clipper on

0.6

RGBout(Vb-w)

PWL setting

2.4

120 130

00H 08H 0FH

Soft clipping

range

(Defined by

SOC1/SOC0 bits)

VIDEO

REF Φ-1

BURST KEY

BLANKING3.5 µs 7.8 µs5.9 µs 10.2 µs

15 steps of 0.16 µs 15 steps of 0.16 µs

Fig.85 Timing of horizontal wide blanking

2003 Nov 11 238



CONFIDENTIAL

TEST AND APPLICATION INFORMATION

East-West output stage

In order to obtain correct tracking of the vertical andhorizontal EHT-correction, the EW output stage should bedimensioned as illustrated in Fig.86.

Resistor REW determines the gain of the EW output stage.Resistor Rc determines the reference current for both thevertical sawtooth generator and the geometry processor.The preferred value of Rc is 39 kΩ which results in areference current of 50 µA (Vref = 1.95 V).

The value of REW must be:

Example: With Vref = 1.95 V; Rc = 39 kΩ andVscan = 120 V then REW = 68 kΩ.

REW Rc

Vscan

36 Vref×-----------------------×=

book, full pagewidth

MLA744 - 1

TDA8366

HORIZONTALDEFLECTION

STAGE

DIODE MODULATOR

VDD

Vscan

VEW

Rew

EW outputstage

EWD

Csaw

100 nF(5%)

VrefRc

39 kΩ(2%)

I ref

43

4950

TDA 935X21

28 27

TDA110XXH*21

27 26

Fig.86 East-West output stage

150 nF

TDA120XXH*series

2003 Nov 11 239



CONFIDENTIAL

Fig. 87 Control range of vertical amplitude.

VA = 0, 20H and 3FH; VSH = 1FH; SC = 0EH.

Fig. 88 Control range of vertical slope.

VS = 0, 20H and 3FH; VA = 1FH; VSH = 1FH; SC = 0EH.

700

500

300

100

-100

-300

-500

-700

IVERT

(µA)

TIME0 T/2 T

Fig. 89 Control range of vertical shift.

VSH = 0, 20H and 3FH; VA = 1FH; SC = 0EH.

-1.0-750.0m

-500.0m-250.0m

0.0250.0m

500.0m750.0m

1.0

Fig. 90 Control range of S-correction.

SC = 0, 0EH and 3FH; VA = 1FH; VSH = 1FH.

TIME0 T/2 T

IVERT

(µA)

600

400

200

0

-200

-400

-600

2003 Nov 11 240



CONFIDENTIAL

0.0200.0m

400.0m600.0m

800.0m1.0

Fig. 91 Control range of EW width.

EW = 0, 20H and 3FH; PW = 3FH; TC = 1FH; CP = 10H.

1200

1000

800

600

400

200

0

IEW

(µA)

0 T/2 TTIME 0.0200.0m

400.0m600.0m

800.0m1.0

Fig. 92 Control range of EW parabola/width ratio.

PW = 0, 20H and 3FH; EW = 3FH; TC = 1FH; CP = 10H.

IEW

(µA)

0 T/2 TTIME

500

400

300

200

100

0

0.0200.0m

400.0m600.0m

800.0m1.0

Fig. 93 Control range of EW corner/parabola ratio.

CP = 0, 20H and 3FH; EW = 3FH; PW = 3FH;TC = 1FH.

0 T/2 TTIME

IEW

(µA)

500

400

300

200

100

0 0.0200.0m

400.0m600.0m

800.0m1

Fig. 94 Control range of EW trapezium correction.

TC = 0, 20H and 3FH; EW = 1FH; PW = 1FH; CP = 10H.

IEW

(µA)

0 T/2 TTIME

650

600

550

500

450

400

350

2003 Nov 11 241



CONFIDENTIAL

0.0200.0m

400.0m600.0m

800.0m1.00 T/2 TTIME

IVERT

(µA)

600

400

0

-200

-400

-600

Fig.95 Vertical linearity control

VLIN = 0, 20H and 3FH; VA=1FH; VSH=1FH; SC=0

200

2003 Nov 11 242



CONFIDENTIAL

Adjustment of geometry control parameters

The deflection processor offers the following parametersfor picture alignment, viz:

• vertical amplitude

• vertical slope

• S-correction

• vertical shift

• Vertical zoom and vertical scroll

• Vertical linearity correction, when required the linearitysetting of the upper and lower part of the screen can bedifferent.

• horizontal shift.

• EW width

• EW parabola width

• EW upper/lower corner parabola

• EW trapezium correction.

• Horizontal parallelogram and bow correction

It is important to notice that the ICs are designed for usewith a DC-coupled vertical deflection stage. This is thereason why a vertical linearity alignment is not necessary(and therefore not available).

For a particular combination of picture tube type, verticaloutput stage and EW output stage it is determined whichare the required values for the settings of S-correction, EWparabola/width ratio and EW corner/parabola ratio. Theseparameters can be preset via the I2C-bus, and do not needany additional adjustment. The rest of the parameters arepreset with the mid-value of their control range (i.e. 1FH),or with the values obtained by previous TV-setadjustments.

The vertical shift control is meant for compensation ofoff-sets in the external vertical output stage or in thepicture tube. It can be shown that without compensationthese off-sets will result in a certain linearity error,especially with picture tubes that need large S-correction.The total linearity error is in first order approximationproportional to the value of the off-set, and to the square ofthe S-correction needed. The necessity to use the verticalshift alignment depends on the expected off-sets in verticaloutput stage and picture tube, on the required value of theS-correction, and on the demands upon vertical linearity.

For adjustment of the vertical shift and vertical slopeindependent of each other, a special service blankingmode can be entered by setting the SBL bit HIGH. In thismode the RGB-outputs are blanked during the second halfof the picture. There are 2 different methods for alignmentof the picture in vertical direction. Both methods make useof the service blanking mode.

The first method is recommended for picture tubes thathave a marking for the middle of the screen. With thevertical shift control the last line of the visible picture ispositioned exactly in the middle of the screen. After thisadjustment the vertical shift should not be changed. Thetop of the picture is placed by adjustment of the verticalamplitude, and the bottom by adjustment of the verticalslope.

The second method is recommended for picture tubes thathave no marking for the middle of the screen. For thismethod a video signal is required in which the middle of thepicture is indicated (e.g. the white line in the circle testpattern). With the vertical slope control the beginning of theblanking is positioned exactly on the middle of the picture.Then the top and bottom of the picture are placedsymmetrical with respect to the middle of the screen byadjustment of the vertical amplitude and vertical shift.After this adjustment the vertical shift has the right settingand should not be changed.

If the vertical shift alignment is not required VSH should beset to its mid-value (i.e. VSH = 1F). Then the top of thepicture is placed by adjustment of the vertical amplitudeand the bottom by adjustment of the vertical slope. Afterthe vertical picture alignment the picture is positioned inthe horizontal direction by adjustment of the EW width andthe horizontal shift. Finally (if necessary) the left- andright-hand sides of the picture are aligned in parallel byadjusting the EW trapezium control.

To obtain the full range of the vertical zoom function theadjustment of the vertical geometry should be carried outat a nominal setting of the zoom DAC at position 19 HEX.

2003 Nov 11 243



CONFIDENTIAL

PACKAGE OUTLINE

UNIT A1 A2 A3 bp c E(1) e HE L L p ywv θ

REFERENCESOUTLINEVERSION

EUROPEANPROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.250.05

3.703.15 0.25

0.450.30

0.230.11

28.127.9 0.8

1.81.4

θ1

65o

55o

7o

0o0.20.25 0.11.95

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.950.55

SOT320-3 - - - MO-112 03-02-19

D(1)

28.127.9

HD

32.231.6

32.231.6

ZD(1) ZE(1)

1.81.4

0 5 10 mm

scale

pin 1 index

bp

bp

e

e

E

B

32

c

DH v M B

D

ZE

ZD

HE

A

v M A

X

1

128

97

96 65

64

33

y

w M

w M

128 leads (lead length 1.95 mm); body 28 x 28 x 3.4 mm; lead angle 60 o

QFP128: plastic quad flat package;SOT320-3

Amax.

3.95

θ

θ1

A

Lp

detail XL

(A3)A2

A1

2003 Nov 11 244



CONFIDENTIAL

SOLDERING

Introduction

There is no soldering method that is ideal for all ICpackages. Wave soldering is often preferred whenthrough-hole and surface mounted components are mixedon one printed-circuit board. However, wave soldering isnot always suitable for surface mounted ICs, or forprinted-circuits with high population densities. In thesesituations reflow soldering is often used.

This text gives a very brief insight to a complex technology.A more in-depth account of soldering ICs can be found inour “IC package Databook” (order code 9398 652 90011).

QFP

REFLOW SOLDERING

Reflow soldering techniques are suitable for all QFPpackages.

The choice of heating method may be influenced by largerplastic QFP packages (44 leads, or more). If infrared orvapour phase heating is used and the large packages arenot absolutely dry (less than 0.1% moisture content byweight), vaporization of the small amount of moisture inthem can cause cracking of the plastic body. For details,refer to the Drypack information in our “Quality ReferenceHandbook” (order code 9397 750 00192).

Reflow soldering requires solder paste (a suspension offine solder particles, flux and binding agent) to be appliedto the printed-circuit board by screen printing, stencilling orpressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,infrared/convection heating in a conveyor type oven.Throughput times (preheating, soldering and cooling) varybetween 50 and 300 seconds depending on heatingmethod. Typical reflow peak temperatures range from215 to 250 °C.

WAVE SOLDERING

Wave soldering is not recommended for QFP packages.This is because of the likelihood of solder bridging due toclosely-spaced leads and the possibility of incompletesolder penetration in multi-lead devices.

If wave soldering cannot be avoided, for QFPpackages with a pitch (e) larger than 0.5 mm, thefollowing conditions must be observed:

• A double-wave (a turbulent wave with high upwardpressure followed by a smooth laminar wave)soldering technique should be used.

• The footprint must be at an angle of 45 ° to the boarddirection and must incorporate solder thievesdownstream and at the side corners.

During placement and before soldering, the package mustbe fixed with a droplet of adhesive. The adhesive can beapplied by screen printing, pin transfer or syringedispensing. The package can be soldered after theadhesive is cured.

Maximum permissible solder temperature is 260 °C, andmaximum duration of package immersion in solder is10 seconds, if cooled to less than 150 °C within6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removalof corrosive residues in most applications.

REPAIRING SOLDERED JOINTS

Fix the component by first soldering two diagonally-opposite end leads. Use only a low voltage soldering iron(less than 24 V) applied to the flat part of the lead. Contacttime must be limited to 10 seconds at up to 300 °C. Whenusing a dedicated tool, all other leads can be soldered inone operation within 2 to 5 seconds between270 and 320 °C.

2003 Nov 11 245



CONFIDENTIAL

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of theseproducts can reasonably be expected to result in personal injury. Philips customers using or selling these products foruse in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from suchimproper use or sale.

PURCHASE OF PHILIPS I2C COMPONENTS

Data sheet status

Objective specification This data sheet contains target or goal specifications for product development.

Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.

Product specification This data sheet contains final product specifications.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one ormore of the limiting values may cause permanent damage to the device. These are stress ratings only and operationof the device at these or at any other conditions above those given in the Characteristics sections of the specificationis not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification.

Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use thecomponents in the I2C system provided the system conforms to the I2C specification defined byPhilips. This specification can be ordered using the code 9398 393 40011.

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