phase change memory-arjun

8/3/2019 Phase Change Memory-Arjun

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PHASE CHANGE MEMORY

(PCM)

ARJUN P RAJ

S7 EEE

ROLL NO:9

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INTRODUCTION

Modern computer system demands huge

amount of memor y

Current DRAM based main memor y starting to

hit power and cost limit

Therefore resear ch for new memories that have

higher capacity than Dram while still being

competitive in terms of power and cost

One of the most promising among them is

PHASE CHANGE MEMORY (PCM)

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What is PCM?

PCM is a non volatile memor y that exploits the property of chalcogenide glass, to switch

between two states amorphous and crystalline,

with the application of heat using current pulses.

It exploits the difference in the electrical

resistivity of the material in these different

phases.

R ecent ver sions with multi level cell storage can achieve two additional distinct states, effectively

dou bling its storage capacity

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PE

w

o r d - l

i n e s

bit-lines

Figure2:A typical PCM cell

Figure 3:

Memory array with NMOS transistors Figure1 :basic structure of a PCM cell

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Chalcogenide mater ials

Chalcogenide materials are alloys

with a group VI element

(usually com bined with IV and V group

elements)

Used in CDs and DVDs as well

Ge2Sb2Te5 (GST),

Ge-Germanium

Sb-Antimony

Te- TelluriumNitrogen-doped GST,

Sb2Te3 with N-doping (ST N),

AgInSbTe (silver-indium-antimony-tellurium)

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FIGURE 4: PERIODIC TABLE-

CHALCOGENIDES



Pr inciple

These materials can var y between two states:

± Crystalline ±

low resistance (1-10k) >> represents binar y 0

± Amorphous ±

high resistance (>1M) >> represents binar y 1

This phase change is induced in the material

through intense localized Joule heating caused bycurrent injection

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FIGURE 5: AMORPHOUS AND POLYCRYSTALLINE



Pr inciple_wr iting

Joule heating

The programming pulse drives the memor y cell into a highor low resistance state( phase transition process), depending on current magnitude.

There are two different currents used to write to the device. A small current used to change the device from a 0 to a 1.

(set).The small current raises the temperature a bove the cr ystallization temp and below melting temp so that it iscr ystallized.

A larger current is used to change the state from a 1 to a 0(reset). This is done by melting the cr ystalline state and quickly cooling it to leave it in the amorphous state.

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Figure 6:SET PULSE AND RESET PULSE

Ta-amorphization temperature ~610 C

Tx-crystallization temperature ~

Figure 7:current-voltage curve for PCM

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Wr iting

Set operation R eset operation

Melt quenching to mak e it

amorphous. Pulse of higher power but short

duration

To High resistance state

Logically stores 0. ~300 A , 1.6V

RESET dissipates 480 W for

40ns ~19.2 pJ.

Cr ystallizing the pcm.

Pulse of Moderate power but

long duration

To Low resistance state

Logically stores 1

~150 A ,1.2V. A SET dissipates 90 W for

150ns ~13.5 pJ.

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Reading

Information stored in the cell is read

out by measurement of the cell¶s resistance.

In read mode, verif ying

the cell resistance is accomplished at a

Voltage < V th, typically 0.4 V ,

Prior to reading, bit line is precharged to read voltage.

If selected cell is in cr ystalline state the bit line isdischarged with current f lowing through storage element and access transistor .

If it is in amorphous state then the bitline current is prevented or limited.

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Figure 8:reading



Main f eatures

Bit alterable:Similar to RAM or EEPROM, PCM is bit-altera ble.

Unlik e Flash, PCM does not require a separate erase step.

Scalability:

Flash rely on f loating gate memor y structures, which are difficult to shrink. PCM does not store charge (electrons), it is immune to the charge storage scaling issues.Newtechnologies also allows stack ing of PCM

Density:

PCM offer s much higher density than that of DRAM The density of PCM is almost four times to that of DRAM.Hence more amount of information can be stored in a PCM,than that of a DRAM for a given size

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Main f eatures

Non-volatile:PCM is non-volatile.It does not require a constant power supply to retain information, while DRAM does.

R ead performance:

Similar to DRAM and NOR f lash memor y, PCM featuresfast random access times. This ena bles the execution of code directly from the memor y, without an intermediate copy to RAM.

Write/erase performance:

No separate erase step is required.So faster than Flash.

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Disadvantages

o Limited Lifetime:

The num ber of writes to a PCM is limited (a bout 10^9), afterwhichthe memor y cell begin to wear out. Due to the fact that the operation is temperature dependant.Expansion and contraction.

o H igh access latencies:PCM also suffer s from high access latencies compared to DRAM.Itis ~250 ns for PCM whereas 60 ns in case of DRAM

o H igh energy consumption:Though PCM enjoys the advantage of having almost zero leak age

power , it suffer s from higher dynamic power consumption. Thismainly supported by the fact that the read and write operations are temperature dependant.

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-Density similar to

NAND f lash&

-R ead latency similar to

NOR f lash Figure 10:comparison of different memory

technologies

Figure9:The typical access latency (in cycles, assuming a 4GHz machine) of different

memory technologies, and their relative place in the overall memory hierarchy.



PCM v/s FLASH

PCM performance

Fast

Low voltage (0.4-2 V)

Scaling: good

Medium endurance (~109)

Medium current (50-300 QA)

Energy ( pJ/switch)

lash performance

Slow

High voltage (10-15 V)

Scaling: bad

Short endurance (~105)

Low current (~ nA)

Energy (nJ/switch)

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MEMORY MODEL

FIGURE 11:MAIN MEMORY ORGANIZATIONS

(a)Traditional system (b)Aggressive system with f lash based disk cache

(c)System with PCM (d) System with hybrid memor y system

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Hybr id main memor y organization

The PCM storage is managed by the OS using a page ta ble, similar to current DRAM main memor y systems.

DRAM memor y acts as a buffer as well as an interface between the PCM and processor .

Techniques-

± lazy write organization,

± line level writes,

± fine grained wear levelling,

± page level by pass.

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Lazy-wr ite organization

Figure 12: lazy write organization

R educes the num ber

of writes to the PCM

Over comes the slow

write s peed of PCM. Write queue-serves as

a buffer

Size of 100 pages to

avoid stalls.

Tags of both the write

queue and the dram

buffer are made of SRAM

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Lazy-wr ite organization

The page fetched from HDD is written only to DRAM cache. At the time of page fetch, only s pace is allocated in PCM but the data is not written into PCM.

The dram tag is extended with a ³ presence´ bit (P)and a ³dirty bit´ (D).

When page from HDD is stored in dram cache P bit isset to 0.

If on a dram miss the page is loaded from pcm,then the P bit is set 1.

A page is written to pcm only when it is evicted from dram and the P bit is 0 or dirty bit is 1.

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Line Level Wr ites

Ty pically main memor y is read and written in pages.However endurance of pcm limits the write cycles.

So writing to PCM in smaller chunks instead of a whole page.

Line Level Write Back(LLWB)

± Only dirty lines within the page are written

To do so the tag director y is extended to hold a dirty bit for each line.

± Eg: For a system with page size of 4096 and line size of 256 we need 16 dirty bits per page in the DRAM tag

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Line Level Wr ites

So when a dirty page is evicted from DRAM,

± if the P bit is 1,only the dirty lines of the page are

written.Not the whole page.

± If the P bit is 0, whole page has to be written.

LLWB significantly reduces wasteful writes

from DRAM to PCM

Thus life of PCM is improved and also

processor time is saved

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Fine Grained Wear -Levelling

LLWB reduces the write traffic to PCM.

However if only some cache lines within a

page are written to frequently,they will wear

out sooner than other lines.

So writes need to be made uniform across all

lines of PCM.

For this we use fine grained wear levelling

technique.

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In FGWL, the lines in each page are stored in

the PCM in a rotated manner .

If the rotate value is 0, page is stored in traditional manner

If it is 1,then line 0 of the address s pace is

stored in line1 of physical PCM.

i.e, the pages are written from write queue to

PCM in a line shifted format.

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Figure:13

write traffic to different lines

without FGWL

Figure:14

Write traffic to different lines

with FGWL

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Page Level ByPass For Wr ite

Filter ing

Not all applications benefit from more memor ycapacity

± For eg: streaming applications.They have poor

reuse

Storing pages of such applications accelerateswear out of PCM.

So actual writing of such pages can be avoided by leveraging lazy write ar chitecture.

This is called Page Level By-Pass (PLB).

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Page Level ByPass For Wr ite

Filter ing

We assume that the OS ena bles/disa bles PLB

for each application using a configuration bit.

If this PLB bit is turned ON,all pages of that application by passes the PCM storage.

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Impact of using these techniques

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Figure 15: Avg. No.Of

bytes per cycle and

avg.Lifetime of different

configurations

Figure 16:comparison of dram

pcm and hybrid

model



Summar y Phase Change Memor y (PCM), promises much higher density

than DRAM and can increase the main memor y capacity

su bstantially. However , PCM comes with the draw back of

increased access latency and limited num ber of writes.

As PCM is slower than DRAM, it can be used in conjunction

with a DRAM buffer . A small DRAM buffer (3% the size of PCM storage) can bridge the latency gap between PCM and

DRAM.

Three techniques: Lazy Write, LLWB, and PLB to reduce the

write traffic to PCM.These simple techniques can reduce the write traffic by 3X and increase the average lifetime of PCM

from 3 year s to 9.7 year s.

Fine Grained Wear Leveling (FGWL), a simple technique to

mak e the wear-out of PCM storage uniform across all lines in

a page. 29



Ref erences [1] Moinuddin K . Qureshi Vijayalakshmi Srinivasan Jude A. R iver s,

³Scalable High Performance Main Memory System Using Phase-Change Memory Technology´,978-1-60558-526-0/09/06(2009)

[2]Wong,H.S.P;sang bum k im;byoungil lee;Caldwell,M.A;Jiale Liang;YiWu ; Jeyasingh,R.G.D;Shimyeng Yu, ³ Recent progress of phase change

memory (pcm) and resistive switching random access memory(RRAM)´,IEEE 10.1109/ICSICT.2010.5667542 2010,Page(s):1055-1060

[3] The Basics of Phase Change Memor y Technology.http://www.numonyx.com/Documents/WhitePaper s/ PCM_ Basics _ WP. pdf .

[4] International Technology Roadmap for Semiconductors,ITRS 2007 .

[5] F. Bedeschil et al. A multi-level-cell bipolar-selected phase-change memor y. In 2008 IEEE International Solid-State Circuits Conference,

pages 428 ± 430, Fe b. 2008.

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