phase change memory - nvmw.eng.ucsd.edu

Phase Change Memory: Development Progress and System Opportunities

Greg AtwoodNumonyx Sr. FellowCorporate Technology Office

#2

Outline

Motivation for Phase Change Memory

Technology Status

Development Directions

System Opportunities

#3

Memory Consideration:Past, Present, and Future

“New Memory” Motivation (Recognized ~1999) :– Current NVM (and DRAM) are becoming Electrostatics Limited– Starting to Encounter Physical Scaling Limitations– Manifesting First as Degradation in Reliability (Endurance/Retention)

Realization:– Next Generation NVM will Exploit New Storage Physics– Significant Innovation Will take Time (History says ~10yr “Gestation”)

Response:– Phase Change Memory Identified as the Best Candidate– Research Efforts Validated Assumptions and Initiated Development– Phase Change Memory Moving into Production Today

PCM Features Will Enable New Usage Models Approaching the Goals of “Storage Class Memory”

#4

NAND Scaling Challenges

Reducing Cell Capacitance Results in Fewer Stored

Electrons with Scaling – Effect Magnified with MLC

Degrading Reliability Results in Increased Usage of Error Correction – More System

Management Required

SLC R/W

NAND Electron Scaling

20122011

20102009

2008

2007

2006

2004

10

100

1000

10000

20406080100

Litho Node

# E

lect

rons

SingleBit/Cell

0

5

10

15

20

25

30

0

20

40

60

80

100

120

90 70 60 50 40 30 20Lithography (nm)

# of

EC

C B

its

R/W

Cyc

les

(k)

Cycles/ECC vs NAND Litho

SLC R/W

MLC R/W

SLC ECC

MLC ECC

0

5

10

15

20

25

30

0

20

40

60

80

100

120

90 70 60 50 40 30 20Lithography (nm)

# of

EC

C B

its

R/W

Cyc

les

(k)

Cycles/ECC vs NAND Litho

SLC R/W

MLC R/W

SLC ECC

MLC ECC

#5

DRAM Scaling Challenges

Major Changes Required

New Periphery Transistor Every Gen

Frequent Capacitor Structure and Material Changes with Highest “known” HiK Material at ~32nm Generation

New Cell Transistor Every Generation

#6

Phase Chang Memory Key Attributes

105 -106

200-200 ns

13-30

KB/s

~Flash

Easy

No

Small/Byte

Yes

EEPROM

NoYesYesNoErase

20 - 80 ns15 - 50 us70-100 ns50 - 100 nsRead Latency

100+

MB/s

10+

MB/s

0.5-2

MB/s

1- 15+

MB/sWrite

Bandwidth

EasyHardModerateEasySoftware

High~Flash~Flash~FlashPower

Small/ByteLargeLargeSmall/ByteGranularity

NoYesYesYesNon-Volatile

104-5

NAND

Unlimited

DRAM

105

NOR

106+Endurance

PCMAttribute

PCM provides an new set of features combining components of NVM with DRAM

#7

Outline


Technology Status



#8

Phase Change Material Properties

amorph fcc hexagonal

XRD-measurements

M.Wuttig et al., RWTH Aachen FP6 Project CAMELS

Certain alloys containing one/more group VI elements (chalcogenides) exhibit reversible transition between the disordered (amorphous) and ordered (crystalline) atomic structure

Ge2Sb2Te5

#9

Phase Change Memory Mechanisms

Storage– GST: Germanium-Antimony-Tellurium

Chalcogenide glass

– Cell states varying from amorphous (high resistance) to crystalline (low resistance) states

Read Operation– Measure resistance of the GST

Write Operation– Heat GST via current flow (Joule effect)

– Time at critical temperature determines cell state

Crystalline Amorphous

Time

Tx

Tm

Reset (amorphization)

Set (crystallization)

TimeTem

pera

ture

Tx

TmReset (amorphization)

Set (crystallization)

I

V

I

VTemperature during write

0.0 0.5 1.0 1.50.00

0.25

0.50

0.75

Vth

Crystal Amorphous

Cur

rent

[mA

]

Voltage [V]

Read

Write

#10

BJT-PCM Cell and Array Construction

Chalcogenide

n-array

p+

n-array

p+

n-array

p+

Bitline (Metal 0)

Wordline(Metal 1)

B-B’ cross section

A A’

B

B’

Basic layout

BaseContact

EmitterContact

A-A’ cross section

Wordline

Chal

Bitline

Chal

Bitline

n+n+

Chal

Bitline

Chal

Bitline

N - Base

P – SubstrateCollector

PEmitter

PEmitter

PEmitter

PEmitter

4F2 Basic Cell, 5.5F2 Including Base Contacts

#11

PCM Technology Roadmap

20072005 2009

Numonyx

PCM Roadmap

#12

Summary of Key PCM Reliability Metrics

Retention decoupled from endurance

P/E Cycles

Ret

entio

nT

ime

PCM

NAND

No issue with Read disturb

P/E Cycles

Rea

d

End

uran

ce PCM

NAND

Result:

Greatly simplified management

No software overhead for some apps

Post-stress shelf-life problem solved

Endurance can be increased significantly through management of bit errors

Data is stable once successfully writtenP/E Cycles

Writ

e E

rror

R

ate

PCM

NAND

Wearout is Well Behaved

#13

PCM Reliability Data – 90nm 128Mb

0.01

0.1

1

10 100 1000 10000 100000

Prior Write Cycles

Nor

mal

ized

Cel

l Fai

ls A

fter B

ake Retention/Endurance

Independence

0.01

0.1

1

10 100 1000 10000 100000

Prior Write Cycles

Nor

mal

ized

Cel

l Fai

ls A

fter B

ake Retention/Endurance

Independence

Lot #

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1 2 3 4 5 6 7 8 9 1

0

1

1

1

2

1

3

1

4

1

5

1

6

1

7

1

8

Goal

Cel

l Fai

ls

Data Retention

Lot #

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1 2 3 4 5 6 7 8 9 1

0

1

1

1

2

1

3

1

4

1

5

1

6

1

7

1

8

Goal

Cel

l Fai

ls

Lot #

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1 2 3 4 5 6 7 8 9 1

0

1

1

1

2

1

3

1

4

1

5

1

6

1

7

1

8

Goal

Cel

l Fai

ls

Data Retention

Each Point is the average of ~200die

(log)

10x – 100x Margin to Goal

Lot #

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1 2 3 4 5 6 7 8 9 1

0

1

1

1

2

1

3

1

4

1

5

1

6

1

7

1

8

Goal

Cel

l Fai

ls

Data Retention

Lot #

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1 2 3 4 5 6 7 8 9 1

0

1

1

1

2

1

3

1

4

1

5

1

6

1

7

1

8

Goal

Cel

l Fai

ls

Lot #

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1 2 3 4 5 6 7 8 9 1

0

1

1

1

2

1

3

1

4

1

5

1

6

1

7

1

8

Goal

Cel

l Fai

ls

Data Retention


Lot #

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1 2 3 4 5 6 7 8 9 1

0

1

1

1

2

1

3

1

4

1

5

1

6

1

7

1

8

Goal

Cel

l Fai

ls

Data Retention

Lot #

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1 2 3 4 5 6 7 8 9 1

0

1

1

1

2

1

3

1

4

1

5

1

6

1

7

1

8

Goal

Cel

l Fai

ls

Lot #

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1 2 3 4 5 6 7 8 9 1

0

1

1

1

2

1

3

1

4

1

5

1

6

1

7

1

8

Goal

Cel

l Fai

ls

Data Retention

Lot #

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1 2 3 4 5 6 7 8 9 1

0

1

1

1

2

1

3

1

4

1

5

1

6

1

7

1

8

Goal

Cel

l Fai

ls

Data Retention

Lot #

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1 2 3 4 5 6 7 8 9 1

0

1

1

1

2

1

3

1

4

1

5

1

6

1

7

1

8

Goal

Cel

l Fai

ls

Lot #

1.E-04

1.E-03

1.E-02

1.E-01

1.E+00

1 2 3 4 5 6 7 8 9 1

0

1

1

1

2

1

3

1

4

1

5

1

6

1

7

1

8

Goal

Cel

l Fai

ls

Data Retention


(log)

10x – 100x Margin to Goal

1Mc Endurance

0

20

40

60

80

100

1 2 3 4 5Lot #

% U

nits

pas

sing

Process + Programmingoptimization

Each Point represents ~30die

Improvements due to Process and Programming

Optimization

1Mc Endurance

0

20

40

60

80

100

1 2 3 4 5Lot #

% U

nits

pas

sing



1Mc Endurance

0

20

40

60

80

100

1 2 3 4 5Lot #

% U

nits

pas

sing



Improvements due to Process and Programming

Optimization

Cell Current

Dis

trib

utio

n #

Sig

ma

Array DistributionReset Set

Cell Current

Dis

trib

utio

n #

Sig

ma

Array DistributionReset Set

128M

b V

ehic

le12

8Mb

Veh

icle

DiePhoto

128M

b V

ehic

le12

8Mb

Veh

icle

DiePhoto

0

20

40

60

80

100

1.E+05 1.E+06 1.E+07 1.E+08 1.E+09

Writes

% P

assi

ng U

nits

100Mc FeasibilitySmall Sample

0

20

40

60

80

100

1.E+05 1.E+06 1.E+07 1.E+08 1.E+09

Writes

% P

assi

ng U

nits

100Mc FeasibilitySmall Sample

#14

Outline


Technology Status



#15

45nm Technology – 1Gb “Bonelli” Product

Process Architecture

PCM cell

– Salicided minimum-size BJT selector

– Self-aligned “Wall” Structure

– 1 Base Contact / 4 Emitter

– 0.015 µm2 cell size

CMOS periphery– Dual gate oxide (3nm for 1.8V and

8nm for 3V operation)

3 Cu levels for tight interconnects

#16

Scalability of PCM

Thermal Disturb Scales if Cell Geometry is Properly Scaled

Scaling of the “Wall” structure for the storage element and of the BJT for the selector

#17

CMOS SupportCircuitry

PCMS Array

3-d corner view of PCMS array

PCMS Cell


PCMS Array


PCMS Cell

Extending PCM into the 3rd DimensionResearch Program

Stacked Phase Change Memory– Same PCM memory concept

– Uses a diode (Ovonic Threshold Switch – OTS ) as select device

– OTS is the same class of materials as PCM - Calcogenide

OTS

Electrode

PCM

Electrode

OTS

Electrode

PCM

Electrode

OTS

Electrode

PCM

Electrode

Potential benefits– True cross point array -

4F2 cell

– Stackable n-layers for effective cell size of 4F2/n

– MLC NAND cost structure

– Performance of PCM

64Mb Array Distribution

64Mb Array Distribution

>1Mc Endurance Demonstrated>1Mc Endurance Demonstrated

#18


PCMS Array


PCMS Cell


PCMS Array


PCMS Cell

Numonyx PCM Development

Scaling the existing architecture, providing the smallest cell size, following the lithography roadmap

Introduction of Multi-Level-Cell exploiting the analog storage capability of PCM

Exploration of new chalcogenide alloys which may open new application fields

Exploitation of a true cross-point array which will allow vertical stacking of more than one memory layer

Ge or M (at %)

0 100

90

80

7060

5040

3020

100

1020

30

4050

6070

80

90100

60 70 80 90 10050403020100Sb (at %)Te (at %)

GeTe

Sb2Te3

GeSbTe(GST) Doped SbTe

Sb2Te

M-Sb2Te

DVD+RW

225

147

DVD+RAM

124

Mai

nstr

eam

D

evel

opm

ent

Ear

ly

Eva

luat

ions

Ong

oing

R

esea

rch

Pro

f of

Con

cept

R

esea

rch

Our Main Thrust

Expanding theEnvelope

Breakthrough Research

#19

Outline


Technology Status



#20

PCM Application Opportunities

Wireless System– Direct code execution, semi-static data and file storage�Bit alterability allows direct-write memory

Solid State Storage Subsystem– Frequently accessed pages and elements easily managed when

manipulated in place�Caching with PCM will improve performance and reliability

Computing Platforms– Taking advantage of non-volatility to reduce the power�PCM offers endurance and write latency that are compelling for a

number of novel solutions

#21

PCM in Computing Applications

– More latency improvement • PCM is to SSDs as SSDs are to HDDs

• How is it possible to increase performance?– Bandwidth improvement

– Latency improvement

#22

Memory Hierarchy in Servers & StorageWhere PCM can Fit

PCM enables improved endurance for logging applications

PCM replaces battery backed up RAM-cache at cabinet and rack levels

PCM improves reliability and performance in HDD / SSD’s

PCM for performance high IOPS, low latency

Servers

ClientsNetwork Attached Storage

Storage Area Networks

Network

Local and Remote Memory

Direct Attached Storage

Storage Controllers

CPU RAM DISK TAPE

ns / GB ms / TB s / PB

SSD

us / GB

SCM

#23

Summary

Phase Change Memory (PCM) technology is demonstrating the capability to enter the broad memory market and to become a mainstream memory

PCM provides a new set of features interesting for novel applications, combining components of NVM and DRAM and being at the same time a sustaining and a disruptive technology

The technology maturity achieved, the scaling perspective and the broad application range allow predicting a key role for the PCM in the memory market for the next decade.

phase change memory - nvmw.eng.ucsd.edu

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