Penn ESE370 Fall2010 -- DeHon1

ESE370:Circuit-Level

Modeling, Design, and Optimization for Digital Systems

Day 10: September 29, 2010

MOS Transistors Details

Last Time• Focused on I vs V relationships

– Effective resistance– Drive

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Today

• Capacitance– Gate– Source/Drain Contact

• More threshold dependence– VDS

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Theme

• Refining model– Exploring next level of complexity

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channel

gate

srcdrain

Capacitance

• First order: looks like a capacitor

• Today: – Like resistance, it is not constant– Capacitance not just to src (drain)

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Threshold

• Threshold decreases with VDS

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VT

VDS

Capacitance Setup

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Capacitance

• Argued looked like a capacitor to the channel

• …but the channel isn’t really one of our terminals– Don’t connect directly to it.

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Capacitance

• Four Terminals

• How many combinations– 4 things taken 2 at a time

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Capacitances

• GS, GB, GD, SB, DB, SD

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Moving Plates?

• What is distance from gate to conductor?– Depletion?– Strong Inversion?

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Capacitance Decomposition

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Overlap

• What is the capacitive implication of gate/src and gate/drain overlap?

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Overlap

• Length of overlap?

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Overlap Capacitance

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€

C = ε rε 0

A

d

€

Co = ε ox

W Ldrawn−Leffective( ) /2

tox

Overlap Capacitance

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€

C = ε rε 0

A

d

€

COX =εOX

tOX

€

Co = ε ox

W Ldrawn−Leffective( ) /2

tox

€

Co = CoxW Ldrawn−Leffective( ) /2

Capacitance in Strong Inversion(easy case)

• Looks like parallel plate Gate – Channel– What is CGC?

– What is CGB?

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Capacitance in Strong Inversion

• Looks like parallel plate Gate – Channel– What is CGC?

– CGB=0

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€

CGC = CoxWLeffective

Capacitance in Strong Inversion

• But channel isn’t a terminal– Split evenly with source and drain

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€

CGCS = CGCD = 0.5CoxWLeffective

€

CGC = CoxWLeffective

Capacitance in Strong Inversion

• Add in Overlap capacitance

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€

CGCS = CGCD = 0.5CoxWLeffective

€

CGS = CGSC +CO = 0.5CoxWLdrawn

€

Co = CoxW Ldrawn−Leffective( ) /2

Capacitance Subthreshold

• Need to refine model– What showed on Day 9 not quite right

• Channel doesn’t start depleted– Starts with substrate doping

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Channel Evolution Subthreshold

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Capacitance Depletion

• What happens to capacitance here?– Capacitor plate distance?

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Capacitance Depletion

• Capacitance becomes Gate-Body

• Capacitance drops

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Capacitance vs VGS

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• G CGC

CGCS=CGCD

CGCB

Saturation Capacitance?

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Saturation Capacitance?

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• Source end of channel in inversion

• Destination end of channel close at threshold

• Capacitance shifts to source– Total capacitance reduced

Saturation Capacitance

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CGC

CGCS

CGCD

VDS/(VGS-VT)

Contact Capacitance

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Contact Capacitance

• n+ contacts are formed by doping = diffusion

• Depletion under contact– Contact-Body capacitance

• Depletion around perimeter of contact– Also contact-Body capacitance

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Contact/Diffusion Capacitance

• Cj – diffusion depletion

• Cjsw – sidewall capacitance

• LS – length of diffusion

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€

Cdiff = C jLSW +C jsw 2LS +W( )

LS

Capacitance Roundup

• CGS=CGCS+CO

• CGD=CGCD+CO

• CGB=CGCB

• CSB=Cdiff

• CDB=Cdiff

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One Implication

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Step Response?

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Rsmall

Rlarge

Step Response

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Impact of CGD

• What does CGD do to the switching response here?

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Impact of CGD

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Threshold

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Threshold

• Describe VT as a constant

• Induce enough electron collection to invert channel

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VDS impact

• In practice, VDS impacts state of channel

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VDS impact

• Increasing VDS, already depletes portions of channel

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VDS impact

• Increasing VDS, already depletes portions of channel

• Need less charge, less voltage to invert

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Drain-Induced Barrier Lowering (DIBL)

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VT

VDS

DIBL Impact

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In a Gate?

• What does it impact most?– Which device, which state/operation?

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In a Gate

• VDS largest for off device

– Easier to turn on

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€

IDS = μnCOX

W

L

⎛

⎝ ⎜

⎞

⎠ ⎟ VGS −VT( )VDS −

VDS2

2

⎡

⎣ ⎢

⎤

⎦ ⎥

In a Gate

• VDS largest for off device

– Easier to turn on– Leak more

Penn ESE370 Fall2010 -- DeHon47

€

IDS = μnCOX

W

L

⎛

⎝ ⎜

⎞

⎠ ⎟ VGS −VT( )VDS −

VDS2

2

⎡

⎣ ⎢

⎤

⎦ ⎥

€

IDS = ISW

L

⎛

⎝ ⎜

⎞

⎠ ⎟e

VGS

nkT / q

⎛

⎝ ⎜

⎞

⎠ ⎟1− e−

VDS

kT / q

⎛

⎝ ⎜

⎞

⎠ ⎟

⎛

⎝ ⎜

⎞

⎠ ⎟1+ λVDS( )

In a Gate

• VDS largest for off device

– Easier to turn on– Leak more

Penn ESE370 Fall2010 -- DeHon48

€

IDS = ISW

L

⎛

⎝ ⎜

⎞

⎠ ⎟e

VGS

nkT / q

⎛

⎝ ⎜

⎞

⎠ ⎟1− e−

VDS

kT / q

⎛

⎝ ⎜

⎞

⎠ ⎟

⎛

⎝ ⎜

⎞

⎠ ⎟1+ λVDS( )

€

IDS = IS′W

L

⎛

⎝ ⎜

⎞

⎠ ⎟e

VGS −VT

nkT / q

⎛

⎝ ⎜

⎞

⎠ ⎟1 − e−

VDS

kT / q

⎛

⎝ ⎜

⎞

⎠ ⎟

⎛

⎝ ⎜

⎞

⎠ ⎟1+ λVDS( )

Admin

• HW3 due Friday

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Ideas

• Capacitance– To every terminal– Voltage dependent

• Threshold– Voltage dependent

• Generally do manual analysis without

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VT

VDS

CGC

CGCS

CGCB