penn ese370 fall 2011 -- townley & dehon ese370: circuit-level modeling, design, and...

Penn ESE370 Fall 2011 -- Townley & DeHon

ESE370:Circuit-Level

Modeling, Design, and Optimization for Digital Systems

Day 13: October 5, 2011

Layout and Area

2

Today

• Layout– Transistors– Gates

• Design rules

• Standard cells


3

Transistor

Side view

Perspective view


4

Layout

• Sizing & positioning of transistors

• Designer controls W,L

• tox fixed for process– Sometimes

thick/thin oxide “flavors”


5

NMOS Geometry

Top view Perspective view

L

W


6

NMOS Geometry

Top view

L

W

• Color scheme– Red: gate– Green: source and drain

areas (n type diffusion)S DG


7

tox

• Transistors built by depositing materials– Constant rate of deposition (nm/min)– Time controls tox

• Oxides across entire chip deposited at same time– Same time interval– thickness is (roughly) constant– Process engineer sets value to:

• Assure yield• What does tox control?

– Field strength Vth, current– Achieve Performance, minimize leakage


8

NMOS vs PMOS

Rabaey text, Fig 2.1Penn ESE370 Fall 2011 -- Townley & DeHon

• Mostly talked about NMOS so far– PMOS: “opposite” in some sense– NMOS built on p substrate, PMOS built on n

substrate– Name refers to bias/carriers when channel is

inverted

9

PMOS Geometry

n well

L

W

• Color scheme– Red: gate– Orange: source and drain

areas (p type)– Green: n well

• NMOS built on p wafer– Must add n material to

build PMOS

S DG


10

Body Contact

• “Fourth terminal”• Needed to set

voltage around device– PMOS: Vb = Vdd

– NMOS: Vb = GND

• At right: PMOS (orange) with body contact (dark green)



From: http://www.bioee.ee.columbia.edu/courses/cad/html/layout.html

Rotate All butPMOS Transistor90 degrees

12

Interconnect

• How to connect transistors– Different layers of metal Intermediate

layers• “Contact” - metal to transistor• “Via” - metal to metal

Rabaey text, Fig 2.7kPenn ESE370 Fall 2011 -- Townley & DeHon

13

Interconnect Cross Section

ITRS 2007Penn ESE370 Fall 2011 -- Townley & DeHon

14

Masks

• Define areas want to see in layer– Think of “stencil” for material deposition

• Use photoresist (PR) to form the “stencil”– Expose PR through mask– PR dissolves in exposed area– Material is deposited

• Only “sticks” in area w/ dissolved PR


15

Masking Process

• Goal: draw a shape on the substrate– Simplest example: draw a rectangle

Silicon wafer

Mask


16

Masking Process

• First: deposit photoresist

photoresist

Mask

Silicon wafer


17

Masking Process

• Expose through mask– UV light


18

Masking Process• Remove mask and

develop PR– Exposed area

dissolves– This is “positive

photoresist”


19

Masking Process• Deposit metal through PR

window– Then dissolve remaining PR

• Why not just use mask?– Masks are expensive– Shine light through mask to

etch PR– Can reuse mask


20

Logic Gates

• How to build compete inverter?– Connect NMOS,

PMOS using metal

• HW4, part 6: reverse engineer layouts into gates


21

Inverter Layout Example


22


• Start with PMOS, NMOS transistors

• Space for interconnect


23



24


• Add body contacts

• Connect gates of transistors


25



26


• Add contacts to source, drain, gate, body

• Connect using metal (blue)


27

Design Rules• Why not adjacent

transistors?– Plenty of empty

space– If area is money,

pack in as much as possible

• Recall: processing imprecise– Margin of error for

process variation


28

Design Rules• Contract between process engineer &

designer– Minimum width/spacing– Can be (often are) process specific

• Lambda rules: scalable design rules– In terms of = 0.5 Lmin (Ldrawn)– Can migrate designs from similar process– Limited scope: 45nm process != 1m


Design Rules: Some Examples


2

66

3

2

2

1.5

n doping

p doping

gate

contact

metal 1

metal 2

via

Legend

30

Layout Revisited

• How to “decode” circuit from layout?


Penn ESE370 Fall2010 -- DeHon31

Layout to Circuit

• 1. Identify transistors


32

Layout to Circuit

• 2. Add wires


33

Layout to Circuit

• 2. Add wires

Penn ESE370 Fall 2010 -- Townley (DeHon)Penn ESE370 Fall 2011 -- Townley & DeHon

34

Layout to Circuit

• 2. Add wires


35

Layout to Circuit

• 2. Add wires


36

Layout #2 (practice)


37

Layout #2 (practice)

• How many transistors?– PMOS?– NMOS?

• How connected?– PMOS, NMOS?

• Inputs connected?• Outputs?• What is it?


38

Standard Cells• Lay out gates so that heights match

– Rows of adjacent cells– Standardized sizes

• Motivation: automated place and route– EDA tools convert HDL to layout



Standard Cell Area

inv nand3

All cellsuniformheight

Width ofchanneldeterminedby routing

Cell area

Identify the full custom and standard cell regions on 386DX diehttp://microscope.fsu.edu/chipshots/intel/386dxlarge.html

http://microscope.fsu.edu/chipshots/intel/386dxlarge.html

Admin

• HW4 due Friday

• Exam next Wednesday– No class at noon that day


Exam

• Function from CMOS circuit

• CMOS circuit to implement function

• Restoration / Noise Margins– Potentially including MOS equations– Might include variation

• CMOS gate switching delay


42

Big Idea

• Layouts are physical realization of circuit– Geometry tradeoff

• Can decrease spacing at the cost of yield• Design rules

• Can go from circuit to layout or layout to circuit by inspection


penn ese370 fall 2011 -- townley & dehon ese370: circuit-level modeling, design, and...

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