multichannel buffered serial port - people@rset

Multichannel Buffered Serial Port

McBSP

Features

The McBSP provides these functions:

Full-duplex communication.

Double-buffered data registers, which allow a continuousdata stream.

Independent framing and clocking for receive andtransmit.

Direct interface to industry-standard codecs, analoginterface chips (AICs), and other serially connectedanalog-to-digital (A/D) and digital-to-analog (D/A)devices.

External shift clock or an internal, programmablefrequency shift clock for data transfer.

Features

Multichannel transmit and receive of up to 128 channels

A wide selection of data sizes, including 8, 12, 16, 20, 24,

and 32 bits

µ-Law and A-Law companding

8-bit data transfers with the option of LSB or MSB first

Programmable polarity for both frame synchronization

and data clocks

Highly programmable internal clock and frame

generation.

McBSP Interface Signals and

Registers

The multichannel buffered serial port (McBSP) consists ofa data path and a control path, which connect to externaldevices.

Data is communicated to these external devices viaseparate pins for transmission and reception.

Control information (clocking and frame synchronization)is communicated via four other pins.

The device communicates to the McBSP via 32-bit-widecontrol registers accessible via the internal peripheral bus.

TMS320C671x Peripherals

McBSP Block Diagram

McBSP Interface Signals

Data is communicated via the data transmit (DX) pin for

transmission and the data receive (DR) pin for reception.

Control information (clocking and frame synchronization) is

communicated via CLKX, CLKR, FSX, and FSR.

The C6000 communicates to the McBSP via 32-bit-wide

control registers accessible via the internal peripheral bus.

McBSP Interface Signals

Either the CPU or the EDMA controller reads the receiveddata from the data receive register (DRR) and writes the datato be transmitted to the data transmit register (DXR).

Data written to the DXR is shifted out to DX via the transmitshift register (XSR).

Similarly, receive data on the DR pin is shifted into thereceive shift register (RSR) and copied into the receivebuffer register (RBR). RBR is then copied to DRR, whichcan be read by the CPU or the EDMA controller. This allowssimultaneous internal data movement and external datacommunications.

McBSP Registers

TMS320C671x Data Receive and Transmit

Registers (DRR/DXR) Mapping:

For devices with the EDMA peripheral, the data receive andtransmit registers (DRR and DXR) are also mapped tomemory locations 3xxxxxxxh. The DRR and DXR locations018Cxxxxh/0190xxxxh are accessible via the peripheral bus,while the 3xxxxxxxh locations are accessible via the EDMAbus.

Both the CPU and the EDMA in these devices can access theDRR and DXR in all the memory-mapped locations shown inTable. An access to any EDMA bus location is equivalent toan access to the DRR/DXR of the corresponding McBSP.



For example, a read from any location in 30000000h–

33FFFFFFh is equivalent to a read from the DRR of

McBSP0 at 018C0000h. A write to any location in

30000000h–33FFFFFFh is equivalent to a write to the

DXR of McBSP0 at 018C0004h.

The user has a choice of reading from/writing to the DRR

and DXR in either the 3xxxxxxxh or the

018Cxxxxh/0190xxxxh location.

McBSP CPU Interrupts and DMA

Synchronization Events

The control block consists of internal clock generation,

frame-synchronization signal generation and control of these

signals, and multichannel selection.

This control block sends notification of important interrupts

to the CPU and events to the EDMA controller via the four

signals shown in Table.

Serial Port Configuration

The serial port is configured via the serial portcontrol register (SPCR) and the pin controlregister (PCR).

The SPCR and PCR contain McBSP status controlbits.

The PCR is also used to configure the serial portpins as general purpose inputs or outputs duringreceiver and/or transmitter reset.

Serial Port Control Register

Details

Serial Port Control Register (SPCR):

SPCR Field Descriptions:

Serial Port Control Register

Details Cont..

Pin Control Register (PCR):

PCR Field Descriptions Cont..

Serial Port Control Registers

Receive Control Register (RCR):

RCR Field Descriptions

Serial Port Control Registers

Transmit Control Register (XCR):

XCR Field Descriptions

McBSP Standard Operation

Operation:

The receive operation is triple-buffered and the

transmit operation is double-buffered.

Transmitting Data:

DXR XSR DX

Receiving Data:

DR RSR RBR DRR


Determining Ready Status:

RRDY and XRDY indicate the ready state of the McBSP

receiver and transmitter, respectively.

Writes and reads from the serial port can be synchronized

by any of the following methods:

Polling RRDY and XRDY

Using the events sent to the DMA or EDMA controller (REVT

and XEVT)

Using the interrupts to the CPU (RINT and XINT) that the events

generate.


Receive Operation:

Once the receive frame synchronization signal (FSR) transitions toits active state, it is detected on the first falling edge of the receiver’sCLKR.

The data on the DR pin is then shifted into the receive shift register(RSR) after the appropriate data delay as set by RDATDLY.

The contents of RSR is copied to RBR at the end of every elementon the rising edge of the clock, provided RBR is not full with theprevious data.

Then, an RBR-to-DRR copy activates the RRDY status bit to 1 onthe following falling edge of CLKR. This indicates that the receivedata register (DRR) is ready with the data to be read by the CPU orthe DMA controller.

RRDY is deactivated when the DRR is read by the CPU or theDMA controller.

Receive Operation Cont..

Receive Timing Diagram:


Transmit Operation:

Once transmit frame synchronization occurs, the valuein the transmit shift register, XSR, is shifted out anddriven on the DX pin after the appropriate data delay asset by XDATDLY.

XRDY is activated after every DXR-to-XSR copy onthe following falling edge of CLKX, indicating that thedata transmit register (DXR) can be written with thenext data to be transmitted.

XRDY is deactivated when the DXR is written by theCPU or the DMA controller.

Transmit Operation Cont..

Transmitter Timing Diagram:

Multiphase Frame Example: AC97

The Audio Codec ’97 (AC97) standard, which uses the dual-

phase frame feature. The first phase consists of a single 16-bit

element. The second phase consists of 12 20-bit elements. The

phases are configured as follows:

Multiphase Frame Example: AC97

DSP LAB - McBSP Interfacing

6713 DSK

AIC23 CODEC INTERFACING

The DSP interfaces to analog audio signals throughan on-board AIC23 codec.

The codec samples analog signals on themicrophone or line inputs and converts them intodigital data so it can be processed by the DSP.When the DSP is finished with the data it uses thecodec to convert the samples back into analogsignals on the line and headphone outputs so theuser can hear the output.

AIC23CODEC INTERFACING Cont..

The codec communicates using two serial channels, one tocontrol the codec’s internal configuration registers and oneto send and receive digital audio samples. McBSP0 is usedas the unidirectional control channel.

It should be programmed to send a 16-bit control word tothe AIC23 in SPI format.

McBSP1 is used as the bi-directional data channel.

The DSK generally use a 16-bit sample width with thecodec in master mode.

The preferred serial format is DSP mode which is designedspecifically to operate with the McBSP ports on TI DSPs.

TMS320C6713 DSK CODEC INTERFACE

AIC23 Codec

The TLV320AIC23 is a high-performance stereo

audio codec.

Data-transfer word lengths of 16, 20, 24, and 32

bits, with sample rates from 8 kHz to 96 kHz, are

supported.

The codec has a 12MHz system clock.

The internal sample rate generate subdivides the

12MHz clock to generate common frequencies such

as 48KHz, 44.1KHz and 8KHz.

Interfacing Signals

Modes of Communication

SPI Mode : The control interface. In SPI mode, SDIN carries the serial data, SCLK is the

serial clock and CS latches the data word into theTLV320AIC23.

A control word consists of 16 bits, starting with theMSB. The data bits are latched on the rising edge ofSCLK. A rising edge on CS after the 16th rising clockedge latches the data word into the AIC .

The control word is divided into two parts. The firstpart is the address block, the second part is the datablock: B[15:9] Control Address Bits

B[8:0] Control Data Bits

SPI Protocol: CLKSTP

SPIE protocol is a 4-wire interface composed of serial data in (master in slave out orMISO),

serial data out (master out slave in or MOSI),

shift clock (SCK),

active (low) slave enable (SS) signal.

Communication between the master and the slave isdetermined by the presence or absence of the master clock.Data transfer is initiated by the detection of the masterclock and is terminated on absence of the master clock.The slave has to be enabled during this period of transfer.

When the McBSP is the master, the slave enable is derivedfrom the master transmit frame sync pulse, FSX.

SPI Protocol: CLKSTP

SPI Configuration: McBSP as the Master

SPI Configuration: McBSP as the Slave

Modes of Communication Cont..

DSP mode: Digital Audio-Interface Mode

The DSP mode is compatible with the McBSP ports of

TI DSPs.

LRCIN and LRCOUT must be connected to the Frame

Sync signal of the McBSP. A falling edge on LRCIN or

LRCOUT starts the data transfer.

The left-channel data consists of the first data word,

which is immediately followed by the right channel

data word.

Input word length is defined by the IWL register.

AIC23 Register Map

Codec Control Registers

Codec Control Registers Cont..

Sample Rate Control

Codec Connection Diagram

McBSP Control Register Values

void mcbsp0_init()

{

*(unsigned volatile int*)MCBSP0_SPCR = 0;

*(unsigned volatile int*)MCBSP0_PCR=0x00000A0A;

*(unsigned volatile int*)MCBSP0_RCR=0;

*(unsigned volatile int*)MCBSP0_XCR=0x00010040;

*(unsigned volatile int*)MCBSP0_SPCR=0x00C11001;

*(unsigned volatile int*)MCBSP0_SRGR=0x10001999;

}

void mcbsp1_init()

{

*(unsigned volatile int*)MCBSP1_SPCR = 0;

*(unsigned volatile int*)MCBSP1_PCR=0x00000003;

*(unsigned volatile int*)MCBSP1_RCR=0x00000140;

*(unsigned volatile int*)MCBSP1_XCR=0x00000140;

*(unsigned volatile int*)MCBSP1_SPCR=0x00C10001;

}

DSK6713_AIC23_Config config = {\ 0x0017, /* 0 DSK6713_AIC23_LEFTINVOL Leftline input channel

volume */\ 0x0017, /* 1 DSK6713_AIC23_RIGHTINVOL Right line input channel

volume*/\ 0x00d8, /* 2 DSK6713_AIC23_LEFTHPVOL Left channel

headphone volume */\ 0x00d8, /* 3 DSK6713_AIC23_RIGHTHPVOL Right channel

headphone volume */\ 0x0011, /* 4 DSK6713_AIC23_ANAPATH Analog audio path

control */\ 0x0000, /* 5 DSK6713_AIC23_DIGPATH Digital audio path control

*/\ 0x0000, /* 6 DSK6713_AIC23_POWERDOWN Power down control

*/\ 0x0043, /* 7 DSK6713_AIC23_DIGIF Digital audio interface format

*/\ 0x0081, /* 8 DSK6713_AIC23_SAMPLERATE Sample rate control */\ 0x0001 /* 9 DSK6713_AIC23_DIGACT Digital interface activation */

\ };

Serial Port Control Register..

Sample Rate Generator Register (SRGR):

SRGR Field Descriptions Cont..

multichannel buffered serial port - people@rset

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