m.s. february 25, 2013 1 1 1 ultimate-2 sensors preliminary summary of lbl probe test results...
DESCRIPTION
M.S. February 25, Yield and wafer map – U2 thick, std epi A01A02 B01B02B03B04B05B06 C01C02C03C04C05C06C07C08 D01D02D03D04D05D06D07D08 E01E02E03E04E05E06E07E08 F01F02F03F04F05F06F07F08 G01G02G03G04G05G06 H01H02 Wafer 501: Tested:29 good:931% bad:1552% (?):517% Physical damage Failed JTAG or power Failed probe tests ? Hot/cold pixel 1% OK noisy Low VCLP NOT TESTED Vref2 high Vref2 low Failed 160 MHz High VCLP High power Wire-bonded (power consumption – NA) A02 – ok at 3.3 V but cross-talk B02 – ok C06 – okTRANSCRIPT
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Ultimate-2 sensorspreliminary summary of LBL probe test results
• Introduction• Wafer maps:
1 STD epi, full thickness 5 high-res 2 DRIE
• Summary• Distribution of Noise/FPN• Additional slides
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Introduction• LBL probe testing procedure is currently used for testing and selecting sensors
for ladder construction for the prototype detector
• The yield that we have observed so far is satisfactory
• IPHC requested several sensors for additional analysis of sensor performance• 8 sensors were available at the time of the request• Mathieu discovered several issues with the sensors he tested
• What is the impact of the identified problems on our testing procedure and sensor selection?
Chip Probe testing results Issues identified at IPHC
E05 w 205 high vref2 stuck vclp
F05 w 205 good (3rd category)
B02 w 201 bad pixels >1%
B06 w 203 (?)
G02 w 204 noisy
A01 w 303 good high power consumption
B01 w 303 good corrupted frame structure
C01 w 303 hot pixels
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Yield and wafer map – U2 thick, std epi
A01 A02
B01 B02 B03 B04 B05 B06
C01 C02 C03 C04 C05 C06 C07 C08
D01 D02 D03 D04 D05 D06 D07 D08
E01 E02 E03 E04 E05 E06 E07 E08
F01 F02 F03 F04 F05 F06 F07 F08
G01 G02 G03 G04 G05 G06
H01 H02
Wafer 501:Tested: 29 • good: 9 31%• bad: 15 52%• (?): 5 17%
Physical damage
Failed JTAG or power
Failed probe tests
?
Hot/cold pixel <1%
Hot/cold pixel >1%
OK
noisy
Low VCLP
NOT TESTED
Vref2 high
Vref2 low
Failed 160 MHz
High VCLP
High power
Wire-bonded (power consumption – NA)• A02 – ok at 3.3 V but cross-talk• B02 – ok• C06 – ok
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Yield and wafer maps – wafer 201,202
x x
x 3 2 2 2 3
2 2 2 3 2 x 2 x
2 3 x 2 2 3 x 3
2 1 1 2 x 2 1 1
1 1 2 1 2 1 1 x
1 2 1 3 3 2
3 2
2 x
2 x 1 1 2 x
2 2 C03 1 2 2 C07 1
x 1 D03 2 2 2 1 x
2 E02 2 1 1 1 1 1
1 2 1 1 1 1 2 2
x 1 1 2 2 x
2 1
Physical damage
Failed JTAG or power
Failed probe tests
?
Hot/cold pixel <1%
Hot/cold pixel >1%
OK
noisy
Low VCLP
Vref2 high
Vref2 low
High VCLP
High power
Initial classification : colorsLadder selection criteria : numbers (grades) 1-3
Wafer 201:• grade 1 11• grade 2 19• grade 3 9• dummies 9
Wafer 202:• grade 1 19• grade 2 18• grade 3 0• dummies 7• other 4
grade 2 <1% bad pixels
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Yield and wafer maps – wafer 203,204
- -
- - - - - 3
- - - - - - 1 2
- - - - - - 1 1
- - - - - - - 2
2 - - 2 x 1 x 2
- - - - 1 1
H01 2
Wafer 203:• grade 1 6• grade 2 6• grade 3 1• dummies 2• other 1
Wafer 204:• grade 1 18• grade 2 7• grade 3 3• dummies 14• other 1
- -
1 x x 1 x 2
1 x x C04 2 1 1 x
2 1 2 1 1 2 1 1
1 1 - 1 1 x 1 x
2 1 3 1 - 3 1 x
x 3 x x x -
x 2
Physical damage
Failed JTAG or power
Failed probe tests
?
Hot/cold pixel <1%
Hot/cold pixel >1%
OK
noisy
Low VCLP
Vref2 high
Vref2 low
High VCLP
High power
grade 2 <1% bad pixels
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Yield and wafer maps – wafer 205
x x
1 1 x 2 x 1
x x 1 2 1 C06 1 2
x 1 2 1 1 2 1 1
x 1 2 1 3 1 2 1
x 1 1 1 3 x F07 2
2 1 1 x 1 2
2 3
Physical damage
Failed JTAG or power
Failed probe tests
?
Hot/cold pixel <1%
Hot/cold pixel >1%
OK
noisy
Low VCLP
Vref2 high
Vref2 low
High VCLP
High power
Wafer 205:• grade 1 21• grade 2 11• grade 3 3• dummies 11• other 2
grade 2 <1% bad pixels
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Yield and wafer maps – 2 DRIE wafers
A01 x
B01 B02 x B04 B05 B06
C01 x x - C05 C06 x C08
D01 D02 3 1 x 1 x 1
1 2 3 2 1 1 3 x
1 1 x 1 3 1 3 3
1 x G03 x x 3
2 3
Wafer 303:• grade 1 11• grade 2 3• grade 3 8• dummies 12• “skipped” 12
Wafer 304:• grade 1 19• grade 2 12• grade 3 6• dummies 11
x x
x 3 1 2 2 1
3 1 3 1 1 2 x x
1 1 2 1 2 1 2 x
1 1 2 1 1 2 1 2
1 x 2 1 3 1 1 x
x 2 1 3 3 x
2 x
Physical damage
Failed JTAG or power
Failed probe tests
?
Hot/cold pixel <1%
Hot/cold pixel >1%
OK
noisy
Low VCLP
Vref2 high
Vref2 low
Failed 160 MHz
High VCLP
High power
grade 2 <0.1% bad pixelsgrade 3 0.1-1.7 % bad pixels
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Summary
Tests at IPHC indicated holes in the currently used sensor selection procedure
All identified issues had been measured in probe tests but were not part of the selection criteria
It is necessary (and becoming urgent) to develop more advanced and automated sensor selection procedures– This has been one of the goals for the PXL construction project but
has not been implemented yet
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Noise and FPN measured in Ultimate 2 sensors 8 wafers
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Noise and FPN measured in Ultimate 2 sensors wafer 501
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Noise and FPN measured in Ultimate 2 sensors wafers 201-205
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Noise and FPN measured in Ultimate 2 sensors wafers 303-304
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Additional slides
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Not classified sensors wafers 201-205
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Yield and wafer maps – wafer 201,202
A01 A02
B01 B02 B03 B04 B05 B06
C01 C02 C03 C04 C05 C06 C07 C08
D01 D02 D03 D04 D05 D06 D07 D08
E01 E02 E03 E04 E05 E06 E07 E08
F01 F02 F03 F04 F05 F06 F07 F08
G01 G02 G03 G04 G05 G06
H01 H02
Wafer 201:• good: 35 73%• bad: 10 21%• (?): 3 6%
Wafer 202:• good: 36 75%• bad: 8 17%• (?): 4 8%
A01 A02
B01 B02 B03 B04 B05 B06
C01 C02 C03 C04 C05 C06 C07 C08
D01 D02 D03 D04 D05 D06 D07 D08
E01 E02 E03 E04 E05 E06 E07 E08
F01 F02 F03 F04 F05 F06 F07 F08
G01 G02 G03 G04 G05 G06
H01 H02
Physical damage
Failed JTAG or power
Failed probe tests
?
Hot/cold pixel <1%
Hot/cold pixel >1%
OK
noisy
Low VCLP
Vref2 high
Vref2 low
High VCLP
High power
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Yield and wafer maps – wafer 203,204
A01 A02
B01 B02 B03 B04 B05 B06
C01 C02 C03 C04 C05 C06 C07 C08
D01 D02 D03 D04 D05 D06 D07 D08
E01 E02 E03 E04 E05 E06 E07 E08
F01 F02 F03 F04 F05 F06 F07 F08
G01 G02 G03 G04 G05 G06
H01 H02
Wafer 203:• good: 12 25%• bad: 35 73%• (?): 1 2%
Wafer 204:• good: 26 54%• bad: 19 40%• (?): 3 6%
A01 A02
B01 B02 B03 B04 B05 B06
C01 C02 C03 C04 C05 C06 C07 C08
D01 D02 D03 D04 D05 D06 D07 D08
E01 E02 E03 E04 E05 E06 E07 E08
F01 F02 F03 F04 F05 F06 F07 F08
G01 G02 G03 G04 G05 G06
H01 H02
Physical damage
Failed JTAG or power
Failed probe tests
?
Hot/cold pixel <1%
Hot/cold pixel >1%
OK
noisy
Low VCLP
Vref2 high
Vref2 low
High VCLP
High power
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Yield and wafer maps – wafer 205
A01 A02
B01 B02 B03 B04 B05 B06
C01 C02 C03 C04 C05 C06 C07 C08
D01 D02 D03 D04 D05 D06 D07 D08
E01 E02 E03 E04 E05 E06 E07 E08
F01 F02 F03 F04 F05 F06 F07 F08
G01 G02 G03 G04 G05 G06
H01 H02
Wafer 205:• good: 35 73%• bad: 12 25%• (?): 1 2%
Physical damage
Failed JTAG or power
Failed probe tests
?
Hot/cold pixel <1%
Hot/cold pixel >1%
OK
noisy
Low VCLP
Vref2 high
Vref2 low
High VCLP
High power
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Yield and wafer maps – 2 DRIE wafers
A01 A02
B01 B02 B03 B04 B05 B06
C01 C02 C03 C04 C05 C06 C07 C08
D01 D02 D03 D04 D05 D06 D07 D08
E01 E02 E03 E04 E05 E06 E07 E08
F01 F02 F03 F04 F05 F06 F07 F08
G01 G02 G03 G04 G05 G06
H01 H02
Wafer 303:• good: 33 69%• bad: 13 27%• (?): 2 4%
Wafer 304:• good: 36 75%• bad: 11 23%• (?): 1 2%
A01 A02
B01 B02 B03 B04 B05 B06
C01 C02 C03 C04 C05 C06 C07 C08
D01 D02 D03 D04 D05 D06 D07 D08
E01 E02 E03 E04 E05 E06 E07 E08
F01 F02 F03 F04 F05 F06 F07 F08
G01 G02 G03 G04 G05 G06
H01 H02
Physical damage
Failed JTAG or power
Failed probe tests
?
Hot/cold pixel <1%
Hot/cold pixel >1%
OK
noisy
Low VCLP
Vref2 high
Vref2 low
Not in DB: A01, A02, B01, C01, C02, C03
Failed 160 MHz
High VCLP
High power