modular design in bluespec using asim/awbcsg.csail.mit.edu/bluespec/talks/10-emer-awb.pdf · 20...

Modular Design in BluespecUsing Asim/AWB

Joel Emer‡†, Michael Adler‡, Michael Pellauer‡†

‡VSSAD GroupIntel

†CSG - CSAILMIT

2007.08.13 Modular Design in Bluespec using Asim/AWB2

Why modularity?

• Speed of development

• Shared components between products

• Reuse across generations

• Improved fidelity

• Incremental refinement

• Facilitates area/speed trade-offs

• Architectural experimentation

• Factorial development and evaluations

• Sharing


ASIM Module Hierarchy

S

MC N

D R X C WF

B


ASIM Module Selection

B

B

B

B

S

MC N

D R X C WF

BB


D R X C WF D R X C WF

S

MC NC M N

Module Selection

S

BB

B

B

B

B


Module Replacement

B

B

B

B

S

MC N

D R X C WF

B

X


Module Instantiation

U

D R X C WF

MC NC

D R X C WF

M

C

D R X C WF


Factorial Coding/Experiments

SC

S

MC N

SM

RC

S

MC N

SM

SC

S

MC N

RM

RC

S

MC N

RM


Module Description (.awb file)

%name SMIPS R10K Superscalar Decode Stage

%desc SMIPS R10K Superscalar Decode Stage

%attributes s10k smips hasim

%provides hasim_pipe_decode

%requires hasim_rob hasim_branch_pred

%public Decode.bsv


(H)ASIM Module Hierarchy


Module Interfaces

• Plumbing Modules

• Algorithm Modules

• Message Modules

• Library Modules


AWB Operation

Repositories Workspace


Build Features

• Model level parameter specification

• Automatic Makefile creation from templates (L2)

• Bluespec module dependence analysis

• Easy to specify synthesis boundaries (L3a)

• Support for parallel builds (L3b)

• Allows BDPI and Verilog modules (L7)

• Support for hybrid hardware/software modules

• Targets bitfile, iverilog, Bluesim


Communication: A modularity speedbump

C

D R X C WF

N N


Soft Connections:Flattening the speedbumps

S DA-out A-in


Soft Connections

• Use “ModuleCollect” to collect connection names:

let my_con <- mkConnection_Send(“dec_to_exe”);

• Use static elaboration to find/join ends. Pseudo-code:

let cons <- getCollection(toplevel); //Get the connectionsmatch {.sends, .recs} = splitConnections(ld); //Split into sends, recsmatch {.dang_sends, .dang_recs, .cncts} = groupByName(sends, recs);foreach {.send, rec} in cncts

mkConneciton(send, rec);if (dang_sends != nil || dang_recs != nil)

error “Dangling Connections at top level!


Connections

Module AModule A Module BModule B

send “foo” recv “foo”


1. “Expose” Soft Connections and tie them to a known interface2. Output the connection mapping as a compiler message3. Use a script to parse the compiler logs and “re-bury” connections4. Use the previous scheme to connect as normal

Connections Across Synthesis Boundaries (L3)

Module AModule A

Module CModule Csend “bar”

boundary

1

2

cmax

…

Module BModule B

recv “baz”

1 is bar1 is bar

2 is baz2 is baz

recv “bar”

send “baz”

1

2

cmax

…

Note: the script could be removed if Bluespec could read input files during static elaboration

Note: the script could be removed if Bluespec could read input files during static elaboration


Acknowledgments

• David Goodwin

• Artur Klauser

• Martha Mercaldi

• Toni Juan

• Srilatha Manne

• Nate Binkert

• Shubu Mukherjee

• Angshu Parashar

• Ramon Matas

• Arvind

• Saila Parthasarathy

• Krishna Rangan

• Brian Slechta


Soon…

http://asim.csail.mit.edu


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modular design in bluespec using asim/awbcsg.csail.mit.edu/bluespec/talks/10-emer-awb.pdf · 20...

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