copyright © bluespec inc. 2006 bluespec systemverilog™ design example a dma controller with a...

Copyright © Bluespec Inc. 2006

Bluespec SystemVerilog™Design Example

A DMA Controller with a Socket Interface

2Copyright © Bluespec Inc. 2006

Overview

A DMA controller using Bluespec is presentedIncluding several examples showing one possible refinement flowFirst model shows a simple 1 channel, 1 port model (222 lines)Final model shows a 2 channel, 2 port model, with pipelined and concurrent transactions (308 lines) Testbenches included for all models


General Setup

DMA Target

master

slave

slave

master

Testbench


DMA

All DMA models contain a configuration port (slave), to read & write configuration and status registersOne or two memory ports are includedConfiguration/Status registers

Source and destination address register Transfer count Enable and current status Port selection


File Organization

DMA.bsv – The DMA modelTestBench.bsv – The testbenchsysTestBenchBench.out.expected – expected simulations results

Socket_IFC.bsv – defines a simple socket protocol, interfaces, structures, and utility functions.EdgeFIFOs.bsv – some specialized FIFOs used throughout the designsTargets.bsv – A simple target module used for testingMakefile – usual


Socket Interface

We use a simple Socket interface which is similar to OCPRequest and Responses are decoupledSeveral requests may be outstanding (pipelined)


Socket Interface

reqOpreqAddrreqDatareqInfo

reqAccept

respOprespAddrrespDatarespInfo

respAccept

Master interface

Slave interface

Request side

Responseside

TargetInitiator


Socket_Ifc.bsv

Defines structures for Request and Responses

Interfaces for the Master and Slave

typedef struct { RespOp respOp; RespInfo respInfo; RespAddr respAddr; RespData respData;} Socket_Resp

interface Socket_master_req_ifc; method ReqOp getReqOp (); method ReqInfo getReqInfo (); method ReqAddr getReqAddr (); method ReqData getReqData (); method Action reqAccept ();endinterface


Socket_Ifc.bsv

Conversion functions from FIFO interfaces to Interface

Utilities to connect Master and slave interfaceConvenience functions for debug

function Socket_master_ifc fifos_to_master_ifc (FIFOF#(Socket_Req) reqs, FIFOF#(Socket_Resp) resps);


Edge FIFOs

Specialized FIFOsPipeline FIFOs – a pipeline register with a FIFO interface.Bypass FIFOs – a 1 element FIFO which allows non-registered operationsUnguarded versions – Disables Bluespec’s implicit conditions; needed for socket protocol to provide data every cycle


Targets

Contains just a “dummy” target to act like a “memory” for testingMinimum 2 cycle latency

Sla

ve

requests

responses

Rules for Read and Write requests


Model development details

V0 – Simple FSM based DMA controller. 1 channel, 1 busV1 – Rule-based DMA controller, allowing pipelined requestsV2 – 2 Memory port, allowing pipelined concurrent read and write requestV3 – Modified version of V2 showing Bluespec’s elaboration featuresV4 – 2 channels, 2 ports, concurrent and pipelined transactions


V0 – simple DMA FSMS

lave

Configrequests

Configresponses

Rules for Read and Write config/status resisters

Mas

ter

mmu

config

Idle

WriteFinish Write

ReadFinish

Non-idle arc write a mmu request or read a response

Pipeline FIFO

Bypass FIFO


VO DMA behavior

8 cycles to move each word 2 cycle in memory 2 cycle in DMA (enqueue request, and grad data)

cycle: 25Target mem: Socket_Req{RD, 001, 001001, 0000000000000000}}cycle: 26cycle: 27cycle: 28cycle: 29Target mem: Socket_Req{WR, 002, 005001, 0000100100001001}}cycle: 30cycle: 31cycle: 32cycle: 33Target mem: Socket_Req{RD, 001, 001002, 0000000000000000}}


V0 thoughts

Most cycles are spent waiting for the mmu to respondRead requests cannot overlap with write requestsV1 decouples all these activities

Read and write requests start anytime one is needed (and all pre-conditions are met)

Responses are taken and acted upon when they arrive.


DMA V1

Each read request passes the write address to the write side via a FIFOReads or Writes can start at any time

rule startRead (dmaEnabledR && readCntrR > currentReadR ) ; let req = Socket_Req {reqAddr : readAddrR, reqData : 0, reqOp : RD, reqInfo : 1}; mmuReqF.enq( req ) ; // Enqueue the Write destination address destAddrF.enq( destAddrR ) ;

// increment addresses, decrement the counter. readAddrR <= readAddrR + 1 ; currentReadR <= currentReadR + 1 ; destAddrR <= destAddrR + 1 ; endrule


V1 DMA write rule

Implicit conditions check FIFO states as neededRule urgency puts writes before reads

(* descending_urgency = "startWrite, startRead" *) rule startWrite ( True ) ; let wreq = Socket_Req {reqAddr : destAddrF.first, reqData : responseDataF.first, reqOp : WR, reqInfo : 2 }; // tag info with 2 // enqueue the request. mmuReqF.enq( wreq ) ; // remove wdata from the fifos destAddrF.deq ; responseDataF.deq ;endrule


V1 Behavior

Fully pipelined behavior Achieves maximum throughput - 2 cycles per word

Target mem: Socket_Req{RD, 001, 001000, 0000000000000000}}cycle: 18Target mem: Socket_Req{RD, 001, 001001, 0000000000000000}}cycle: 19Target mem: Socket_Req{RD, 001, 001002, 0000000000000000}}cycle: 20Target mem: Socket_Req{RD, 001, 001003, 0000000000000000}}cycle: 21Target mem: Socket_Req{WR, 002, 005000, 0000100000001000}}cycle: 22Target mem: Socket_Req{WR, 002, 005001, 0000100100001001}}cycle: 23Target mem: Socket_Req{WR, 002, 005002, 0000100200001002}}cycle: 24Target mem: Socket_Req{WR, 002, 005003, 0000100300001003}}cycle: 25Target mem: Socket_Req{RD, 001, 001004, 0000000000000000}}


V2 – A second memory port

Port can be second memory, bus, or peripheral, separate read/write ports.Hardware additions:

Second master interface to DMA New FIFOs for interface Configuration register to mark port Duplicated rules for each port

Bluespec’s Rule analysis insures safe use of shared hardware – MMUs, FIFOs, etc.Muxes and control logic added automatically


V2 DMA behavior

Concurrent read and writes on different memoriesPeak throughput – 1 word per cyclePipeline behavior maintainedcycle: 23Target memA: Socket_Req{WR, 002, 005000, 0000100000001000}}cycle: 24Target memB: Socket_Req{RD, 001, 001004, 0000000000000000}}Target memA: Socket_Req{WR, 002, 005001, 0000100100001001}}cycle: 25Target memB: Socket_Req{RD, 001, 001005, 0000000000000000}}Target memA: Socket_Req{WR, 002, 005002, 0000100200001002}}cycle: 26Target memB: Socket_Req{RD, 001, 001006, 0000000000000000}}Target memA: Socket_Req{WR, 002, 005003, 0000100300001003}}cycle: 27Target memB: Socket_Req{RD, 001, 001007, 0000000000000000}}


V3 – Bluespec Elaboration

Bluespec allow manipulation of most objects (e.g., Rules, FIFOs) during elaborationReduces cut & paste code, allows better reuseV3 defines function to generate rules for each mmu port

function Rules generatePortDMARules (Bool rdPortCond, Bool wrPortCond, FIFOF#(Socket_Req) requestF, FIFOF#(Socket_Resp) responseF );


V3 Results

Same behavior as V2Real difference is about 26 lines of code out of 227 lines. Less than 10 % for a second mmu port.


V4 – multiple channels

Each channel is separate DMA engine – has it own read/write address, config/status registers, etc. V4 model changes constructs from scalar to vector, e.g.

Rule generation function used to create second set of rule second channelBluespec’s rules manages concurrency

// The destination address registers Vector#(NumChannels,Reg#(ReqAddr)) destAddrRs <- replicateM( mkReg(0) );


V4 Behavior

Multiple channels, multiple ports, fully pipelined, concurrent reads and writes across channelsTarget memB: Socket_Req{RD, 000, 001026, 0000000000000000}}Target memA: Socket_Req{WR, 001, 005023, 0000102300001023}}cycle: 135Target memB: Socket_Req{RD, 000, 001027, 0000000000000000}}Target memA: Socket_Req{RD, 002, 002017, 0000000000000000}}cycle: 136Target memB: Socket_Req{WR, 003, 007016, 0000201600002016}}Target memA: Socket_Req{WR, 001, 005024, 0000102400001024}}


Summary

Concurrency automatically analyzed and control logic automatically synthesized4 unique DMA architectures minimum development effort – compare lines of code

Allow rapid exploration and analysis of different architectures

V0 V1 V2 V3 V4

222 227 298 266 308

copyright © bluespec inc. 2006 bluespec systemverilog™ design example a dma controller with a...

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