mmalpha mmalpha: a tool box for silicon compilation patrice quinton, sanjay rajopadhye, tanguy...

MMAlpha

MMAlpha: A tool box for silicon compilation

Patrice Quinton,Sanjay Rajopadhye,Tanguy RissetIRISA - Projet COSIhttp://www.irisa.fr/cosi/ALPHA

09/11/2000 Oxford: MMAlpha 2

presentation overview

Brief overview of MMAlpha

Running an example

Demonstrating the software


What is MMAlpha?

A public domain silicon compiler for loop nests

FPGA

ASICVHDL

for i = 1 to n do

for k = 1 to m do

y[i,k] = y[i,k-1] + w[i,k]*x[i-k]


Vhdl1

Alpha

UniformizationScheduling/Mapping

HDL derivation

MMAlpha

What is MMAlpha?

User controlled design process

Vhdl2Vhdl3

Design script easily reused

UniformizationScheduling/Mapping 2

HDL derivation

MMAlpha


Target applications

Data intensive applications

Fir Adaptive LMS Kalman filtering

Signal processing Motion estimators

2D-filters

Multimedia

DNA sequencing

Bio-Informatics


MMAlpha highlights

Compilation of loop nests to parallel circuits

for i = 1 to n do

for k = 1 to m do

y[i,k] = y[i,k-1] + w[i,k]*x[i-k]

by means of the polyhedral model


UniformizationScheduling/Mapping

HDL derivation

MMAlpha

Alpha

MMAlpha highlights

Hierarchical design methodology

Alpha


MMAlpha highlights

Multi-target output for co-design

VHDL

for i = 1 to n do

for k = 1 to m do

y[i,k] = y[i,k-1] + w[i,k]*x[i-k] C


MMAlpha implementation

Open source software (GNU license)Mathematica + CEasily extensibleCurrent development:

Interface host/co-processor Prototyping real life applications (adaptive

filters, DNA sequence comparison) partitionning


MMAlpha running exemple

SAMBA:

Hardware accelerator for DNA sequence comparison


The algorithm


The algorithm

Alignment matrix


Samba: history

VLSI array built in 1995

128 systolic processor on 32 chips


Equations

Recurrence

for one point of the matrix

M[i,j]

M[i-1,j]-8

M[i,j-1]-8

M[i-1,j-1]+MatchQ


Alpha code (part 1)

system sequence: {X,Y| Y>X>2} (QS : {i| 1<= i <= X} of integer; DB : {j| 1<= j <= Y} of integer)returns (res : {j| 1<= j <= Y} of integer); varM: {i,j| 0<= i <= X; 0<= j <= Y} of integer;MatchQ: {i,j| 1<= i <= X; 1<= j <= Y} of integer;let ...


Alpha code (part 2)

...letM[i,j]=case

{|i=0} | {|j=0}: 0[];{|i>0; j>0}: Max4(0[],

M[i,j-1]-8[], M[i-1,j]-8[],

M[i-1,j-1]+MatchQ[i,j]);MatchQ[i,j]=if (QS[i]=DB[j]) then 15[] else -12[];res[j]=M[X,j];tel;


Iteration space

MatchQ[i,j]=if (QS[i]=DB[j]) then 15[] else -12[];

M[i,j]=case{|i=0} | {|j=0}: 0[];{|i>0; j>0}: Max4(0[], M[i,j-1]-8[],

M[i-1,j]-8[], M[i-1,j-1]+MatchQ[i,j]);esac;


Uniformization (part 1)


Uniformization (Part 2)


Scheduling


Mapping


RTL derivation (control generation)


RTL derivation (structuring)


pipeline of the control


Design flow summary

Matlab

Alpha

FPGA

ASIC

VHDL

Uniformization

RTL derivation

Scheduling


What I did not talk about:in test

Z-polyhedral domain: {2i,3j+9i| 0<= i <= X; 0<= j <= Y}

Hardware-software interface Experiments on the Virtex XCV800

Starting from imperative code Use MatParser (Compaan project) to

translate Matlab into Alpha


What I did not talk about:in development

Partitioning and memory …. Still not implemented

Bit width selection methodology in development for nested loop

programs.

Stronger semantic checks connection to PVS (theorem proover)

Hierarchical design


Perspective for MMAlpha

Prototyping the tool for “real life” application

Provide support for use in Academic places

Industrial use? industrial development?

mmalpha mmalpha: a tool box for silicon compilation patrice quinton, sanjay rajopadhye, tanguy...

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et une horloge

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et une architecture

une bote vhdl

fpga et asicson

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