Mixed Analog and Digital Circuit Boards for the

ATLAS TRTNandor Dressnandt, Godwin Mayers, Toni Munar, Mitch Newcomer,

Rick Van Berg, Brig WilliamsUniversity of Pennsylvania

Bjorn LundbergLund University

Thurston Chandler, Colin GayYale

Curt BaxterUniversity of Indiana

NSS 2003 2

TRT Physical Layout

Barrel End Cap Wheel

Electronics

Readout on Tread

Barrel Readout

in 2.5cm Crack

NSS 2003 3

Full Readout With Custom ASICSLow Level Differential Ternary Output

(200uAStep) ASDBLRDTMROC

LVDS (like)

Clock/Control/DataChip to Back End

16 Channel Readout ASIC 16 Channel Readout ASIC TripletTriplet

NSS 2003 4

Barrel TRT Module End

HV Connector

Arrays of 16 Straw Wire Anodes +

6 (AC coupled) Cathode Ref

Barrel Support Frame

Straw wire Density30mm2/ straw

2X the density of Wheel

NSS 2003 5

Stamp Board Approach

Stamp FLEX Boards Kapton Connection

Inputs from straw wires

Output RoofConnectorDTMROC in TQFP

Chip on Board ASDBLR’s

16 Channel ASIC triplet Readout

Cathode Reference

Low

Man

ufac

turin

g Yie

ld

NSS 2003 6

ASIC Packaging Custom Fine Pitch Ball Grid

Arrays

ASDBLR8channel

ASDBLR8channel

16 Channel DTMROC

7.2 X 9.6mm

11X13mm

NSS 2003 7

Stamp Board Threshold Scans

Large Channel to Channel Variations

due to Clock pickup

# H

its in

75n

s G

ate

Increasing Thresold

NSS 2003 8

External currents added in signal return path can seriously corrupt straw signal.

Signal Return Path

ASD Preamp Agnd Connector pins

Straw reference Plane HV CAP Straw Cathode

Ideal Signal Return

These currents may be redirected over a large area by adding a low impedance network of conductors at the end of the module.

Other ConductorsCable Shield currents, Dgnd bounce noise

NSS 2003 9

Single Analog and Digital Board Approach

Module 1 Small Triangle (one of 16 Custom Barrel Designs)

Data Cable Connector(Unstuffed)

DTMROC ASICS

Top Side Digital

Under side Analog

ASDBLR ASICSundersideStraw Pin Floating Contact (NAIS) Connector

Input Protection Board(s) 16 Straw modularity1 of 10 Boards Shown

Pow

er

Access along All Edges toAnalog GND

Encloses Detector Ends

NSS 2003 10

First try at A and D Board

Hopeful but not very good.

•Clock pickup between supplies.•Poor access to board grounds at the top of the board. •Line over line differential clock / control routing near inputs. •Trial areas where different routing techniques were studied.

It did provide an essential case study to justify effects of various design techniques that otherwise would be simple speculation.

Motivates Common Sense Design Rules:

• Separate Analog and Digital Power Domains.• Maximize distance between Digital and layers

and Analog power layers (lower Capacitance between domains).

• A and D Grounds join at board edges with small resistance at many locations (Current Flow Control).

• Blind Vias for Analog inputs and Digital clock, data and control.

NSS 2003 11

Second A and D Barrel Board

• 90% of channels work acceptably.

• 1 – 2 channels per location exhibit serious clock pickup noise.

Cause Blind vias from inputs poking through Board shield layers.

Straw Input Side with first

inner layer

Loc

#3

NSS 2003 12

Problem Location (#3)

Position 3 Active Roof for Module 2

50%

Th

resh

old

in D

AC

Co

un

ts

Beam Clock Syncronous Time Bin 3.1ns /Bin

75ns total Width

50% occupancy threshold by time 3.1ns bin

NSS 2003 13

AR2FS Location #3Layer 14 Component Side

Inpu

t C

onne

ctor

AS

DB

LRA

SD

BLR

NSS 2003 14

AR2FS Location #3Layers 14 and 12 (analog side)

Inpu

t C

onne

ctor

AS

DB

LRA

SD

BLR

Side by side input traces

under connectorlayer 12

NSS 2003 15

AR2FS Location #3Layers 12, 14, and 1(DTMROC side)

NSS 2003 16

AR2FS Location #3Layers 14, 12, and 1 Clock vias Highlighted

NSS 2003 17

AR2FS Location #3Layers 14, 12, 1, and 4 Clock vias Highlighted

NSS 2003 18

AR2FS Location #3Layers 14, 12, 1, and 4

Clock vias, Line 11 Highlighted

MeasuredClock Pickup

Threshold50% min-max

100 DAC Cnts

Ch #7

NSS 2003 19

AR2FS Location #3Layers 14, 12, 1, and 4

Clock vias, Lines 11, 14, and 15 Highlighted

MeasuredClock Pickup

Threshold50% min-max

180 DAC cnts

Ch #9

NSS 2003 20

AR2FS Location #3Layers 14, 12, 1, and 4

Clock vias, Lines 11, 14, and 15 Highlighted

Line 5 Highlighted in Light Gray

MeasuredClock Pickup

Threshold50% min-max

35 DAC Cnts

Ch #3

NSS 2003 21

Board Injection CapacitanceAnalog Blind Via to Digital Clk

TraceEnd of via layer 6 to nearby trace layer 4 250um separation.

Measured “via to trace” clock Injection charge.

Min-Max/2 = 35cnts ~ 1.5fC

Clock edge amplitude ~ 150mV

C = Qinj/ Vclock= 10fF

NSS 2003 22

Improved AR Board Design• Stackup1. Component Signal w Gndd Area fill - Gnda at edges

2. Signal

3. Vdd

4. Gndd

5. Signal - Gnda ring at board edge.

6. Signal (desperation layer) no clocked signals Gnda ring at board edge.

7. Empty

8. Vee (-3V)

9. Gnda ( Shields inputs from Digital side.)

10. Vcc ( Open under inputs to reduce capacitance)

11. Signal ( threshold test pulse etc.) Gnda Area fill with slots under inputs

12. Input Signal with Gnda Area fill

13. Gnda

14. Analog Components, Signal, Gnda Area fill

Blind vias

NSS 2003 23

Visualization of AR Board

Shield Layers

Power Curt Baxter IUDigital Domain Clk/ Control

Vdd Gndd

GndaVee

Vcc

Analog Signal

NSS 2003 24

Active Roof Layout Side ViewSingle Site (visualization)

Input Shield

NSS 2003 25

Present PerformanceOn Detector Threshold AR 1

Scans

NSS 2003 26

Latest Board Test Results(AR1FL)300 KHz Rate Threshold by location and channel

We are Awaiting the Edge Plated and improved GNDA Version

Target Threshold

~2fC

NSS 2003 27

Summary of our Approach

• Separate Analog and Digital Domains vertically.• Merge Grounds but Control Current flow.• Shield inputs with analog ground plane. • Minimize capacitance of input traces to other internal

board layers.• Complete shield of end of detector with analog ground.• Encourage Digital energy to radiate away from Analog

side. Keep clock /control/data above Vdd.• Use board thickness to reduce capacitive coupling

between Analog and Digital power planes.• Use low level differential clock/control/data for off chip

communication.We should note that these boards present a challenge to the board mfgrs Used so far. Not impossible but both expensive and often late in arrival.

NSS 2003 28

Estimating Required VddFilter Capacitance

• Assume 40MHz Clocked devices on DTMROC must be filtered locally to at least 1mV using local capacitance.

• AR1FL Vdd current measurements

clock “on” “off”

Vdd Current 1.1A 0.89A

Difference current by chip – 19.1mA

NSS 2003 29

Determining Filter Capacitance

NSS 2003 30

DTMROC Vdd filtering

Model of Clocking Current (mostly on DTMROC)

40 Mhz Bx

~ 200pF “on Chip”Aggregate clocked Capacitance

Vdd

Gndd

Assume 1.5ns Switching

Peak current ~300mA

NSS 2003 31

AR board Vdd filtering

Bigger Picture

Vdd

Gndd L-R-C

L-R-CPower Cable

AR board DTMROC’s

Each DTMROC ΔQ = 200pF * 2.5V

Choose Filter Cap s.t. ΔV (supply open) =

1mV

Cfilter = ΔQ / 1mV = 0.5μF

NSS 2003 32

Vdd (Layer 3) – Gndd (Layer 4) Scope Measurements

2 - .2uF caps / DTMROC 6 - .2uF caps / DTMROC

7mV peak – Peak2.3mV RMS

17mV peak – Peak5mV RMS

Via impedance limitsImprovement here.