July

2, 2003

mitch@

hep.u

penn.e

du

1

Th

e A

SD

BL

R a

nd

DT

MR

OC

Dete

cto

r M

ou

nte

d R

ead

ou

t f

or

the A

TL

AS

TR

T

Mit

ch

New

co

mer

fo

r th

e A

TL

AS

TR

T E

lectr

on

ics G

rou

p

July

2, 2003

mitch@

hep.u

penn.e

du

2

TRT

TR

T W

heels

Rad

ially

Alig

ned

Str

aw

s (

320K

ch

an

nels

)

TR

T F

ron

t E

nd

Ele

ctr

on

ics

Barr

el M

od

ule

s

Axia

lly a

lig

ned

100K

ch

an

nels

July

2, 2003

mitch@

hep.u

penn.e

du

3

Dete

ctor

Mou

nted

Readou

t Obje

ctives

•L

ow

No

ise

/Lo

w t

hre

sh

old

op

era

tio

n

~2

00

0e

EN

C

< 3

00

KH

z s

ponta

neous str

aw

tube tr

igger

rate

•1

ns tim

e r

esolu

tion

~1

30

µm

po

sitio

n r

eso

lutio

n

•H

igh

Ra

te o

pe

ratio

n

20

MH

z w

ith

sta

ble

th

resh

old

(100:1

Sig

nal variation)

•R

ad

iatio

n T

ole

ran

ce

3.5

X10

14

n/c

m 5M

Rad

•R

elia

ble

op

era

tio

no

f h

igh

ba

nd

wid

th A

na

log

an

d D

igita

l re

ad

ou

t A

SIC

sw

ith

ou

t in

terf

ere

nce

•A

TLA

S R

eadO

utD

rive

rC

om

pa

tib

ility

July

2, 2003

mitch@

hep.u

penn.e

du

4

Readou

t Elect

ronics

basic

block

16

ch

an

ne

l c

us

tom

AS

IC t

rip

let

July

2, 2003

mitch@

hep.u

penn.e

du

5

ASDBLR R

efe

renc

es

Imp

lem

en

tati

on

of

the

AS

DB

LR

Str

aw

Tu

be

Re

ad

ou

t

AS

IC i

n D

MIL

L T

ec

hn

olo

gy

N. D

ressnandt, N

. Lam

, F

.M. N

ew

com

er,

R. V

an B

erg

and H

.H. W

illia

ms

IEE

E (

2000)

Tra

ns. O

n N

ucl. S

ci. V

48 n

4 p1239

An

Am

plifi

er-

Sh

ap

er-

Dis

cri

min

ato

r w

ith

Baselin

e R

esto

rati

on

for

the

AT

LA

S T

ran

sit

ion

Ra

dia

tio

n T

rac

ke

rB

. B

evensee,

F.M

. N

ew

com

er,

R.

P.

Van B

erg

and H

.H.

Will

iam

s

IEE

E (

1996)

Tra

ns. on N

uc. S

ci.

V 4

3 p1725

http://w

ww

.hep.u

penn.e

du/a

tlas

July

2, 2003

mitch@

hep.u

penn.e

du

6

ASDBLR

8 C

h A

nalog

Fro

nt E

nd

DT

MR

OC

Diffe

rential S

ignal P

rocessin

g

Tra

ckin

g C

om

para

tor

Inp

ut

gain

~

18m

V/f

C

Tra

ck T

hre

sh

old

Gain

~ 120m

V/f

C

TR

T

hre

sh

old

Gain

~ 10m

V/f

C

July

2, 2003

mitch@

hep.u

penn.e

du

7

ASDBLR

Basic

Design

Spe

c

•Po

wer

~ 4

0mW

/ch.

•Pr

eamp

Inpu

t pr

otect

ion

~ 2

.8mJ.

•Ana

log

Gain ~

18mV/f

C a

t Com

para

tor

inpu

t.•

Dou

ble P

ulse

Reso

lution

~ 2

5 –

50ns

depe

ndent

on

1st

pulse a

mplitud

e.

•Spo

ntane

ous

Trigg

er

Rate

at

2fC

thre

shold ~

300KHz.

•High T

hre

shold M

axim

um R

ang

e140fC

.•

Tern

ary

(co

mpa

rato

r) o

utpu

t leve

ls (no

minal Design

):

Tern

Neg

Tern

Po

sS

ign

al

-400u

A0u

AT

rack &

TR

-200u

A-2

00u

AT

rack o

nly

0u

A-4

00u

AQ

uie

scen

t

July

2, 2003

mitch@

hep.u

penn.e

du

8

ASDBLR

Implement

ation

•Pro

cess

-Rad

Tolera

nt 0.8

um B

iCM

OS

Tech

nology

(DM

ILL)

•Design

ed a

t th

e d

iscr

ete

device

leve

l us

ing

SPI

CE f

or S

imulation

•Chann

el Com

plexity

160 B

ipolar

Tra

nsisto

rs /

10 C

MOS S

witch

es

160 R

esist

ors

/ 105 C

apa

cito

rs

•Chann

el base

d L

ayou

t ~

Avo

ided m

eta

l ru

ns o

ver

trans

isto

rs/r

esist

ors.

Dou

ble v

ias

where

pos

sible.

Sepa

rate

d A

nalog

and

Com

para

tor/

Tern

ary

Drive

r Po

wer

Dedicate

d p

ower

bus

distr

ibut

ion

at

the c

hann

el leve

l.

Sub

stra

te C

onta

ct a

nd P

ower

bus

s isolation

betw

een

ch.

Preamp

Sup

ply f

ilte

r on

each

chann

el.

•Eight

(ne

arly) ident

ical Chann

els o

n 340um

Pitch

July

2, 2003

mitch@

hep.u

penn.e

du

9

ASDBLR d

esign

Cycle

Layo

ut

Netl

ist

Extr

ac

tio

n w

ith

para

sit

ics

Sim

ula

tio

n w

ith

Extr

acte

d S

ch

em

ati

c

Layo

ut

Driven

Sch

em

atic R

evis

ionF

ou

nd

ry P

rovid

ed

Lib

rary

Part

s

Develo

p N

ew

Lib

rary

Part

s

Perf

orm

an

ce

Driven

Sch

em

atic R

evis

ion

Fab

( 20 w

eeks)

Test D

evic

es

Package

Sch

em

ati

c L

evel

Desig

n a

nd

Sim

ula

tio

n

July

2, 2003

mitch@

hep.u

penn.e

du

10

ASDBLR02 F

inal Design

•Reduc

e a

rea o

f inpu

t pr

otect

ion

netw

ork

Reduc

e C

apa

cita

nce

11pf

5pF

.

•In

crease

Inp

ut t

rans

isto

r cu

rrent

to

7.5

uA/m

reduc

e b

eta

los

s.

•In

crease

ana

log

gain b

y 5

0% t

o re

duc

e s

ens

itivity t

o device

matc

hing

in c

ompa

rato

r. (56mV/f

C a

t BLR o

utpu

t)

Fin

al D

esig

n Im

pro

vem

en

ts

•In

put

refe

rred t

hre

shold m

atc

hing

good

, RM

S <

.25fC

•Noise

~ 2

100e E

NC o

n boa

rd w

ith ~

5pF

capa

cita

nce (100e/p

f).

•Po

wer

~ 4

0mW

/chann

el.

•High R

ate

ope

ration

~ d

emon

stra

ted t

o 20M

Hz

(pulse

rte

sts)

Measu

red

Resu

lts

July

2, 2003

mitch@

hep.u

penn.e

du

11

Prod

uction

ASDBLR

Du

al

Pre

am

ps

inte

rmin

gle

d

layo

ut

Inp

ut

Tra

nsis

tors

in

cro

ss Q

uad

Co

nfi

gu

rati

on

Inp

ut

pro

tecti

on

N

PN

Tra

nsis

tors

Exp

an

ded

Geo

metr

y

Em

itte

r S

trip

es 4

x 3

0 u

m

3.3

X 3

.6m

m

Com

para

tors

B L

R’s

Shape

rs

Preamps

July

2, 2003

mitch@

hep.u

penn.e

du

12

ASDBLR R

adiation

Test

ing

•G

am

ma T

esti

ng

up

to

7M

Rad

wit

h n

o s

ign

ific

an

t

perf

orm

an

ce d

eg

rad

ati

on

.

•1M

eV

NE

IL N

eu

tro

n T

esti

ng

to

5X

10

14

(10 y

ear

wit

h

saft

ey

facto

r) s

ho

ws a

sig

nif

ican

t r

ed

ucti

on

in

beta

resu

ltin

g in

lo

wer

gain

an

d in

cre

asin

g t

he c

han

nel to

ch

an

nel th

resh

old

off

set.

A

t B

eta

= 3

0 t

he g

ain

is

low

ere

d b

y ~

50%

.

–DM

ILL N

PN B

eta

is

sens

itive t

o Therm

al Neut

rons

Mor

e s

tudy n

eeded. M

odera

tor

re-eva

luation

?

July

2, 2003

mitch@

hep.u

penn.e

du

13

Neu

tron

s

Therm

al N

eutr

ons p

resent at

the L

jubja

na

facili

ty p

oin

t out

a p

ossib

le w

eakness u

sin

g

the D

MIL

L P

rocess.

Care

ful com

parison o

f th

ese

results w

ith the e

xpecte

d

exposure

in the A

TLA

S ID

need to b

e p

erf

orm

ed.

8 y

ear

TR

T E

xp

osu

re

wit

h S

afe

ty f

ac

tors

All

devi

ces

anne

aled

at

15

0o

C fo

r 4

8 h

rs.

(1M

eV

NE

IL)

July

2, 2003

mitch@

hep.u

penn.e

du

14

ASDBLR R

adiation

Test

ing

repo

rt

NSS 2

002

ASDBLR

# chips

Power on

Date

Ty

pe

Dose

1

Change in

Resistance

Post Rad

NPN Beta

3

4

/00

5

X1

013

n

NA

8

4

3

4

/00

1

X1

014

n

NA

5

2

99

6

x

5/0

1

5M

rad

5

%

18

0

00

9

1

0/0

1

3.5

X1

014 n

1

.5%

5

5 3

01

6

x

6/0

2

1.5

X1

0 1

4 p

5

%

70

01

16

x

7

/02

7

MR

ad

8%

1

30

01

10

5/0

2

3.5

X1

014

n1

0.4

%

11

2,3

1n

and p

dose

is in

un

its o

f p

art

icle

s/c

m2.

2T

he

rma

l neu

tron d

ose h

igh ~

10

14 n

/cm

2.

3 A

fte

r annealin

g 2

3hrs

@150C

05

10

15

20

25

30

35

0.0

5.0

10.0

15.0

20.0

25.0

30.0

35.0

Colle

ctor

Curr

ent

Den

sity

(A

/M)

Beta after Neutron Damage

Ave

rage

Va

lue

s fo

r 6

ir

radi

ate

d 4

um

NP

N's

Inp

ut

Tra

nsi

stor

Tra

ck D

isc

Com

para

tor

Sh

ap

er

Sta

ges

Fro

m:

R

ad

iati

on

Hard

ness:

Desig

n A

pp

roach

an

d M

easu

rem

en

ts

of

the

AS

DB

LR

AS

IC f

or

the A

TL

AS

TR

TN

andor

Dre

ssnandt, M

itch

New

com

er,

mem

ber

IEE

E, O

le R

ohne

and S

teven P

assm

ore

See N

SS

2002 C

on

fren

ce

Reco

rd

Su

mm

ary

of

Devic

e t

ests

to

11 / 2

002

The m

easure

d c

urr

ent ga

in o

f D

MIL

L N

PN

tra

nsis

tors

afte

r

exposu

re to 3

.5X

1014n/c

m2

and p

rio

r to

annea

ling

. T

he

arr

ow

s s

how

the o

pera

ting p

oin

ts c

hosen fo

r va

rious p

art

s

of th

e A

SD

BLR

channe

l desig

n. A

fte

r annea

ling the b

eta

incre

ased b

y a

facto

r of tw

o.

July

2, 2003

mitch@

hep.u

penn.e

du

15

DTM

ROC-S

CE

RN

Mic

roE

lectr

on

ics

an

dP

en

nV

.Ryjo

v

JIN

R, M

oscow

, R

ussia

and U

niv

ers

ity o

f Lund, Lund, S

weden

F.A

ng

hin

olf

i, P

h.F

art

ho

uat,

P.L

ich

ard

CE

RN

, G

eneva 2

3, S

witzerland

R.S

zczyg

iel

CE

RN

, G

eneva 2

3, S

witzerland a

nd IN

P, C

racow

, P

ola

nd

N.D

ressn

an

dt,

P.T

.Keen

er,

F.M

.New

co

mer,

R.V

an

Berg

,

H.H

.William

s

Univ

ers

ity o

f P

ennsylv

ania

, P

hila

delp

hia

, U

SA

July

2, 2003

mitch@

hep.u

penn.e

du

16

DTM

ROC R

efe

renc

es

Pro

gre

ss i

n t

he D

evelo

pm

en

t o

f th

e D

TM

RO

C T

ime M

easu

rem

en

t C

hip

for

the A

TL

AS

Tra

nsit

ion

Rad

iati

on

Tra

cker

(TR

T)

C. A

lexan

der

, F

. A

ng

hin

olf

i, N

. D

ress

nan

dt,

T. E

ken

ber

g, P

h. F

arth

ou

at, P

. T

. K

een

er, N

. L

am, D

. L

a M

arra

,

J. M

ann, F

. M

. N

ewco

mer

, V

. R

yjo

v, M

. S

oder

ber

g, R

. S

zczy

gie

l,

V. T

ikhom

iro, R

. V

an B

erg, H

.H. W

illi

ams

IEE

E (

2000)

Tra

ns

. O

n N

uc

l. S

ci.

V4

8 n

3

p51

4

Imp

lem

en

tati

on

of

the D

TM

RO

C-S

AS

IC f

or

the A

TL

AS

TR

T

Dete

cto

r in

a 0

.25µ

m C

MO

S t

ech

no

log

y

V.R

yjo

v, F

.An

gh

ino

lfi, P

h.F

art

ho

uat,

P.L

ich

ard

, R

.Szczyg

ielN

.Dre

ssn

an

dt,

P.T

.Keen

er,

F.M

.Ne

wc

om

er,

R.V

an

Be

rg, H

.H.W

illi

am

s, T

.Ak

es

so

n, P

.Ee

rola

htt

p:/

/he

p.u

pe

nn

.ed

u/a

tla

s

NS

S 2

002 C

on

fren

ce

Reco

rd

July

2, 2003

mitch@

hep.u

penn.e

du

17

DTM

ROC

func

tion

al B

lock

s

V.R

yjov

July

2, 2003

mitch@

hep.u

penn.e

du

18

DTM

ROC–S

Tim

e M

arking

•8

eq

ua

lly s

pa

ce

d c

lock

outp

uts

used to s

am

ple

str

aw

tra

ck p

uls

es

•5

0%

duty

cycle

clo

ck

regenera

ted to

run the

ch

ip c

ore

lo

gic

RE

F C

LO

CK

BC

1

BC

2

BC

3

BC

4

BC

5

BC

6

BC

7

BC

8

Lth

r

00000011

11111110

Fro

nte

nd

La

tch

ing

Fro

nte

nd

La

tch

ing

In p

ipe

lin

e l

atc

hin

gIn

pip

elin

e l

atc

hin

g

32 e

lemen

ts d

elay

cha

in, ph

ase

det

ecto

r, c

harg

e pu

mp

40

MH

z C

lock

3

ns t

ime

bin

s

July

2, 2003

mitch@

hep.u

penn.e

du

19

DTM

ROC–S

Mem

ory

/Pipe

line

Dua

l-po

rt 1

28

153

-bit

SR

AM

(2.3

9kB

)

V.R

yjov

July

2, 2003

mitch@

hep.u

penn.e

du

20

DTM

ROC–S

I/O

•Ful

l/R

educ

ed r

ead-

out

: 44

4/3

80

bit

s pe

r ev

ent,

incl

udin

g H

eade

r

•LV

DS

-com

pati

ble,

tri

stat

edr

iver

s ->

40

Mbi

ts/s

copp

er li

nks

•Wir

e-O

R”

–fo

r se

lf t

rigg

erin

g fa

st-o

ut o

ptio

n -

sele

cted

tern

ary

inpu

ts c

ontr

ibut

e to

the

chi

p-le

vel t

rigg

erU

p to

15

DT

MR

OCs

can

be

“OR

’ed

on a

com

mon

bus

s

July

2, 2003

mitch@

hep.u

penn.e

du

21

DTM

ROC-S

DAC’s

•In

tern

al bandgap

refe

rence 1

.26V

•C

urr

ent m

irro

r m

aste

r -

128 P

MO

S

unit d

evic

es (

L=

8um

,W=

5um

)

•256 identical P

MO

S s

lave c

urr

ent

mirro

rs p

er

DA

C

V.R

yjov

July

2, 2003

mitch@

hep.u

penn.e

du

22

DTM

ROC-S

Ana

log

Sen

sing

•Two

DACs

•Fou

r Com

para

tors

–Tem

pera

ture

–VDD

–Ext

Volta

ge 1

–Ext

Volta

ge 2

Vdd

Sen

se r

emaine

d a

t 191 f

rom 2

6 –

55 C

July

2, 2003

mitch@

hep.u

penn.e

du

23

DTM

ROC-S

test

ability

•Gen

eral-pu

rpos

e 32-bits

Sta

tus

Reg

iste

r •

Logica

l OR o

f all DTM

ROC e

rror

ind

icat

ors

in t

he D

ata

Hea

der

field

•Pa

rity

che

ck log

ic f

or a

ll inte

rnal r

egiste

rs•

Lock

sta

tus,

a

“wat

ch d

og”an

d a

“dyn

amic”ch

eck

circ

uitr

ies

exam

ine

the

DLL

•JTAG B

ound

ary-

Sca

n•

Spe

cial s

can

mod

e -

conf

igur

es a

ll DTM

ROC f

lip-flop

s as

a

larg

e sh

ift

regist

er c

ontr

olled v

ia J

TAG int

erfa

ce•

Mem

ory

Build-In

-Self-

Tes

t (B

IST) co

ntro

lled v

ia t

he

Con

figu

ration

reg

iste

r an

d J

TAG int

erfa

ce

July

2, 2003

mitch@

hep.u

penn.e

du

24

•In

tern

al r

egiste

rs a

re e

quippe

d

with

parity

err

or c

heck

•The

mos

t cr

itical p

arts

are

built o

f th

e SEU r

esista

ntan

d s

elf-

reco

vering

elemen

tsbas

ed o

n tr

iple log

ic w

ith

maj

ority

vote

.•

Sta

tist

ics

circ

uit

mon

itor

s th

e nu

mber

of

det

ecte

d S

EU’s

DTM

ROC-S

SEU P

rote

ction

V.R

yjov

July

2, 2003

mitch@

hep.u

penn.e

du

25

DTM

ROC-S

Des

ign

Too

ls(C

ERN b

ased

)

•V

eri

log

mo

de

llin

g

•S

yn

op

sys

syn

the

sis

to

ols

•S

ilico

n E

nse

mb

le

Pla

ce

&R

ou

te to

ols

•C

om

ple

tely

scrip

ted

ph

ysic

al

de

sig

n flo

w

•N

um

ber

of synth

esis

-layout

cycle

s t

o p

redic

t post-

route

tim

ing d

uring R

TL s

ynth

esis

•N

C V

eri

log

Sim

ula

tor

–In

terle

ave

d N

ative

Co

mp

iled

C

od

e A

rch

ite

ctu

re

Be

ha

vio

ral

Mo

de

l

Syn

op

sys

syn

the

sis

Pla

ce

&

Ro

ute

Netlis

ts

Syn

op

sys

Lib

rary

Co

mp

ile

r

Hyp

erE

xtr

ac

tLay

out

Wire

Load

Tab

le

Tech

no

logy

Lib

rary

veri

log

V.R

yjov

July

2, 2003

mitch@

hep.u

penn.e

du

26

DTM

ROC-S

Layo

ut

Die

siz

e 5

.25

.0 m

m²

~50

0k

Tra

nsis

tors

July

2, 2003

mitch@

hep.u

penn.e

du

27

DTM

ROC-S

Fab

•S

ubm

itte

d/fa

bric

ated

(.2

5um

pro

cess

) in

Jan

20

02

–W

afer

siz

e 8

”(3

50

µm)

1017

use

able

die

s pe

r w

afer

•8

50

chi

ps t

este

d on

the

mix

ed s

igna

l IM

S T

este

r at

CE

RN

•5

pro

cess

cor

ner

(85

/92

/10

0/1

15/1

25

%)

eval

uate

d•

87

%Y

ield

for

85

0 c

hips

•Ir

radi

atio

n to

lera

nce

test

at

CEA

Sac

lay

Pagu

refa

cilit

y in

J

uly

20

02

•S

EU

sen

siti

vity

eva

luat

ed a

t th

e CE

RN

PS

in J

uly

20

02

•T

est

Bea

m a

t th

e CE

RN

H8

in A

ugus

t-S

epte

mbe

r 2

00

2

July

2, 2003

mitch@

hep.u

penn.e

du

28

DTM

ROC-S

Rad

iation

Tes

ting

Tot

al I

onizing

Dos

e to

lera

nce

Tot

al I

onizing

Dos

e to

lera

nce

•T

este

d at

CE

A S

acla

yPa

gure

faci

lity

in J

uly

20

02

•7

Mra

dto

tal d

ose

/ 1.

33

MeV

gam

ma

radi

atio

n•

~10

% in

crea

se in

the

DA

C’s

outp

ut v

olta

ge a

fter

irra

diat

ion,

no

DN

L ch

ange

•N

o va

riat

ions

in t

he p

ower

con

sum

ptio

n an

d th

e ch

ip p

erfo

rman

ce

SEU s

ensitivity

SEU s

ensitivity

•E

valu

ated

at

the

CER

N P

S ir

radi

atio

n fa

cilit

y in

Jul

y 2

00

2•

Inte

grat

ed f

luen

ceof

1.8

1014

p/cm

2on

24

GeV

bea

m•

SE

U c

ross

-sec

tion

for

a s

ingl

e D

flip

-flo

p in

dif

fere

nt in

tern

al r

egis

ters

va

ries

fro

m 0

.810

-14

to 1

.210

-14

cm2

•Im

pact

of

SE

U’s

in t

he v

ital

com

pone

nts

is s

uppr

esse

d by

sel

f-re

cove

ring

logi

c

July

2, 2003

mitch@

hep.u

penn.e

du

29

ASDBLR &

DTM

ROC

Pack

aging

Labeling

Fine P

itch

Ball

Grid A

rrays

Lase

r M

ark

ed p

ack

age

s2D Bar

code

Hum

an

Readable

numbering

July

2, 2003

mitch@

hep.u

penn.e

du

30

ASIC

Test

ing

July

2, 2003

mitch@

hep.u

penn.e

du

31

ASDBLR

DU

T B

oard

on

IMS

DUT B

oard

With F

BGA S

ocke

t

July

2, 2003

mitch@

hep.u

penn.e

du

32

IMS T

est

s on

ASDBLR

Read B

ar

code a

nd r

eco

rd t

est

(eve

nt) Num

ber

•S

uppl

y C

urre

nt

•In

put

volt

age/

resi

stan

ce

•O

utpu

t cu

rren

t /

swit

chin

g

•Lo

w T

hre

shol

d r

espo

nse

to 0

, 2

, 3

fC

inpu

t

•H

igh T

hre

shol

d r

espo

nse

to 3

0 f

C.

Write

Resu

lts

to SQ

L d

ata

base

July

2, 2003

mitch@

hep.u

penn.e

du

33

Failur

es

Due

to

Soc

ket

Pin

Reliability

Un

reliab

le

Pin

Co

nta

ct

On

Ou

tpu

t

July

2, 2003

mitch@

hep.u

penn.e

du

34

Using

For

ced A

ir t

o clean

pogo

pins

July

2, 2003

mitch@

hep.u

penn.e

du

35

Finding

ASDBLR

50% T

hre

shold

Fit

th

resh

old

cu

rve t

o f

ind

50%

po

ints

July

2, 2003

mitch@

hep.u

penn.e

du

36

IMS B

eta

Sta

ge T

est

ing

Expe

rienc

e

•F

irst

3

00

0 c

hip

s dem

onst

rate

min

or p

roble

ms.

•

Soc

ket

Pins

mus

t be

clea

red w

ith f

orce

d a

ir

dai

ly.

•S

ome

wan

der

ing

of t

he

Thre

shol

d 5

0%

poi

nts

day

to

day

.•

Bar

cod

e to

o cl

ose

to c

hip

lab

el, le

ads

to ~

5%

re

ad e

rror

s.False f

ailur

e r

ate

~10% p

rese

ntly

Shou

ld impr

ove o

ver

time.

July

2, 2003

mitch@

hep.u

penn.e

du

37

Yield o

n First

3000 D

evice

s with B

eta

Test

ing

vers

ion

Rep

resen

ts Y

ield

of

AS

ICS

an

d T

este

r

Targ

et

for

Fin

al A

ccep

tan

ce

July

2, 2003

mitch@

hep.u

penn.e

du

38

End

Cap

Wheel Boa

rds

•1

92

ch

an

ne

ls p

er

asse

mb

ly

•2 D

TM

Board

’s =

1 v

irtu

al

mo

du

le.

–1/3

2 o

f endcap

type A

w

he

el

•F

lexib

le in

terc

on

ne

ct

be

twe

en

6

4 c

ha

nn

el D

TM

RO

C b

oa

rds

allo

ws 1

92 c

hannel board

to

follo

w c

urv

atu

re o

f w

heel

tread.

•In

itia

l nois

e m

easure

ments

on

pro

toty

pe d

ete

cto

r show

opera

tion a

t 2fC

possib

le.

Sid

e v

iew

of

the s

tackup

of one 6

4 c

hannel A

SD

board

, one

(old

) 64 c

hannel D

TM

board

, and a

connecto

r board

192 c

han

nel D

TM

RO

C b

oard

July

2, 2003

mitch@

hep.u

penn.e

du

39

Barr

el M

odule B

oard

with

15 A

SDBLR /

DTM

ROC

triplets

July

2, 2003

mitch@

hep.u

penn.e

du

40

Noise

Rate

Plot

with B

arr

el

Mod

uleBoa

rdand

Pulse

r

6 M

Hz =

50%

Puls

er

Eff

icie

ncy

(note

that P

uls

er

adds n

ois

e)

July

2, 2003

mitch@

hep.u

penn.e

du

41

Ana

log

and

Digital Readou

t on

the

Barr

el M

odule B

oard

(go

od C

hann

el)

75

ns

50%

Eff

icie

ncy D

ac

Sett

ing

by T

ime

Bin

5m

V/

Dac

~ 2

4 C

ou

nts

/fC

Test Pulse response

July

2, 2003

mitch@

hep.u

penn.e

du

42

Bea

ting

Dow

n Pu

lser

Noise

using

DTM

ROC T

iming

window

50%

Th

resh

old

VS

In

pu

t C

harg

e

0

50

10

0

15

0

20

0

25

0

01

23

45

6

Pu

lse

r in

pu

t C

ha

rge

in

fC

DTMROC DAC counts

Fu

ll 7

5n

s T

ime

Win

do

w

12

ns T

ime

Win

do

w

24C

nts

/ f

C

140m

V / f

C

July

2, 2003

mitch@

hep.u

penn.e

du

43

Test

Beam

Measu

rement

sSpa

tial Reso

lution

S. S

mir

nov

100

140

Rate

MH

z

20

10

July

2, 2003

mitch@

hep.u

penn.e

du

44

Test

Beam P

erf

ormanc

e o

f Pr

oduc

tion

ASIC

S a

nd n

ear

fina

l pr

otot

ype

boa

rds.

S. S

mir

nov

July

2, 2003

mitch@

hep.u

penn.e

du

45

Sum

mary

•ASDBLR

and

DTM

ROC

AS

ICs

are

in p

roduc

tion

and

hav

e bee

n sh

own

to m

eet

TR

T d

esig

n ob

ject

ives

. •

Dev

elop

men

t of

Pro

duc

tion

AS

IC T

esti

ng F

acili

ty is

near

ly f

inis

hed

. •

Des

ign

of B

oard

s w

ith b

oth a

nalo

g an

d d

igit

al A

SIC

S

on t

hem

is

under

way

and

we

hav

e ve

ry p

rom

isin

g re

sult

s to

dat

e.•

Rad

iati

on T

esti

ng o

f A

SD

BLR

AS

ICS

ind

icat

es n

pnne

utro

n se

nsit

ivit

y th

at m

ay li

mit

life

tim

e to

~8

yea

rs

when

saf

ety

fact

ors

are

cons

ider

ed.

•T

her

mal

neu

tron

con

tent

of

TR

T e

nvir

onm

ent

need

s st

udy.