microprocessor lab ii

8/7/2019 Microprocessor LAB II

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Microprocessors &

Microcontrollers

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S omnath DeyA microprocessor incorporates most or all of thefunctions of a computer's central processing unit (CPU)on a single integrated circuit (IC, or microchip). The firstmicroprocessors emerged in the early 1970s and wereused for electronic calculators, using binary-codeddecimal (BCD) arithmetic on 4-bit words. Other

embedded uses of 4-bit and 8-bit microprocessors, suchas terminals, printers, various kinds of automation etc.followed soon after. Affordable 8-bit microprocessorswith 16-bit addressing also led to the first general-purpose microcomputers from the mid-1970s on.



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INTEL 8086 Microprocessor Introduction:

The 8086 was the first 16-bit Microprocessor to be introduced by Intel Corporation. It is designedto be upwardly compatible with the older 8080/8085 series of 8-bit microprocessors. The upwardcompatibility allows programs written for the 8080/8085 to be easily converted to run on the 8086.

The word 16-bit means that its arithmetic logical unit, internal registers, and most of itsinstructions are designed to work with 16-bit binary words. The 8086 has a 16-bit data bus, so itcan read data form or write data to memory and ports either 16-bits or 8- bits at a time. The 8086has a 20-bit address bus, so it can address any one of 220 or 1,048,576 memory locations. Each of the 1,048,576 memory addresses of the 8086 represents a byte-wide location. Words will be storedin two consecutive memory locations. If the first byte of a word is at an even address, the 8086can read the entire word in one operation. If the first byte of the word is at an odd address, the8086 will read the first byte of the word in one operation, and the second byte in another

operation.

Maximum & Minimum Mode:

The 8086 has two modes of operation:

y The Minimum Modey The Maximum Mode

In single processor system, the 8086 operates in the minimum mode of operation. In amultiprocessor& coprocessor configuration, the 8086 operates in the maximum mode of

operation. The status of the pin MN/MX (pin 33) decides the operating mode of 8086. WhenMN/MX =1, the 8086 operates in minimum mode and when MN/MX=0, the 8086 operates inmaximum mode. The 24 pin to 31 pin of 8086 have alternate function.

Hardware Architecture:

The term architecture, as used in microprocessor circuits, describes the functional componentsthat make up the MPU and the interaction between them. These include the temporary storagedevices known as registers, which are used to hold data, instructions, and status information.There are also devices to perform arithmetic and logical operations. Control devices are used tocontrol the flow of information through the MPU.

As shown by the block diagram in Fig.3, the 8086 MPU is divided into two independent functionalparts known as the Execution Unit (EU) and the Bus Interface Unit(BIU).The Bus Interface Unitconsists of segment registers, adder to generate 20 bit address and instruction prefetch queue.

Once this address is sent out of BIU, the instruction and data bytes are fetched from memoryand they fill a First in First out 6 byte queue.



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Bus Interface Unit (BIU)

The BIU is made up of the address generation and bus-control unit, the instruction queue, andthe instruction pointer. It has the task of making sure that the bus is used to its fullest capacityin order to speedup operations. This function is carried in t wo ways. First, by fetching theinstructions before they are needed by the execution unit and storing them in the instructionqueue, the 8086 M

U is able to increase computing speed. Second, by taking care of all bus-control functions, the EU is free to concentrate on processing data and carrying out theinstructions. The instruction pointer contains the location or address of the next instruction tobe executed.

Execution unit (EU):The EU is where the actual processing of data takes place inside the 8086 M

U. It is here thatthe arithmetic and logic unit (ALU) is located, along with the registers used to manipulate dataand store immediate results. The EU accepts instructions and data that have been fetched bythe BIU and then processes the information. Data processed by the EU can be transmitted tothe memory or peripheral devices through the BIU. EU has no direct connection with theoutside world and relies solely on the BIU to feed it with instructions and data as indicated inFig.4.



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It unit consists of scratch pad registers such as 16-bit AX, BX, CX and DX and pointers like SP(Stack Pointer), BP (Base Pointer) and finally index registers such as source index anddestination index registers. The 16-bit scratch pad registers can be split into two 8-bitregisters. For example, AX can be split into AH and AL registers. The segment registers andtheir default offsets are given below.

The Arithmetic and Logic Unit adjacent to these registers perform all the operations. The resultsof these operations can affect the condition flags.

Different registers and their operations are listed below:



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R egisters:

Most of the registers contain data/instruction offsets within 64 KB memory segment. There arefour different 64 KB segments for instructions, stack, data and extra data. To specify where in 1MB of processor memory these 4 segments are located the 8086 microprocessor uses four segment registers:

Code segment (CS) is a 16-bit register containing address of 64 KB segment with processor instructions. The processor uses CS segment for all accesses to instructions referenced byinstruction pointer (IP) register. CS register cannot be changed directly. The CS register isautomatically updated during far jump, far call and far return instructions.

Stack segment (SS) is a 16-bit register containing address of 64KB segment with program stack.By default, the processor assumes that all data referenced by the stack pointer (SP) and basepointer (BP) registers is located in the stack segment. SS register can be changed directly usingPOP instruction.

Data segment (DS) is a 16-bit register containing address of 64KB segment with program data.By default, the processor assumes that all data referenced by general registers (AX, BX, CX, andDX) and index register (SI, DI) is located in the data segment. DS register can be changeddirectly using POP and LDS instructions.

Extra segment (ES) is a 16-bit register containing address of 64KB segment, usually withprogram data. By default, the processor assumes that the DI register references the ES segmentin string manipulation instructions. ES register can be changed directly using POP and LESinstructions.

It is possible to change default segments used by general and index registers by prefixinginstructions with a CS, SS, DS or ES prefix.

All general registers of the 8086 microprocessor can be used for arithmetic and logicoperations. The general registers are:

Accumulator register consists of 2 8-bit registers AL and AH, which can be combined together and used as a 16-bit register AX. AL in this case contains the low-order byte of the word, and AHcontains the high-order byte. Accumulator can be used for I/O operations and stringmanipulation.

Base register consists of 2 8-bit registers BL and BH, which can be combined together and usedas a 16-bit register BX. BL in this case contains the low-order byte of the word, and BH contains

the high-order byte. BX register usually contains a data pointer used for based, based indexedor register indirect addressing.

Count register consists of 2 8-bit registers CL and CH, which can be combined together andused as a 16-bit register CX. When combined, CL register contains the low-order byte of theword, and CH contains the high-order byte. Count register can be used as a counter in stringmanipulation and shift/rotate instructions.



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Data register consists of 2 8-bit registers DL and DH, which can be combined together and usedas a 16-bit register DX. When combined, DL register contains the low-order byte of the word,and DH contains the high-order byte. Data register can be used as a port number in I/Ooperations. In integer 32-bit multiply and divide instruction the DX register contains high-order word of the initial or resulting number.

General and index registers:

Stack Pointer (SP) is a 16-bit register pointing to program stack.

Base Pointer (BP) is a 16-bit register pointing to data in stack segment. BP register is usuallyused for based, based indexed or register indirect addressing.

Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register indirectaddressing, as well as a source data address in string manipulation instructions.

Destination Index (DI) is a 16-bit register. DI is used for indexed, based indexed and register indirect addressing, as well as a destination data address in string manipulation instructions.

Other registers:

Instruction Pointer (IP) is a 16-bit register.



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8086 flag register format:

a) CARRY FLAG ² SET BY CARRY OUT OFMSB

b) PARITY FLAG ² SET IF RESULT HAS EVEN PARITYc) AUXILIARY CARRY FLAG FOR BCDd) ZERO FLAG ² SET IF RESULT = 0e) SIGN FLAG =MSB OF RESULTf) SINGLE STEP TRAP FLAGg) INTERRUPT ENABLE FLAGh) STRING DIRECTION FLAGi) OVERFLOW FLAG

Flag is a 16-bit register containing 9 1-bit flags:

y Overflow Flag (OF) - set if the result is too large positive number, or is too smallnegative number to fit into destination operand.

y Direction Flag (DF) - if set then string manipulation instructions will auto-decrementindex registers. If cleared then the index registers will be auto-incremented.

y Interrupt-enable Flag (IF) - setting this bit enables maskable interrupts.y Single-step Flag (TF) - if set then single-step interrupt will occur after the next

instruction.y Sign Flag (SF) - set if the most significant bit of the result is set.y Zero Flag (ZF) - set if the result is zero.



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y Auxiliary carry Flag (AF) - set if there was a carry from or borrow to bits 0-3 in the ALregister.

y Parity Flag (PF) - set if parity (the number of "1" bits) in the low-order byte of the resultis even.

y Carry Flag (CF) - set if there was a carry from or borrow to the most significant bit duringlast result calculation.

There are three internal buses, namely A bus, B bus and C bus, which interconnect the variousblocks inside 8086. The execution of instruction in 8086 is as follows:

The microprocessor unit (MPU) sends out a 20-bit physical address to the memory and fetchesthe first instruction of a program from the memory. Subsequent addresses are sent

Memory

Program, data and stack memories occupy the same memory space. The total addressablememory size is 1MB. As the most of the processor instructions use 16-bit pointers the

processor can effectively address only 64 KB of memory. To access memory outside of 64 KBthe CPU uses special segment registers to specify where the code, stack and data 64 KBsegments are positioned within 1 MB of memory (see the " R egisters" section above).

16-bit pointers and data are stored as:address: low-order byteaddress+1: high-order byte

32-bit addresses are stored in "segment: offset" format as:

address: low-order byte of segmentaddress+1: high-order byte of segmentaddress+2: low-order byte of offsetaddress+3: high-order byte of offset

Physical memory address pointed by segment: offset pair is calculated as:

address = (<segment> * 16) + <offset>

Program memory - program can be located anywhere in memory. Jump and call instructionscan be used for short jumps within currently selected 64 KB code segment, as well as for far jumps anywhere within 1 MB of memory. All conditional jump instructions can be used to jumpwithin approximately +127 - -127 bytes from current instruction.

Data memory - the 8086 processor can access data in any one out of 4 available segments,which limits the size of accessible memory to 256 KB (if all four segments point to different 64KB blocks). Accessing data from the Data, Code, Stack or Extra segments can be usually doneby prefixing instructions with the DS:, CS:, SS: or ES: (some registers and instructions bydefault may use the ES or SS segments instead of DS segment).



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Word data can be located at odd or even byte boundaries. The processor uses two memoryaccesses to read 16-bit word located at odd byte boundaries. R eading word data from even byteboundaries requires only one memory access.

Stack memory can be placed anywhere in memory. The stack can be located at odd memoryaddresses, but it is not recommended for performance reasons (see "Data Memory" above).

R eserved locations:

y 0000h - 03FFh are reserved for interrupt vectors. Each interrupt vector is a 32-bit pointer in format segment: offset.

y FFFF0h - FFFFFh - after R ESET the processor always starts program execution at theFFFF0h address.

Interrupts

An interrupt is the method of accessing the MPU by a peripheral device. An interrupt is used tocause a temporary halt in the execution of a program. The MPU responds to the interrupt withan interrupt service routine, which is a short program or subroutine that instructs the MPU onhow to handle the interrupt.

When the 8086 is executing a program, it can get interrupted because of one of the following.

1. Due to an interrupt getting activated. This is called as hardware interrupt.2. Due to an exceptional happening during an instruction execution, such as

division of a number by zero. This is generally termed as exceptions or Traps.3. Due to the execution of an Interrupt instruction like "INT 21H". This is called a

Software interrupt.

The action taken by the 8086 is similar for all the three cases, except for minor differences.

There are two basic types of interrupts, maskable and non-maskable. A non-maskable interruptrequires an immediate response by the MPU. It is usually used for serious circumstances likepower failure. A maskable interrupt is an interrupt that the MPU can ignore depending uponsome predetermined condition defined by the status register. Interrupts are also prioritized toallow for the case when more than one interrupts needs to be serviced at the same time.

Hardware interrupts of 8086:

In a microcomputer system whenever an I/O port wants to communicate with themicroprocessor urgently, it interrupts the microprocessor. In such a case, the microprocessor completes the instruction it is presently executing. Then, it saves the address of the nextinstruction on the stack top. Then it branches to an Interrupt Service Subroutine (ISS), toservice the interrupting I/O port. An ISS is also commonly called as an Interrupt Handler. After completing the ISS, the processor returns to the original program, making use of the returnaddress that was saved on the stack top.



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In 8086 there are two interrupt pins. They are NMI and INTR . NMI stands for non maskableinterrupt. Whenever an external device activates this pin, the microprocessor will be interrupted.This signal cannot be masked. NMI is a vectored

In 8086 there are two interrupt pins. They are NMI and INTR

y INTR is a maskable hardware interrupt. The interrupt can be enabled/disabled usingSTI/CLI instructions or using more complicated method of updating the FLAGS register with the help of the POPF instruction. When an interrupt occurs, the processor storesFLAGS register into stack, disables further interrupts, fetches from the bus one byterepresenting interrupt type, and jumps to interrupt processing routine address of whichis stored in location 4 * <interrupt type>. Interrupt processing routine should return withthe IR ET instruction.

y NMI is a non-maskable interrupt. Interrupt is processed in the same way as the INT R interrupt. Interrupt type of the NMI is 2, i.e. the address of the NMI processing routine is

stored in location 0008h. This interrupt has higher priority than the maskable interrupt.

Software interrupts can be caused by:

y INT instruction - breakpoint interrupt. This is a type 3 interrupt.

y INT <interrupt number> instruction - any one interrupt from available 256 interrupts.

y INTO instruction - interrupt on overflow

y Single-step interrupt - generated if the TF flag is set. This is a type 1 interrupt. When theCPU processes this interrupt it clears TF flag before calling the interrupt processing

routine.y Processor exceptions: divide error (type 0), unused opcode (type 6) and escape opcode

(type 7).

Software interrupt processing is the same as for the hardware interrupts.

I/O ports

65536 8-bit I/O ports. These ports can be also addressed as 32768 16-bit I/O ports.



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Instruction SetInstruction set of Intel 8086 processor consists of the following instructions:

y Data moving instructions.y Arithmetic - add, subtract, increment, decrement, convert byte/word and compare.y Logic - AND, OR , exclusive OR , shift/rotate and test.y String manipulation - load, store, move, compare and scan for byte/word.y Control transfer - conditional, unconditional, call subroutine and return from subroutine.y Input/output instructions.y Other - setting/clearing flag bits, stack operations, software interrupts, etc.

Addressing modes:

Implied - the data value/data address is implicitly associated with the instruction.R egister - references the data in a register or in a register pair.

Immediate - the data is provided in the instruction.

Direct - the instruction operand specifies the memory address where data is located.

R egister indirect - instruction specifies a register containing an address, where data is located.This addressing mode works with SI, DI, BX and BP registers.

Based - 8-bit or 16-bit instruction operand is added to the contents of a base register (BX or BP),

the resulting value is a pointer to location where data resides.

Indexed - 8-bit or 16-bit instruction operand is added to the contents of an index register (SI or DI), the resulting value is a pointer to location where data resides.

Based Indexed - the contents of a base register (BX or BP) is added to the contents of an indexregister (SI or DI), the resulting value is a pointer to location where data resides.



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Based Indexed with displacement - 8-bit or 16-bit instruction operand is added to the contentsof a base register (BX or BP) and index register (SI or DI), the resulting value is a pointer tolocation where data resides.

INTEL 8051 Microcontroller Introduction:

There are a wide range of devices available in the 8051 family, di ering in terms of memory typeand capacity, number of counter/timers, types of serial inter-face, number of input/output ports,clock rates, frequency range, etc. However, there is a commonality among all devices in that theyhave been developed from the ¶core· 8051 device with modiÀcations to produce the particular attributes of a di erent family member. Each member of the 8051 microcontroller family has beendesigned with improved device speciÀcations in mind and to provide the customer with a deviceto suit particular user requirements.

The 80c51 can be considered as the core device, and functions such as I/O ports, timer/counters,serial interfacing and interrupts will be discussed. Any variations that exist for a particular familymember will be dealt with in the relevant appendix that covers a particular device.

The 80c51 is available in three di erent package types and is basically a 40-pin device (somepackages have 44 pins but only 40 are internally connected) with the following architecture:

y 4KB 8R OM;y 128 8R AM;y Four 8-bit I/O ports.y full-duplex enhanced UAR T with framing error detection and automatic address

recognition;y three 16-bit counter/timers;y a six-source four-priority level nested interrupt structure;y On-chip oscillator.

Block diagram:

The arrangement for the 80c51 device is shown in the block diagram of Fig.1. Variations existaccording to the family member, i.e. the on-chip program memory could be R OM or EPR OM andthe memory size could vary (the 0C52 has 8KB R OM while the 87C52 has 8KB EPR OM). Also theon-chip data memory size could vary (both the 80C52 and 87C52 devices have 256 bytes of RAM).



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Fig. 1: 8051 Block diagram

Architecture of 8051 Microcontroller:

The 80C51 architecture is shown in Figure 1. The basic architecture is the same for all membersof the 8051 family although there are di erences for devices, which may have more, or less,ports, comparators, ADC circuits, etc. Block diagrams for other relevant devices can be seen inthose appendices that cover their speciÀcation. Reference has already been made in generalterms to the 80C51 ports, timer/counters, internal RA Mand ROM /EPROM(where applicable).



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SpeciÀc features include:

y 8-bit CPU with registers A (accumulator) and By 16-bit program counter (PC)y 16-bit data pointer register (DPT R )y 8-bit program status word register (PSW)y 8-bit stack pointer (SP).

It is clear from the above that the 80C51 has a collection of 8-bit and 16-bit registers and 8-bitmemory locations.

Memory organization:

INTER NALR AM:

The 80C51 has 128 bytes of on-chip R AM plus a number of SFRs. Including the SF R space gives256 addressable locations but the addressing modes for internal R AM can accommodate 384

bytes by splitting the memory space into three blocks viz. the lower 128, the upper 128 and theSFR space. The lower 128 bytes use address locations 00H to 7FH and these can be accessedusing direct and indirect addressing. The upper 128 bytes use address locations 80H to FFH andmay be accessed using direct addressing only; locations in this space with addresses endingwith 0H or 8H are also bit addressable. Some members of the 80C51 family have 256 bytes of on-chip R AM and the upper 128 bytes in this case would be accessible only using the indirectaddressing mode.

For the 80C51 device, the internal RAM of 128 bytes is broken down into:

y Four register banks 0 to 3, each of which contains eight registers R 0 to R 7. The 32 bytesoccupy addresses from 00H to 1FH. Each register can be addressed speciÀcally when

its bank is selected or an address can identify a particular register regardless of thebank, i.e. R 2 of bank 2 can be speciÀed if bank 2 is selected or the same location can bespeciÀed as address 12H. The register banks not selected can be used as general-purpose R AM. Bits 3 and 4 of the PSW register determine which bank is selected when aprogram is running. R eset will cause bank 0 to be selected.

y Sixteen bytes that are bit addressable in the address range 20H to 2FH giving 128addressable bits. The bits have individual addresses ranging from 00H to 07H for byteaddress 20H, to 78H to 7FH for byte address 2FH. Thus a bit may be addressed directly,say bit 78H, which is bit 7 of byte address 2F.

y A general-purpose memory range from 30H to 7FH, which is addressable as bytes.

In addition there are SF R s (special function registers) in the address range 80H to FFH. Thisaddress range actually gives 128 addresses but only 32 are deÀned for the 80C51; thenumberdeÀned varies according to device, being much larger for some devices and lessfor others. Details of the SF R s for the devices referred to in the main body ofthe text can be foundin Appendices D, E and F.For the 80C51 the SF R s of the internal R AM are described in moredetail asfollows:

Accumulator (ACC):



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This 8-bit register, usually referred to as register A, is the major register for data operationssuch as addition, subtraction, etc. and for Boolean bit manipulation. The register is also usedfor data transfers between the device and external memory, where applicable. The accumulator is both bit and byte addressable with the byte address at E0H and the bit addresses from E0H toE7H.

B Register:

This 8-bit register is used for multiplication and division operations. For other instructions it canbe considered another ¶scratch pad register. The B register is both bit and byte addressablewith byte address at F0H and bit addresses from F0H to F7H.

Program status word (PS W):

This 8-bit register at address D0H contains program status information as shown below:

With the bit functions deÀned in Table 1 stated below

Stack pointer (SP):

This 8-bit register at address 81H is incremented before data is stored during PUSH and CALLexecutions. The SP is initialized to RA M address 07H after a reset, which causes the stack tocommence at location 08H.

Data pointer (DP):

This 16-bit register is intended to contain the two bytes that make a 16-bit address, with the highbyte (DPH) at address 83H and the low byte (DPL) at address 82H. It may also be used as twoindependent 8-bit registers.



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Ports 0 to 3 :

P0, P1, P2 and P3 are the 8-bit SFR latches of ports 0, 1, 2 and 3 respectively. The addresses are80H, 90H, A0H and B0H respectively.Writing a ¶1· to any bit of any of the port SFRs causes thecorresponding port output pin to go high; writing a ¶0· causes the corresponding port output pinto go low. When used as an input, the external state of any port pin will be held in the port SFR.

Serial data bu er (SBUF):

This 8-bit register at address 99H is used for serial data in both transmit and receive modes.Moving data to SBUF loads the data ready for transmission while moving data from SBUFallows access to received data.

Timer registers:

The 80C51 contains three 16-bit timer/counters. Timer 0 has a low byte TL0 at address 8AH anda high byte TH0 at address 8CH while timer 1 has a low byte at address 8BH and a high byte ataddress 8DH. Timer 2 has a low byte at address CCH and a high byte at address CDH. Timer 2can operate as an event timer or event counter. An extra SFR register, the T2CON register, ataddress C8H, controls this timer while a timer 2 mode control register T2 MOD is at address C9H.

Control registers:

Certain control registers are required to provide control and status bits for the serial ports,timer/counters and the interrupt system. The 8-bit control registers are:

TCON at address 88H

TMOD at address 89H

SCON at address 98H



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IE at address A8H

IP at address B8H

Timing & Control Unit:

This unit drives all the necessary timing & control signals required for the internal operation of the circuit. It also drives control signals required for controlling the external system bus.

Oscillator:

It generates the basic timing clock signal for the operation of the circuit using crystal oscillator.

Instruction R egister:

It decodes the opcode of an instruction to be executed & gives information to the timing &control unit to generate necessary signals for the execution of the instruction.

EPR OM & Program address register:

These blocks provide an ON-chip EP R OM & a mechanism to internally address it.

R AM &R am address register:

These blocks provide internal 128 bytes of R AM & a mechanism to address it internally.

Arithmetic & Logic Unit (ALU):

ALU performs 8-bit arithmetic & logical operation over the operand held by the temporaryregisters TMP1 & TMP2. Users cannot access these temporary registers.



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Pin-out diagram of 80c51:

The 80C51 microcontroller is available in a 40-pin dual-in-line (DIL) package; the arrangement isshown in Fig.2. Other packages are available and although the device pin functions are thesame regardless of package conÀguration, pin-out numbers vary. The pin-out numbers referredto in the description that follows are valid only for the DIL package.

Figure 2: 80C51 pin-out layout (courtesy Philips Semiconductors)



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Supply voltage (VCC and VSS):

The device operates from a single þ5V supply connected to pin 40 (Vcc) while pin 20 (VSS) isgrounded.

Input/output (I/O) ports:

32 of the pins are arranged as four 8-bit I/O ports P0²P3. Twenty-four of these pins are dualpurpose (26 on the 80C52/80C58) with each capable of operating as a control line or part of thedata/address bus in addition to the I/O functions.

Details are as follows:

y Port 0: This is a dual-purpose port occupying pins 32 to 39 of the device. The port is anopen-drain bidirectional I/O port with Schmitt trigger inputs. Pins that have 1s written tothem Áoat and can be used as high-impedance inputs. The port may be used withexternal memory to provide a multiplexed address and data bus. In this applicationinternal pull-ups are used when emitting 1s. The port also outputs the code bytes duringEPR OM programming. External pull-ups are necessary during program veriÀcation.

y Port 1: This is a dedicated I/O port occupying pins 1 to 8 of the device. The pins areconnected via internal pull-ups and Schmitt trigger input. Pins that have 1s written tothem are pulled high by the internal pull-ups and can be used as inputs; as inputs, pinsthat are externally pulled low will source current via the internal pull-ups. The port alsoreceives the low-order address byte during program memory veriÀcation. Pins P1.0 andP1.1 could also function as external inputs for the third timer/counter i.e.:

(P1.0) T2 Timer/counter 2 external count input/clock-out

(P1.1) T2EX Timer/counter 2 reload/capture/direction control

y Port 2: This is a dual-purpose port occupying pins 21 to 28 of the device. ThespeciÀcation is similar to that of port 1. The port may be used to provide the high -order byte of the address bus for external program memory or external data memory that uses16-bit addresses. When accessing external data memory that uses 8-bit addresses, theport emits the contents of the P2 register. Some port 2 pins receive the high-order address bits during EP R OM programming and veriÀcation.

y Port 3: This is a dual-purpose port occupying pins 10 to 17 of the device. ThespeciÀcation is similar to that of port 1. These pins, in addition to the I/O role, serve thespecial features of the 80C51 family; the alternate functions are summarized below:

P3.0 R xD serial data input port

P3.1 TxD serial data output port P3.2 INT0 external interrupt 0 P3.3 INT1 external interrupt 1 P3.4 T0 timer/counter 0 external input P3.5 T1 timer/counter 1 external input P3.6 WR external data memory writes strobe P3.7 R D external data memory read strobe.



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R eset (pin 9):

The 80C51 is reset by holding this input high for a minimum of two machine cycles beforereturning it low for normal running. An internal resistance connects to pin 20 (V SS) allowing apower-on reset using an external capacitor connected to pin 40 (V CC). The device internalregisters are loaded with selected values prior to normal operation.

XTAL1 and XTAL2 (pins 19 and 18 respectively):

The 80C51 on-chip oscillator is driven, usually, from an external crystal. The XTAL1 input alsoprovides an input to the internal clock generator circuits. PSEN (program store enable) (pin 29).This pin provides an output read strobe to external program memory. The output is active lowduring the fetch stage of an instruction. The signal is not activated during a fetch from internalmemory.

ALE/PR OG (address latch enable/program pulse) (pin 30):

The ALE signal is an output pulse used to latch the low byte of an address during access toexternal memory. The signal rate is 1/6 the oscillator frequency and can be used as a general-purpose clock/timing pulse for the external circuitry. The pin also provides the program pulseinput (PR OG) during EPR OM programming. ALE can be disabled by setting SF R auxiliary.0.With this bit set ALE will be active only during a MOV X instruction

EA/VPP (external access/programming voltage) (pin 31):

This pin is either tied high or low according to circuit requirements. If tied high the device willexecute programs from internal memory provided the address is not higher than the lastaddress in the internal R OM/OTP. When the EA pin is tied low, thus disabling the internal R OM,program code is accessed from external R OM. For a R OMless device the EA pin must be tiedlow permanently and the program code accessed from external R OM could be as much as64KB. EPR OM versions of the device also use this pin for the supply voltage (V PP) necessary for programming the internal EP R OM. If security bit 1 is programmed, EA will be internally latchedon reset.



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Instruction SetData transfer Instruction.

y Move byte between accumulator (an SF R ) and resistor at a resistor bank.y Move byte from an SFR /Internal R AM to another direct.y Move indirect.y Move immediate, mode immediate DPTR .y MOVC and MOVX indirect.y Exchange or Push or Pop direct.

Bit Manipulation:

o Set, Complement, AND or OR or Move the bit.

Logic Instructions:

o AND, XOR , OR operation instructions

Byte Manipulation:

o Clear, Complement, or swap and rotate instructions.

Arithmetic Instructions:

o 8-bit ADD, Subtract, Multiply and Divide instructions.o Increment ²Decrement Instruction.

Program flow control Instructions:

o Branch Instructionso Conditional Jumpso Decrement and Jumps conditionalo Compare and then conditional jumpo Subroutine Call Instructionso Nopo Delay

Interrupt flow control Instructions

o Interrupt flow control-mask bits, priority bits.o R ETI



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INTEL 8086 Program#P1: A block of data transfer from one set of

memory location 136D: 0300 to another set of memory location 136D: 0400.

#P2:8-bit BCD addition or decimal addition of

two data stored in 0300H and 0301H location.

C:\> DEBUG

--A 0100

136D: 0100 MOV SI , 0300

136D: 0103 MOV DI , 0400

136D: 0106 MOV CL , [ SI ]

136D: 0108 INC SI

136D: 0109 MOV AL ,[SI]

136D: 010B MOV [DI ] , AL

136D: 010D INC SI

136D: 010E INC DI

136D: 010F LOOP 0109

136D: 0111 INT3

C:\> DEBUG

--A 0100

136D: 0100 MOV SI , 0300

136D: 0103 MOV AL , [ SI ]

136D: 0105 MOV BL , [SI+1]

136D: 0108 MOV AH , 00

136D: 010A ADD AL , BL

136D: 010C DAA

136D: 010D JNC 0111

136D: 010F INC AH

136D: 0111 INT3



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#P3: To find Factorial of a given data stored inthe location 0300H.

#P4: To find the largest no. in a series of 8-bitdata.

C:\> DEBUG

--A 0100

136D: 0100 MOV AL , 01

136D: 0103 MOV BL , 01

136D: 0106 MOV SI , 0300

136D: 0108 MOV CL,[SI]

136D: 0109 MUL BL

136D: 010B INC BL

136D: 010D LOOP 0109

136D: 010E INT3

C:\> DEBUG

--A 0100

136D: 0100 MOV SI , 0300

136D: 0103 MOV CL , [SI]

136D: 0105 MOV AL , 00

136D: 0107 INC SI

136D: 0108 CMP AL , [SI]

136D: 010A INB 010E

136D: 010C MOV AL , [SI]

136D: 010E LOOP 0107

136D: 0110 MOV [0350] , AL

136D: 0113 INT3



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#P5: To find the largest no. in a series of 8-bitdata.

#P6: To find the smallest no. in a series of 8-bitdata.

C:\> DEBUG

--A 0100

136D: 0100 MOV SI , 0300

136D: 0103 MOV CL , [SI]

136D: 0105 MOV AL , 00

136D: 0107 INC SI

136D: 0108 CMP AL , [SI]

136D: 010A INB 010E

136D: 010C MOV AL , [SI]

136D: 010E LOOP 0107

136D: 0110 MOV [0350] , AL

136D: 0113 INT3

C:\> DEBUG

--A 0100

136D: 0100 MOV SI , 0300

136D: 0103 MOV CL , [SI]

136D: 0105 MOV AL , FF

136D: 0107 INC SI

136D: 0108 CMP AL , [SI]

136D: 010A JB 010E

136D: 010C MOV AL , [SI]

136D: 010E LOOP 0107

136D: 0110 MOV [0350] , AL

136D: 0113 INT3



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Intel 8051 Program#P1: Program to add 5(five) nos. Stored from

memory locations 0030H to 0034H and to storethe result in the resistor R5.

#P2: Program to add 1+2+3....10 and to store the result

in the resistor R5.

ORG 0000H;

MOV A, #00H;

MOVR0, #05H;

MOVR1, #30H

AGAIN: ADD A, @R1;

INCR1;

DJNZR 0, AGAIN;

MOVR5, A;

END;

ORG 0000H;

MOV A, #00H;

MOVR 2, #0AH;

AGAIN: ADD A,R2;

DJNZR2, AGAIN;

MOVR 2, A;

END;

#P3: Program to add 03 by 10 times and tostore the result in the resistor R5.

#P4: Program to move a block of data (5 nos.) fromthe location of starting address 0300H to another location of starting address 0050H.

ORG 0000H;

MOV A, #00H;

MOVR2, #10;

AGAIN: ADD A, #03H;

DJNZR 2, AGAIN;

MOVR1, A;

END;

ORG 0000H;

MOV A, #00H;

MOVR 2, #05H;

MOVR 0, #30H;

MOVR 1, #50H;

AGAIN: MOV A, @R0;

MOV @R

1, A;INCR0;

INCR1;

DJNZR2, AGAIN;

END;



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#P5: Program to find the smallest data in a series(5nos.) starting from the location 0040H. The resultis in ACC.

#06. Program to find the largest data in a series(5 nos.) starting from the location 0040H. Theresult is in ACC.

ORG 0000H;

MOVR0, #40H;

MOVR2, #05H;

MOV A, @R0;

LOOP1: INCR0;

MOV 50H, @R0;

CJNE A, 50H, NEXT;

SJMP LOOP2;

NEXT: JC LOOP2;

MOV A, 50H;

LOOP2: DJNZR 2, LOOP1;

END;

ORG 0000H;

MOVR0, #40H;

MOVR2, #05H;

MOV A, @R0;

LOOP1: NCR0;

MOV 50H, @R 0;

CJNE A, 50H, NEXT;

SJMP LOOP2;

NEXT: JNC LOOP2;

MOV A, 50H;

LOOP2: DJNZR2, LOOP1;

END;

microprocessor lab ii

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