memory system organzation-2.pptx

7/27/2019 Memory System Organzation-2.pptx

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CA Lecture-4


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Organization of computer System

The ISA of a computer describes what a computer cando , but provides no information how to use it.

The ISA describes instructions that a computer canprocess but says nothing about how the processoraccess these instructions.

The system designer needs more information than theISA provides in order to design a complete computersystem.


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Organization

A simple computer has three primary subsystems.

The central processing unit or CPU.

performs many operations and controls the

computer. The Memory Subsystem.

used to store programs along with data.

Input/output or I/O subsystem

allows the CPU to interact with input and output

devices.


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Generic Organization of Computer System


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System busses.

Physically a BUS is a set of wires. The components of the computer are connected to the

Busses.

To send information from one component to another,the source component outputs data onto the bus.

The destination component then inputs this data fromthe bus.

As the complexity of the system grows , it becomesmore efficient to at using busses rather than directconnections between every pair of devices.


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The system shown in the generic diagram has threebusses.

Address bus.

when the CPU read data or instruction from or writes data to memory , it must specify the address

of the memory location it wishes to access.

it outputs this address bus; memory inputs this

address from the address bus and uses it to access

proper memory location.


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Each i/o device , such as such as keyboard , monitor ,or disk drive , has a unique address as well.

When accessing an i/o device, the CPU places theaddress of the device on the address bus.

Each device can read the address off the bus anddetermine whether it is the device being accessed by

the CPU.Address bus receives data from CPU the CPU never

reads the address bus.


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Data bus.

Data is transferred via the data bus.

When CPU fetches data from memory, it first outputs

the memory address on its address bus, then memoryoutputs the data onto the data bus; CPU can then readthe data from data bus.

When writing data to memory, the CPU first outputsthe address onto the address bus, then outputs thedata on data bus. Memory then reads and stores the

data at proper location. The process for reading data from and writing data to

i/o devices is similar.

C l b


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Control bus.

The control bus is different from the other two busses.


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Timing diagram for a) memory read b) memory

write.


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CPU internal organization


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Internal linear organization of an 8 x 2 ROM chip


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Internal two dimensional organization of an 8 x 2 ROM chip


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An 8 x 4 memory subsystem constructed from two 8 x 2 ROM

chip.


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A 16 x 2 memory subsystem constructed from two 8 x 2

ROM chip with a) high order interleaving.


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b) Low order interleaving


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An 8x4 memory subsystem constructed from 8x2 ROM

chip with controlvsignals.


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Little endian

Big endian


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memory system organzation-2.pptx

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