logic gates nand nor

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DIGITAL SYSTEMS Introduction to Logic Gates 1

Digital Electronics

Topic 2:Logic Gates


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Logic Gates

The Inverter The AND Gate The OR Gate The NAND Gate

The NOR Gate The XOR Gate The XNOR Gate

Drawing Logic Circuit

Analysing Logic Circuit

Propagation Delay


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Universal Gates: NAND and NOR

NAND Gate NOR Gate

Implementation using NAND Gates

Implementation using NOR Gates

Implementation of SOP Expressions

Implementation of POS Expressions

Positive and Negative Logic

Integrated Circuit Logic Families


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Logic Gates

Gate Symbols

EXCLUSIVE OR

a

b a.b

a

ba+b

a a'

a

b(a+b)'

a

b(a.b)'

a

b

a b

a

b a.b&

a

ba+b1

AND

a a'1

a

b(a.b)'&

a

b(a+b)'1

a

b

a b=1

OR

NOT

NAND

NOR

Symbol set 1 Symbol set 2

(ANSI/IEEE Standard 91-1984)


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Logic Gates: The Inverter

The InverterA A'

0 11 0

A A' A A'

Application of the inverter: complement.

1

0

0

1

0

1

0

1

1

0

0

1

1

0

1

0

Binary number

1s Complement


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Logic Gates: The AND Gate

The AND Gate

A

BA.B

&A

BA.B

A B A . B

0 0 0

0 1 0

1 0 01 1 1


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Logic Gates: The AND Gate

Application of the AND Gate

1 sec

A

1 sec

Enable

A

EnableCounter

Reset to zero

betweenEnable pulses

Register,decode

andfrequencydisplay


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Logic Gates: The OR Gate

The OR Gate

1AB

A+BA

BA+B

A B A + B

0 0 0

0 1 1

1 0 11 1 1


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Logic Gates: The NAND Gate

The NAND Gate

&A

B(A.B)'

A

B(A.B)'

A

B(A.B)'

A B (A.B)'

0 0 1

0 1 1

1 0 11 1 0 NAND Negative-OR


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Logic Gates: The NOR Gate

The NOR Gate

1AB

(A+B)'A

B(A+B)'

A

B(A+B)'

A B (A+B)'

0 0 1

0 1 0

1 0 01 1 0 NOR Negative-AND


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Logic Gates: The XOR Gate

The XOR Gate

=1A

BA B

A

BA B

A B A B

0 0 0

0 1 1

1 0 11 1 0


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Logic Gates: The XNOR Gate

The XNOR Gate

A

B(A B)'

=1A

B(A B)'

A B (A B)'

0 0 1

0 1 0

1 0 01 1 1


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When a Boolean expression is provided, we can easily drawthe logic circuit.

Examples:

(i) F1 = xyz' (note the use of a 3-input AND gate)

xy

z

F1

z'


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(ii) F2 = x + y'z (can assume that variables and theircomplements are available)

x

y'

z

F2

y'z

(iii) F3 = xy' + x'z

x'z

F3

x'z

xy'x

y'


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Analysing Logic Circuit

When a logic circuit is provided, we can analyse the circuit toobtain the logic expression.

Example: What is the Boolean expression of F4?

A'B'

A'B'+C (A'B'+C)'

A'

B'

CF4

F4 = (A'B'+C)' = (A+B).C'


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Propagation Delay

Every logic gate experiences some delay (though very small)in propagating signals forward.

This delay is called Gate (Propagation) Delay. Formally, it is the average transition time taken for the output

signal of the gate to change in response to changes in the

input signals. Three different propagation delay times associated with a

logic gate:

tPHL: output changing from the High level to Low level

tPLH: output changing from the Low level to High level

tPD=(tPLH + tPHL)/2 (average propagation delay)


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Propagation Delay

Input Output

Output

Input

H

L

L

H

tPHL tPLH


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Propagation Delay

A B C

In reality, output signalsnormally lag behind inputsignals:

1

0

1

0

0

1

time

Signal for C

Signal for B

Signal for A

Ideally, nodelay:

1

0

1

0

0

1

time

Signal for C

Signal for B

Signal for A


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Calculation of Circuit Delays

Amount of propagation delay per gate depends on:

(i) gate type (AND, OR, NOT, etc)

(ii) transistor technology used (TTL,ECL,CMOS etc), (iii) miniaturisation (SSI, MSI, LSI, VLSI)

To simplify matters, one can assume

(i) an average delay time per gate, or

(ii) an average delay time per gate-type.

Propagation delay of logic circuit

= longest time it takes for the input signal(s) to propagate to theoutput(s).

= earliest time for output signal(s) to stabilise, given that inputsignals are stable at time 0.


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In general, given a logic gate with delay, t.

Logic

Gate

t1t2

tn

: :

max (t1, t2, ..., tn ) + t

If inputs are stable at times t1,t2,..,tn, respectively; then theearliest time in which the output will be stable is:

max(t1, t2, .., tn) + t

To calculate the delays of all outputs of a combinationalcircuit, repeat above rule for all gates.

C l l i f Ci i D l


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As a simple example, consider the full adder circuit where allinputs are available at time 0. (Assume each gate has delayt.)

XY S

C

Z

max(0,0)+t = t

t

0

0

0

max(t,0)+t = 2t

max(t,2t)+t = 3t2t

where outputs S and C, experience delaysof 2t and 3t, respectively.


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Universal Gates: NAND and NOR

AND/OR/NOT gates are sufficient for building any Booleanfunctions.

We call the set {AND, OR, NOT} a complete set of logic. However, other gates are also used because:

(i) usefulness

(ii) economical on transistors(iii) self-sufficient

NAND/NOR: economical, self-sufficient

XOR: useful (e.g. parity bit generation)


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NAND Gate

NAND gate is self-sufficient (can build any logic circuit withit).

Therefore, {NAND} is also a complete set of logic.

Can be used to implement AND/OR/NOT.

Implementing an inverter using NAND gate:

x x'

(x.x)' = x' (T1: idempotency)


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NAND Gate

Implementing AND using NAND gates:

x x.yy

(x.y)'

((xy)'(xy)')' = ((xy)')' idempotency= (xy) involution

Implementing OR using NAND gates:

x

x+y

y

x'

y'

((xx)'(yy)')' = (x'y')' idempotency

= x''+y'' DeMorgan= x+y involution


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NOR Gate

NOR gate is also self-sufficient.

Therefore, {NOR} is also a complete set of logic

Can be used to implement AND/OR/NOT.

Implementing an inverter using NOR gate:

x x'

(x+x)' = x' (T1: idempotency)


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NOR Gate

Implementing AND using NOR gates:

((x+x)'+(y+y)')'=(x'+y')' idempotency= x''.y'' DeMorgan

= x.y involution

xx.y

y

x'

y'

((x+y)'+(x+y)')' = ((x+y)')' idempotency= (x+y) involution

Implementing OR using NOR gates:

x x+yy

(x+y)'


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Implementation using NAND gates

Possible to implement any Boolean expression using NANDgates.

Procedure:(i) Obtain sum-of-products Boolean expression:

e.g. F3 = xy'+x'z

(ii) Use DeMorgan theorem to obtain expressionusing 2-level NAND gates

e.g. F3 = xy'+x'z

= (xy'+x'z)' ' involution= ((xy')' . (x'z)')' DeMorgan


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Implementation using NAND gates

x'z

F3

(x'z)'

(xy')'x

y'

F3 = ((xy')'.(x'z)') ' = xy' + x'z


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Implementation using NOR gates

Possible to implement any Boolean expression using NORgates.

Procedure:(i) Obtain product-of-sums Boolean expression:

e.g. F6 = (x+y').(x'+z)

(ii) Use DeMorgan theorem to obtain expressionusing 2-level NOR gates.

e.g. F6 = (x+y').(x'+z)

= ((x+y').(x'+z))' ' involution= ((x+y')'+(x'+z)')' DeMorgan


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Implementation using NOR gates

x'z

F6

(x'+z)'

(x+y')'x

y'

F6 = ((x+y')'+(x'+z)')' = (x+y').(x'+z)


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Sum-of-Products expressions can be implemented using:

2-level AND-OR logic circuits

2-level NAND logic circuits

AND-OR logic circuit

F = AB + CD + E

F

A

B

DC

E


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NAND-NAND circuit (by circuittransformation)

a) add double bubblesb) change OR-with-

inverted-inputs to NAND& bubbles at inputs totheir complements

F

A

B

DC

E

A

B

DC

E'

F


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Product-of-Sums expressions can be implemented using:

2-level OR-AND logic circuits

2-level NOR logic circuits

OR-AND logic circuit

G = (A+B).(C+D).E

G

A

B

DC

E


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NOR-NOR circuit (by circuittransformation):

a) add double bubbles

b) changed AND-with-inverted-inputs to NOR

& bubbles at inputs totheir complements

G

A

B

D

C

E

A

B

DC

E'

G


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Positive & Negative Logic

In logic gates, usually:

H (high voltage, 5V) = 1

L (low voltage, 0V) = 0 This convention positive logic.

However, the reverse convention, negative logic possible:

H (high voltage) = 0 L (low voltage) = 1

Depending on convention, same gate may denote different

Boolean function.


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A signal that is set to logic 1 is said to be asserted, or active,or true.

A signal that is set to logic 0 is said to be deasserted, ornegated, or false.

Active-high signal names are usually written inuncomplemented form.

Active-low signal names are usually written in complementedform.


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Positive logic:

EnableActive High:0: Disabled

1: Enabled

Negative logic:

Enable

Active Low:

0: Enabled1: Disabled

d C l


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Some digital integrated circuit families: TTL, CMOS, ECL.

TTL: Transistor-Transistor Logic.

Uses bipolar junction transistors

Consists of a series of logic circuits: standard TTL, low-powerTTL, Schottky TTL, low-power Schottky TTL, advancedSchottky TTL, etc.

I d Ci i L i F ili


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TTL Series Prefix Designation Example of Device

Standard TTL 54 or 74 7400 (quad NAND gates)

Low-power TTL 54L or 74L 74L00 (quad NAND gates)

Schottky TTL 54S or 74S 74S00 (quad NAND gates)Low-powerSchottky TTL

54LS or 74LS 74LS00 (quad NAND gates)

I d Ci i L i F ili


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CMOS: Complementary Metal-Oxide Semiconductor.

Uses field-effect transistors ECL: Emitter Coupled Logic.

Uses bipolar circuit technology.

Has fastest switching speed but high power consumption.

I d Ci i L i F ili


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Performance characteristics

Propagation delay time.

Power dissipation.

Fan-out: Fan-out of a gate is the maximum number of inputsthat the gate can drive.

Speed-power product (SPP): product of the propagationdelay time and the power dissipation.

S


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Summary

Logic Gates

AND,

OR,

NOT

NAND

NOR

Drawing Logic

Circuit

Analysing

Logic Circuit

Given a Boolean

expression, draw the

circuit.

Given a circuit, find

the function.

Implementation of a

Boolean expressionusing these

Universal gates.

Implementation

of SOP and POS

Expressions

Positive and

Negative Logic

Concept of Minterm

and Maxterm


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End of file

logic gates nand nor

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