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Basic Gates Discussion D2.1

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Page 1: Basic Gates Discussion D2.1. Basic Gates NOT Gate AND Gate OR Gate XOR Gate NAND Gate NOR Gate XNOR Gate

Basic Gates

Discussion D2.1

Page 2: Basic Gates Discussion D2.1. Basic Gates NOT Gate AND Gate OR Gate XOR Gate NAND Gate NOR Gate XNOR Gate

Basic Gates

• NOT Gate

• AND Gate

• OR Gate

• XOR Gate

• NAND Gate

• NOR Gate

• XNOR Gate

Page 3: Basic Gates Discussion D2.1. Basic Gates NOT Gate AND Gate OR Gate XOR Gate NAND Gate NOR Gate XNOR Gate

Y = !XY = not XY = ~XY = X'

Basic Gates

NOT

X Y

01

10

X

YZ

X Y

X Y

Z

AND

OR

X Y Z0 0 00 1 01 0 01 1 1

X Y Z0 0 00 1 11 0 11 1 1

Z = X & YZ = X and YZ = X * Y

Z = XY

Z = X # YZ = X or YZ = X | YZ = X + Y

Any logic circuit can be created using only these three gates

Page 4: Basic Gates Discussion D2.1. Basic Gates NOT Gate AND Gate OR Gate XOR Gate NAND Gate NOR Gate XNOR Gate

NOT Gate

X not X not not X = X

X not X not not X0 1 01 0 1

Behavior:The output of a NOT gate is the inverse (one’s complement) of the input

Page 5: Basic Gates Discussion D2.1. Basic Gates NOT Gate AND Gate OR Gate XOR Gate NAND Gate NOR Gate XNOR Gate

AND Gate

X(1)X(2)

X(n)

ZAND

Behavior:The output of an AND gate is HIGH only if all inputs are HIGH

Z = X(1) and X(2) and …. and X(n)

Page 6: Basic Gates Discussion D2.1. Basic Gates NOT Gate AND Gate OR Gate XOR Gate NAND Gate NOR Gate XNOR Gate

4-Input AND GateX(1)

X(2)

X(3)

X(4)

Z

X(1)

X(2)

X(4)

ZANDX(3)

X(1)

X(2)

X(3)

X(4)

Z

3-Level

2-Level

Behavior:Z := '1';for i in 1 to 4 loop Z := Z and X(i);end loop;

Page 7: Basic Gates Discussion D2.1. Basic Gates NOT Gate AND Gate OR Gate XOR Gate NAND Gate NOR Gate XNOR Gate

std_logic_1164.vhd TYPE std_ulogic IS ( 'U', -- Uninitialized 'X', -- Forcing Unknown

'0', -- Forcing 0 '1', -- Forcing 1 'Z', -- High Impedance

'W', -- Weak Unknown 'L', -- Weak 0 'H', -- Weak 1 '-' -- Don't care );

SUBTYPE std_logic IS resolved std_ulogic;

SUBTYPE UX01 IS resolved std_ulogic RANGE 'U' TO '1'; -- ('U','X','0','1')

Page 8: Basic Gates Discussion D2.1. Basic Gates NOT Gate AND Gate OR Gate XOR Gate NAND Gate NOR Gate XNOR Gate

std_logic_1164.vhd -- truth table for "and" function CONSTANT and_table : stdlogic_table := ( -- ---------------------------------------------------- -- | U X 0 1 Z W L H - | | -- ---------------------------------------------------- ( 'U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U' ), -- | U | ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | X | ( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | 0 | ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 1 | ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | Z | ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | W | ( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | L | ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | H | ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ) -- | - | );

FUNCTION "and" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS BEGIN

RETURN (and_table(l, r)); END "and";

Page 9: Basic Gates Discussion D2.1. Basic Gates NOT Gate AND Gate OR Gate XOR Gate NAND Gate NOR Gate XNOR Gate

OR Gate

Behavior:The output of an OR gate is LOW only if all inputs are LOW

Z = X(1) or X(2) or …. or X(n)

X(1)

X(2)

X(n)

ZOR

Page 10: Basic Gates Discussion D2.1. Basic Gates NOT Gate AND Gate OR Gate XOR Gate NAND Gate NOR Gate XNOR Gate

4-Input OR Gate

X(1)

X(2)

X(4)

ZORX(3)

X(1)

X(2)

X(3)

X(4)

Z

3-Level

2-Level

Behavior:Z := '0';for i in 1 to 4 loop Z := Z or X(i);end loop;

X(1)

X(2)

X(3)

X(4)Z

Page 11: Basic Gates Discussion D2.1. Basic Gates NOT Gate AND Gate OR Gate XOR Gate NAND Gate NOR Gate XNOR Gate

Exclusive-OR (XOR) Gate

Behavior:The output of an XOR gate is HIGH only if the number of HIGH inputs is ODD

Z = X(1) xor X(2) xor …. xor X(n)

X(1)

X(2)

X(n)

ZXOR

Page 12: Basic Gates Discussion D2.1. Basic Gates NOT Gate AND Gate OR Gate XOR Gate NAND Gate NOR Gate XNOR Gate

2-Input XOR Gate

XOR X Y Z0 0 00 1 11 0 11 1 0

Z = X $ YZ = X ^ YZ = X xor YZ = X @ Y

X Y

Z

Note: if Y = 0, Z = Xif Y = 1, Z = not X

Therefore, an XOR gate can be used as a controlled inverter

Z X Y

Page 13: Basic Gates Discussion D2.1. Basic Gates NOT Gate AND Gate OR Gate XOR Gate NAND Gate NOR Gate XNOR Gate

4-Input XOR Gate

X(1)

X(2)

X(4)

ZXORX(3)

X(1)

X(2)

X(3)

X(4)

Z

3-Level

2-Level

Behavior:Z := '0';for i in 1 to 4 loop Z := Z xor X(i);end loop;

X(1)

X(2)

X(3)

X(4)Z

Note: Z = 1 if the number of 1 inputs in ODD

Page 14: Basic Gates Discussion D2.1. Basic Gates NOT Gate AND Gate OR Gate XOR Gate NAND Gate NOR Gate XNOR Gate

NAND Gate (NOT-AND)

Behavior:The output of an NAND gate is LOW only if all inputs are HIGH

Z = not (X(1) and X(2) and …. and X(n))

X(1)

X(2)

X(n)

ZNAND

Page 15: Basic Gates Discussion D2.1. Basic Gates NOT Gate AND Gate OR Gate XOR Gate NAND Gate NOR Gate XNOR Gate

2-Input NAND GateNAND

X

YZ

Z = !(X & Y)Z = X nand YZ = ~(X * Y)

X Y Z0 0 10 1 11 0 11 1 0

Page 16: Basic Gates Discussion D2.1. Basic Gates NOT Gate AND Gate OR Gate XOR Gate NAND Gate NOR Gate XNOR Gate

NOR Gate (NOT – OR)

Behavior:The output of an NOR gate is HIGH only if all inputs are LOW

Z = not (X(1) or X(2) or …. or X(n))

X(1)

X(2)

X(n)

ZNOR

Page 17: Basic Gates Discussion D2.1. Basic Gates NOT Gate AND Gate OR Gate XOR Gate NAND Gate NOR Gate XNOR Gate

2 Input NOR Gate

NOR

XY

Z

Z = !(X # Y)Z = X nor YZ = ~(X + Y)

X Y Z0 0 10 1 01 0 01 1 0

Page 18: Basic Gates Discussion D2.1. Basic Gates NOT Gate AND Gate OR Gate XOR Gate NAND Gate NOR Gate XNOR Gate

NAND Gate

X

Y

X

Y

Z Z

Z = (X * Y)' Z = X' + Y'

=

X Y W Z0 0 0 10 1 0 11 0 0 11 1 1 0

X Y X' Y' Z0 0 1 1 10 1 1 0 11 0 0 1 11 1 0 0 0

Page 19: Basic Gates Discussion D2.1. Basic Gates NOT Gate AND Gate OR Gate XOR Gate NAND Gate NOR Gate XNOR Gate

De Morgan’s Theorem-1

(X * Y)' = X' + Y'

• NOT all variables• Change * to + and + to *• NOT the result

Page 20: Basic Gates Discussion D2.1. Basic Gates NOT Gate AND Gate OR Gate XOR Gate NAND Gate NOR Gate XNOR Gate

NOR Gate

X

YZ

Z = (X + Y)'

X Y Z0 0 10 1 01 0 01 1 0

X

YZ

Z = X' * Y'

X Y X' Y' Z0 0 1 1 10 1 1 0 01 0 0 1 01 1 0 0 0

Page 21: Basic Gates Discussion D2.1. Basic Gates NOT Gate AND Gate OR Gate XOR Gate NAND Gate NOR Gate XNOR Gate

De Morgan’s Theorem-2

(X + Y)' = X' * Y'

• NOT all variables• Change * to + and + to *• NOT the result

Page 22: Basic Gates Discussion D2.1. Basic Gates NOT Gate AND Gate OR Gate XOR Gate NAND Gate NOR Gate XNOR Gate

Exclusive-NOR Gate XNOR (NOT – XOR)

Behavior:The output of an XNOR gate is HIGH only if the number of HIGH inputs is EVEN

Z = not (X(1) xor X(2) xor …. xor X(n))

X(1)

X(2)

X(n)

ZXNOR

Page 23: Basic Gates Discussion D2.1. Basic Gates NOT Gate AND Gate OR Gate XOR Gate NAND Gate NOR Gate XNOR Gate

2-Input XNOR Gate

XNOR X Y Z0 0 10 1 01 0 01 1 1

Z = !(X $ Y)Z = X xnor YZ = ~(X @ Y)

Note: Z = 1 if X = Y

Therefore, an XNOR gate can be used as an equality detector

XY

Z

Z X Y

Page 24: Basic Gates Discussion D2.1. Basic Gates NOT Gate AND Gate OR Gate XOR Gate NAND Gate NOR Gate XNOR Gate

X(0)

X(1)

X(2)

X(3)

Z(1)

Behavior of multiple input gates

andd: process(X)variable Y: STD_LOGIC;begin

Y := '1';for i in 0 to 3 loop

Y := Y and X(i);end loop;Z(1) <= Y;

end process;

Page 25: Basic Gates Discussion D2.1. Basic Gates NOT Gate AND Gate OR Gate XOR Gate NAND Gate NOR Gate XNOR Gate

Behavior of multiple input gates

X(0)’

X(1)’

X(2)’

X(3)’Z(2)

X(0)

X(1)

X(n)

Z(2)NAND=

-- 4-input nand gate -- DeMorgan's Theoremnandd: process(X)variable Y: STD_LOGIC;begin

Y := not X(0);for i in 1 to 3 loop

Y := Y or (not X(i));end loop;Z(1) <= Y;

end process;

Page 26: Basic Gates Discussion D2.1. Basic Gates NOT Gate AND Gate OR Gate XOR Gate NAND Gate NOR Gate XNOR Gate

Behavior of multiple input gates

X(0)

X(1)

X(2)

X(3)Z(3)

X(0)’

X(1)’

X(2)’

X(3)’

Z(4)

orr: process(X)variable Y: STD_LOGIC;begin

Y := '0';for i in 0 to 3 loop

Y := Y or X(i);end loop;Z(3) <= Y;

end process;

norr: process(X)variable Y: STD_LOGIC;begin

Y := not X(0);for i in 1 to 3 loop

Y := Y and (not X(i));end loop;Z(4) <= Y;

end process;

Page 27: Basic Gates Discussion D2.1. Basic Gates NOT Gate AND Gate OR Gate XOR Gate NAND Gate NOR Gate XNOR Gate

xorr: process(X)variable Y: STD_LOGIC;begin

Y := X(0);for i in 1 to 3 loop

Y := Y xor X(i);end loop;Z(5) <= Y;

end process;

xnorr: process(X)variable Y: STD_LOGIC;begin

Y := X(0);for i in 1 to 3 loop

Y := Y xnor X(i);end loop;Z(6) <= Y;

end process;

Behavior of multiple input gatesX(0)

X(1)

X(2)

X(3)Z(5)

X(0)

X(1)

X(2)

X(3)Z(6)

Page 28: Basic Gates Discussion D2.1. Basic Gates NOT Gate AND Gate OR Gate XOR Gate NAND Gate NOR Gate XNOR Gate

andnandornorxorxnor