lecture 8 sequential logic prof. sin-min lee department of computer science
TRANSCRIPT
Lecture 8 Sequential Logic
Prof. Sin-Min Lee
Department of Computer Science
Implement D Flip-flop by T Flip-flop
0 1
0 0
1 1
0 1
0 1
1 0
D T
Q Q
0
1
0
1
T = D Q’ + D’ Q
D
D’
T
Implement JK Flip-flop by D Flip-flop
0 1
0 1
0 0
1 0
1 1
J K
Q
0 0
0 1
1 1
1 0
D = J Q’ + K’ Q
D
0 1
J K
Q
0 0
0 1
1 1
1 0
0 1
0 0
1 0
1 1
D Q+
0
1
0
1
J
K
Q
Q’
Implement JK Flip-flop by T Flip-flop
0 1
0 1
0 0
1 0
1 1
J K
Q
0 0
0 1
1 1
1 0
T = J Q’ + K Q
T
0 1
J K
0 0
0 1
1 1
1 0
0 0
0 1
1 1
1 0
T Q+
0
1
Q
Q’
J
K
Q
Q’
QQ+
J K Q+
0 0
0 1
1 0
1 1
Q
0
1
Q’
Implement T Flip-flop by JK Flip-flop
0 X
1 X
X 1
X 0
J K
0 0
0 1
1 0
1 1
TQ
0
1
0 1
1 0
Q Q+0 1
TQ
0
1
0 X
1 X
0 1 TQ
0
1
X 0
X 1
0 1
J = T K = T
Random-Access Memory
• Can read and write at any point in memory
• Implemented using D Flip-Flops
• Each row contains 16 Flip-Flops
• A Decoder
Binary Counter
• Holds each pulse in memory
• Each pulse add another number
• Binary format
Register
• Used to hold one item of information
• CPU’s have many registers
• AX is an example in Assembly
Clocks and Sequencers
• To perform operations a CPU often requires a specific sequence of sub operations
• A sequencer is used to make sure operations happen in correct order
• A clock is a circuit that outputs 0’s and 1’s at specific frequencies
Real World Application
• The RAM discussed is a model for a chip that can actually be found in a computer
• The binary counter can be bought at http://www.web-tronics.com/webtronics/74hc161n.html for 45 cents each
• The Flip-Flop circuits are models of usable chips
State DiagramsState Diagrams
• A state diagram:– Each state is represented by a circled vertex– Each row of the state table is shown as directed
arc
J’
Y
Important Rule for State Diagram
• State diagram has same situation as state table. Their conditions should be mutually exclusive, no input values should meet the condition of more than one arc.
The Alarm Clock The Alarm Clock
Present state Alarm Weekday Next state Turn off alarm
On X Awake in bed YesAsleep
Awake in bed Off Yes Awake and up No
Awake in bed Off No Asleep No
State Diagram for The Alarm Clock State Diagram for The Alarm Clock (a)(a)
Awake in bedAsleepAlarm’ Alarm
Awake and up
1 (Always)
Alarm
Alarm’ /\ Weekday’ Alarm’ /\ Weekday
Turn off Alarm = Yes
( a )
The alarm clock problem with The alarm clock problem with inactioninaction statesstatesPresent state Alarm Weekday Next state Turn off alarm
Asleep Off X Asleep No
Asleep On Awake in bed Yes
Awake in bed On X Awake in bed yes
Awake in bed Off Yes Awake and up No
Awake in bed Off No Asleep No
Awake and up X X Awake and up No
X
State Diagram for The Alarm ClockState Diagram for The Alarm Clock (b)
( b )
Asleep Awake in bed
Awake and up
Alarm’ / 0
Alarm / 1
Alarm’ /\ Weekday’ / 0
1 (Always) / 0
Alarm’ /\ Weekday / 0
Alarm / 1
1 = yes turn off alarm (output)
0 – no turn off alarm (output)
State Tables for The JK Flip-FlopState Tables for The JK Flip-Flop
( a )
Present State
Y
Z
Z
Z
Z
Y
Y
Y
J K
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Next State Q
Y
Y
Z
Z
Z
Y
Z
Y
0
0
1
1
1
0
1
0
Condition in Terms of J and KCondition in Terms of J and K
Z
J
K
J’ K’
Q=0 Q=1
Y
Mealy and Moore MachinesMealy and Moore Machines
• A finite state machine can represent outputs in one of two ways
– Moore Machines– Mealy Machines
Moore MachinesMoore Machines
– Moore Machines• Associates its outputs with the states.
• Output values depend only on the state and not on the transitions.
• It requires less hardware to produce the output values
• It is well suited for representing the control units of microprocessors and cpu.
State Diagram for The Alarm Clock State Diagram for The Alarm Clock (a)(a)
Awake in bedAsleepAlarm’ Alarm
Awake and up
1 (Always)
Alarm
Alarm’ /\ Weekday’ Alarm’ /\ Weekday
Turn off Alarm = Yes
Moore Machine
Mealy MachinesMealy Machines
– Mealy Machines• Associates outputs with the transitions.
• It depends on both its state and its input values
State Diagram for The Alarm ClockState Diagram for The Alarm Clock (b)
Mealy Machine
Asleep Awake in bed
Awake and up
Alarm’ / 0
Alarm / 1
Alarm’ /\ Weekday’ / 0
1 (Always) / 0
Alarm’ /\ Weekday / 0
Alarm / 1
Designing State DiagramsDesigning State Diagrams
• Counter
• String Checker
• Toll Booth
Modulo 6 CounterModulo 6 Counter
• A modulo 6 counter is a 3-bit counter that counts through the sequence.
– 000 001 010 011 100 101 000…
– 0 1 2 3 4 5 0 …
Unlike a regular 3-bit counter
110(6) and 111(7) do not count
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
State Table for The Modulo 6 CounterState Table for The Modulo 6 CounterPresent State Next State C V2 V1 V0U
S0
S0
S1
S1
S2
S2
S3
S3
S4
S4
S5
S5
1
0
0
1
0
1
0
1
0
1
0
1
S0
S1
S1
S2
S2
S3
S3
S4
S4
S5
S5
S0
1
0
0
0
0
0
0
0
0
0
0
1
0 0 0
0 0 1
0 0 1
0 1 0
0 1 0
0 1 1
0 1 1
1 0 0
1 0 1
1 0 1
0 0 0
1 0 0
State Diagram for The Modulo 6 State Diagram for The Modulo 6 Counter (Mealy)Counter (Mealy)
S0
S5
S1
S4
S2
S3
0 / 1000 0 / 0001 0 / 0010
1 / 0001 1 / 0010
1 / 0011
0 / 0011
1 / 0100
0 / 0100
1 / 0101
0 / 0101
1 / 1000
( a ) Mealy
State Diagram for The Modulo 6 State Diagram for The Modulo 6 Counter (Moore)Counter (Moore)
S5
S0 S1
S4
S2
S3
U’
U’
U’
U’
U’
U’
C=1
V =000
U
C=0
V=0010
U
C=0
V=010
U
C=0
V=011
U
C=0
V=100
U
C=0
V=101
( b ) Moore
String CheckerString Checker
• A String Checker inputs a string of
• bits, one bits per clock cycle.
• It checks bits 1,2, and 2, then 2,3,and 4 and so forever
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
State Table For String CheckerState Table For String CheckerPresent State
S0
S0
S1S1
S2
S2
S3
S3
S4
S4
S5
S5
S6
S6
S7
S7
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
L Next State
S0
S1
S2
S3
S4
S5
S6
S7
S0
S1
S2
S3
S4
S5
S6
S7
M
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
State Diagrams for the String Checker State Diagrams for the String Checker ( Mealy)( Mealy)
S3
S7 S0
S1
S4S6S5
S2
0/0
0/0
0/01/0
1/00/0
0/0
0/01/0
1/0
0/10/1
0/1
1/01/0
1/0
Mealy
State Diagrams for the String State Diagrams for the String Checker (Moore)Checker (Moore)
S7 S0
S6 S5 S4
S3 S2 S1
M=1
I’M=0
I’
I’
M=0I
M=0
IM=0
I
M=0
I
I’
I’
I
I I I’I’ I
I’M=0
M=0
Moore