lecture 21comp. arch. fall 2006 chapter 8: i/o systems (continued) adapted from mary jane irwin at...

Lecture 21 Comp. Arch. Fall 2006

Chapter 8: I/O Systems (continued)

Adapted from Mary Jane Irwin

at Penn State University for Computer Organization and Design, Patterson & Hennessy, © 2005

Computer Organization and Architecture, William Stallings, 7th Edition

Fundamentals of Computer Organization and Design, S. Dandamudi Springer, 2003


A Typical I/O System

Processor

Cache

Memory - I/O Bus

MainMemory

I/OController

Disk

I/OController

I/OController

Graphics Network

Interrupts

Disk


Bus Hierarchy


PCI Bus – Example of a Synchronous Bus

Peripheral Component Interconnection Intel released to public domain 32 or 64 bit 50 lines


PCI Bus Lines (required)

Systems lines Including clock and reset

Address & Data 32 time multiplexed lines for address and data Interrupt & validate lines

Interface Control Arbitration

Not shared Direct connection to PCI bus arbiter

Error lines


PCI Bus Lines (Optional)

Interrupt lines Not shared

Cache support 64-bit Bus Extension

Additional 32 lines Time multiplexed 2 lines to enable devices to agree to use 64-bit transfer

JTAG/Boundary Scan For testing procedures


PCI Commands

Transaction between initiator (master) and target Master claims bus Determine type of transaction

e.g. I/O read/write

Address phase One or more data phases


PCI Read Timing Diagram for a block of size 3

1st – occurs ASAP, 2nd – target not ready for 1 cycle, 3rd – initiator not ready for 1 cycle


PCI Read Timing Diagram

Draw a timing diagram for a PCI read operation (similar to example). Assume that 2 data transfers occur and that the following occurs during these transfers:• during the first data transfer the initiator is not ready for two clock cycles, and • during the second data transfer the target is not ready for one clock cycle.On your diagram clearly indicate:• the address phase, data phase(s) and any wait states• which wire(s) are controlled by the target device and which are controlled by the initiator device • when the “target” reads the data off the bus


The Need for Bus Arbitration Multiple devices may need to use the bus at the same

time so must have a way to arbitrate multiple requests Bus arbitration schemes usually try to balance:

Bus priority – the highest priority device should be serviced first Fairness – even the lowest priority device should never be

completely locked out from the bus

Bus arbitration schemes can be divided into four classes Daisy chain arbitration – see next slide Centralized, parallel arbitration – see next-next slide Distributed arbitration by self-selection – each device wanting the

bus places a code indicating its identity on the bus Distributed arbitration by collision detection – device uses the

bus when its not busy and if a collision happens (because some other device also decides to use the bus) then the device tries again later (Ethernet)


Daisy Chain Bus Arbitration

Advantage: simple Disadvantages:

Cannot assure fairness – a low-priority device may be locked out indefinitely

Slower – the daisy chain grant signal limits the bus speed

BusArbiter

Device 1HighestPriority

Device NLowestPriority

Device 2

Ack Ack Ack

Release

Request

wired-OR

Data/Addr


Centralized Parallel Arbitration

Advantages: flexible, can assure fairness Disadvantages: more complicated arbiter hardware Used in essentially all processor-memory buses and in

high-speed I/O buses

BusArbiter

Device 1 Device NDevice 2

Ack1

Data/Addr

Ack2

AckN

Request1 Request2 RequestN


PCI Bus Arbiter


Motivation for PCI Bus “Hidden” ArbitrationBus Transfer:

1) Request bus

2) Grant bus

3) Address phase

4) One or more data phases

5) Release bus

Sequential Usage:

Time

Bus Usage Device A Bus Usage Device B

Request RequestGrant GrantAddr AddrData DataRelease Release

UsefulWork


PCI Bus “Hidden” Arbitration“Pipelined Usage” - hide overhead of arbitration by doing arbitration for the next bus-master while the current I/O is beingperformed.

Time

Bus Usage Device A

Bus Usage Device A

Bus Usage Device A

Request

Request

Request

Grant

Grant

Grant

Addr

Addr

Addr

Data

Data

Data

Release

Release

Release

UsefulWork


PCI Bus “Hidden” Arbitration


Bus Bandwidth Determinates The bandwidth of a bus is determined by

Whether its is synchronous or asynchronous and the timing characteristics of the protocol used

The data bus width Whether the bus supports block transfers or only word at a

time transfers

Firewire USB 2.0

Type I/O I/O

Data lines 4 2

Clocking Asynchronous Synchronous

Max # devices 63 127

Max length 4.5 meters 5 meters

Peak bandwidth

50 MB/s (400 Mbps)

100 MB/s (800 Mbps)

0.2 MB/s (low) 1.5 MB/s (full) 60 MB/s (high)


USB

Universal Serial Bus Originally developed in 1995 by a consortium including

- Compaq, HP, Intel, Lucent, Microsoft, and Philips USB 1.1 supports

- Low-speed devices (1.5 Mbps)

- Full-speed devices (12 Mbps) USB 2.0 supports

- High-speed devices

– Up to 480 Mbps (a factor of 40 over USB 1.1)

- Uses the same connectors

– Transmission speed is negotiated on device-by-device basis


USB (cont’d)

Motivation for USB Avoid device-specific interfaces

- Eliminates multitude of interfaces

– PS/2, serial, parallel, monitor, microphone, keyboard,… Avoid non-shareable interfaces

- Standard interfaces support only one device

Avoid I/O address space and IRQ problems- USB does not require memory or address space

Avoid installation and configuration problems- Don’t have to open the box to install and configure jumpers

Allow hot attachment of devices


USB (cont’d)

Additional advantages of USB Power distribution

- Simple devices can be bus-powered

– Examples: mouse, keyboards, floppy disk drives, wireless LANs, coffee warmers, reading lights, MP3 players, …

Control peripherals- Possible because USB allows data to flow in both directions

Expandable through hubs Power conservation

- Enters suspend state if there is no activity for 3 ms Error detection and recovery

- Uses CRC


USB (cont’d)

USB encoding Uses NRZI encoding

- Non-Return to Zero-Inverted


USB (cont’d)

NRZI encoding A signal transition occurs if the next bit is zero

- It is called differential encoding

Two desirable properties- Signal transitions, not levels, need to be detected

- Long string of zeros causes signal changes

Still a problem- Long strings of 1s do not causes signal change

To solve this problem- Uses bit stuffing

– A zero is inserted after every six consecutive 1s


USB (cont’d)

Bit stuffing


USB (cont’d)

Transfer types- Four types of transfer

Interrupt transfer- Uses polling

– Polling interval can range from 1 ms to 255 ms Isochronous transfer

- Used in real-time applications that require constant data transfer rate

– Example: Reading audio from CD-ROM

- These transfers are scheduled regularly

- Do not use error detection and recovery


USB (cont’d) Control transfer

- Used to configure and set up USB devices

- Three phases

– Setup stage» Conveys type of request made to target device

– Data stage» Optional stage» Control transfers that require data use this stage

– Status stage» Checks the status of the operation

- Allocates a guaranteed bandwidth of 10%

- Error detection and recovery are used

– Recovery is by means of retries


USB (cont’d)

Bulk transfer- For devices with no specific data transfer rate requirements

– Example: sending data to a printer- Lowest priority bandwidth allocation

- If the other three types of transfers take 100% of the bandwidth

– Bulk transfers are deferred until load decreases- Error detection and recovery are used

– Recovery is by means of retries


USB (cont’d)

USB architecture USB host controller

- Initiates transactions over USB Root hub

- Provides connection points Two types of host controllers

- Open host controller (OHC)

– Defined by Intel- Universal host controller (UHC)

– Specified by National Semiconductor, Microsoft, Compaq- Difference between the two

– How they schedule the four types of transfers


USB (cont’d)

UHC scheduling Schedules periodic transfers first

- Periodic transfers: isochronous and interrupts

- Can take up to 90% of bandwidth

These transfers are followed by control and bulk transfers

- Control transfers are guaranteed 10% of bandwidth

Bulk transfers are scheduled only if there is bandwidth available


USB (cont’d)


USB (cont’d)

OHC scheduling Different from UHC scheduling

Reserves space for non-periodic transfers first

- Non-periodic transfers: control and bulk

- 10% bandwidth reserved

Next periodic transfers are scheduled

- Guarantees 90% bandwidth

Left over bandwidth is allocated to non-periodic transfers


USB (cont’d)

Bus powered devices Low-power

- Less than 100 mA

- Can be bus-powered High-powered

- Between 100 mA and 500 mA

– Full-powered ports can power these devices

- Can be designed to have their own power

- Operate in three modes

– Configured (500 mA)

– Unconfigured (100 mA)

– Suspended ( about 2.5 mA)


USB (cont’d)

USB hubs Bus-powered

- No extra power supply required

- Must be connected to an upstream port that can supply 500 mA

- Downstream ports can only supply 100 mA

– Number of ports is limited to four

– Support only low-powered devices Self-powered

- Support 4 high-powered devices

- Support 4 bus-powered USB hubs

Most 4-port hubs are dual-powered


USB (cont’d)

Hubs can be used to expand

Upstream port

Downstream ports


USB (cont’d)

USB transactions Transfers are done in one or more transactions

- Each transaction consists of several packets Transactions may have between 1 and 3 phases

- Token packet phase

– Specifies transaction type and target device address- Data packet phase (optional)

– Maximum of 1023 bytes are transferred- Handshake packet phase

– Except for isochronous transfers, others use error detection for guaranteed delivery

– Provides feedback on whether data has been received without error


USB (cont’d)

USB IRP frame


USB (cont’d)

Specifies token, data, or handshake packet Complement of type field

Token packets use CRC-5

Hardware encoded special pattern


USB (cont’d)

USB 1.1 transactions


USB (cont’d)

USB 2.0 USB 1.1 uses 1 ms frames USB 2.0 uses 125 s frames

- 1/8 of USB 1.1

Supports 40X data rates - Up to 480 Mbps

Competitive with- SCSI

- IEEE 1394 (FireWire)

Current standard


IEEE 1394

Apple originally developed this standard for high-speed peripherals

Known by a variety of names

- Apple: FireWire

- Sony: i.ILINK

IEEE standardized it as IEEE 1394

- First released in 1995 as IEEE 1394-1995

- A slightly revised version as 1394a

- Next version 1394b

Shares many of the features of USB


IEEE 1394 (cont’d)

Advantages High speed

- Supports three speeds

– 100, 200, 400 Mbps» Competes with USB 2.0

– Plans to boost it to 3.2 Gbps Hot attachment

- Like USB

- No need to shut down power to attach devices Peer-to-peer support

- USB is processor-centric

- Supports peer-to-peer communication without involving the processor


IEEE 1394 (cont’d) Expandable bus

- Devices can be connected in daisy-chain fashion

- Hubs can used to expand Power distribution

- Like the USB, cables distribute power

– Much higher power than USB» Voltage between 8 and 33 V» Current an be up to 1.5 Amps

Error detection and recovery- As in USB, uses CRC

- Uses retransmission in case of error Long cables

- Like the USB


Example: The Pentium 4’s Buses

System Bus (“Front Side Bus”): 64b x 800 MHz (6.4GB/s), 533 MHz, or 400 MHz

2 serial ATAs: 150 MB/s

8 USBs: 60 MB/s

2 parallel ATA: 100 MB/s

Hub Bus: 8b x 266 MHz

Memory Controller Hub (“Northbridge”)

I/O Controller Hub (“Southbridge”)

Gbit ethernet: 0.266 GB/sDDR SDRAM

Main Memory

Graphics output: 2.0 GB/s

PCI: 32b x 33 MHz


Buses in Transition Companies are transitioning from synchronous, parallel,

wide buses to asynchronous narrow buses Reflection on wires and clock skew makes it difficult to use 16

to 64 parallel wires running at a high clock rate (e.g., ~400 MHz) so companies are transitioning to buses with a few one-way wires running at a very high “clock” rate (~2 GHz)

PCI PCIexpress ATA Serial ATA

Total # wires 120 36 80 7

# data wires 32 – 64 (2-way)

2 x 4 (1-way)

16 (2-way)

2 x 2 (1-way)

Clock (MHz) 33 – 133 635 50 150

Peak BW (MB/s) 128 – 1064 300 100 375 (3 Gbps)


ATA Cable Sizes

Serial ATA cables (red) are much thinner than parallel ATA cables (green)


Communication of I/O Devices and Processor How the processor directs the I/O devices

Special I/O instructions- Must specify both the device and the command

Memory-mapped I/O- Portions of the high-order memory address space are assigned to

each I/O device

- Read and writes to those memory addresses are interpretedas commands to the I/O devices

- Load/stores to the I/O address space can only be done by the OS

How the I/O device communicates with the processor Polling – the processor periodically checks the status of an I/O

device to determine its need for service- Processor is totally in control – but does all the work

- Can waste a lot of processor time due to speed differences

Interrupt-driven I/O – the I/O device issues an interrupts to the processor to indicate that it needs attention


Interrupt-Driven Input

memory

userprogram

1. input interrupt

2.1 save state

Processor

ReceiverMemory

addsubandorbeq

lbusb...jr

2.2 jump to interruptservice routine

2.4 returnto user code

Keyboard

2.3 service interrupt

inputinterruptserviceroutine


Interrupt-Driven Output

Processor

TrnsmttrMemory

Display

addsubandorbeq

lbusb...jr

memory

userprogram

1.output interrupt

2.1 save state

outputinterruptserviceroutine

2.2 jump to interruptservice routine

2.4 returnto user code

2.3 service interrupt


Interrupt-Driven I/O An I/O interrupt is asynchronous wrt instruction execution

Is not associated with any instruction so doesn’t prevent any instruction from completing

- You can pick your own convenient point to handle the interrupt

With I/O interrupts Need a way to identify the device generating the interrupt Can have different urgencies (so may need to be prioritized)

Advantages of using interrupts Relieves the processor from having to continuously poll for an I/O

event; user program progress is only suspended during the actual transfer of I/O data to/from user memory space

Disadvantage – special hardware is needed to Cause an interrupt (I/O device) and detect an interrupt and save

the necessary information to resume normal processing after servicing the interrupt (processor)


Direct Memory Access (DMA) For high-bandwidth devices (like disks) interrupt-driven

I/O would consume a lot of processor cycles DMA – the I/O controller has the ability to transfer data

directly to/from the memory without involving the processor1. The processor initiates the DMA transfer by supplying the I/O

device address, the operation to be performed, the memory address destination/source, the number of bytes to transfer

2. The I/O DMA controller manages the entire transfer (possibly thousand of bytes in length), arbitrating for the bus

3. When the DMA transfer is complete, the I/O controller interrupts the processor to let it know that the transfer is complete

There may be multiple DMA devices in one system Processor and I/O controllers contend for bus cycles and for

memory


The DMA Stale Data Problem In systems with caches, there can be two copies of a

data item, one in the cache and one in the main memory For a DMA read (from disk to memory) – the processor will be

using stale data if that location is also in the cache For a DMA write (from memory to disk) and a write-back cache

– the I/O device will receive stale data if the data is in the cache and has not yet been written back to the memory

The coherency problem is solved by1. Routing all I/O activity through the cache – expensive and a

large negative performance impact

2. Having the OS selectively invalidate the cache for an I/O read or force write-backs for an I/O write (flushing)

3. Providing hardware to selectively invalidate or flush the cache – need a hardware snooper (details in Lecture 25)


I/O and the Operating System

The operating system acts as the interface between the I/O hardware and the program requesting I/O

To protect the shared I/O resources, the user program is not allowed to communicate directly with the I/O device

Thus OS must be able to give commands to I/O devices, handle interrupts generated by I/O devices, provide equitable access to the shared I/O resources, and schedule I/O requests to enhance system throughput

I/O interrupts result in a transfer of processor control to the supervisor (OS) process

lecture 21comp. arch. fall 2006 chapter 8: i/o systems (continued) adapted from mary jane irwin at...

Documents

bus slide

bus bus arbitration

bus priority

bus speed bus arbiter

bus hierarchy slide

pci bus arbiter slide

bus extension

bus places