lec14 intro to computer engineering by hsien-hsin sean lee georgia tech -- sequential logic
TRANSCRIPT
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ECE2030 Introduction to Computer Engineering
Lecture 14: Sequential Logic Circuits
Prof. Hsien-Hsin Sean LeeProf. Hsien-Hsin Sean LeeSchool of Electrical and Computer EngineeringSchool of Electrical and Computer EngineeringGeorgia TechGeorgia Tech
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Sequential Logic Circuits
• Sequential circuits – Combinational logic circuits– State information (stored in memory)
• Output is a function of inputs and present state• Can be synchronous or asynchronous
Combinationalcircuits
inputs outputs
StorageElementdelaydelay
Present Present StateState
Next Next StateState
Controller by a periodic clock or an event
trigger
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State machine exampleA TV channel control
CH 2CH 2 CH 3CH 3
CH 1CH 1
0
0
1 1
1
0
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Sequential Logic Circuits
• Synchronous Circuits use clock pulse to synchronize• For a typical synchronous design, data are latched
into the storage upon clock transition (edge-triggered)
Combinationalcircuits
inputs outputs
StorageElement
Present Present StateState
Next Next StateState
clock
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Closed-Loop Logic for Storing Information
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A buffer
Tpd Tpd
XX
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SR Latch
SS
RR
QQQQNN
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SR Latch
S R Q QN
0 0 Q Q0 1 0 11 0 1 01 1 0 0
SS
QQNN
RR
ResetSetUndefined
No Change
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SR Latch
S R Q QN
0 0 1 10 1 1 01 0 0 11 1 Q Q
RR
QQNN
SS
ResetSet
Undefined
No Change
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SR Latch w/ Control
C S R Q QN
0 X X Q Q
1 0 0 Q Q
1 0 1 0 1
1 1 0 1 0
1 1 1 1 1
QQNN
RR
CC
SS
ResetSetUndefined
No ChangeNo Change
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Issue of an SR Latch or SR Latch
SS
QQNN
RR
SS
RR
S R Q QN
0 0 Q Q
0 1 0 1
1 0 1 0
1 1 0 0
QQNN
Race, and UnstableRace, and Unstable
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D LatchQQ
QQNN
CC
DD
C D Q QN
0 X Q Q
1 0 0 1
1 1 1 0
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D Latch Keeping Data for Read
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D Latch Writing Data DD
DD QQ
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10T D Latch w/ Transmission Gates
DD
EnEn
EnEn
EnEn
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10T D Latch w/ Transmission Gates
DD
En=1En=1
EnEn
DD
Writing Data
DD
DDEnEn
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10T D Latch w/ Transmission Gates
D_newD_new
En=0En=0
EnEn
Writing Data
DD
DD
DD
EnEn
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D Latch Symbol
DD
EnEn
En D Q Q0 X NC NC
1 0 0 1
1 1 1 0
NC: No Change
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Latch is Transparent• D Latch is called “transparent” or “level
sensitive”• Output follows input instantaneously
EnEn
DD
Transparent
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Transparency PropertyDD
EnEn
QQTransparent
Latch
DD
EnEn
QQStorage
Cell
00
DD
EnEn
QQStorage
Cell
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Latch acts like a WireLatch acts like a Wire
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Problem of Transparency
• A momentary input change tunnels through the latch and the entire circuitry
• What problem this can cause?
DD
EnEn
QQTransparent Transparent
LatchLatch
Other Logic Other Logic CircuitsCircuits
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Problem of Transparency
EnEn
Transparent Transparent LatchLatch
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DD QQ DD
EnEn
DD
Oscillating Oscillating Unstable Unstable UnstableUnstable
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Eliminating Transparency
• Separating the input and output, so they are independently controlled
• Only open one gate at a time to avoid tunneling
EnEn
Transparent Transparent LatchLatch
DD QQ
EnEn
Transparent Transparent LatchLatch
DD QQ
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Behavior of Master-Slave Latches
EnEn
DD QQ
EnEn
DD QQ
11 00
StorageCell
StorageCell (00)
EnEn
DD QQ
EnEn
DD QQ
00 11
StorageCell (11)
StorageCell
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Behavior of Master-Slave Latches
EnEn
D1D1 Q1Q1
EnEn
D2D2 Q2Q2
EnEn
D1D1(initialized to1)(initialized to1)
D1D1
Q1=D2Q1=D2
Q2Q2
A Toggle Cell, will discuss more later
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Behavior of Master-Slave Latches
EnEn
D1D1 Q1Q1
EnEn
D2D2 Q2Q2
EnEn
D1D1(input)(input)
Q1=D2Q1=D2
Q2Q2
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Behavior of Master-Slave Latches
EnEn
D1D1 Q1Q1
EnEn
D2D2 Q2Q2
EnEn
Q1=D2Q1=D2
Q2Q2
D1D1(input)(input)
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Flip-Flop (F/F)
D1D1 Q1Q1 D2D2 Q2Q2
Enable (or clock)Enable (or clock)
InputInput OutputOutput
Enable Enable (or clock)(or clock)
InputInput OutputOutput1-bit 1-bit Flip FlopFlip Flop
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Negative Edge Triggered Flip-Flop
D1D1 Q1Q1 D2D2 Q2Q2
clockclock
InputInput
Q1=D2Q1=D2
OutputOutput
Enable (or clock)Enable (or clock)
InputInput OutputOutput
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Positive Edge Triggered Flip-Flop
D1D1 Q1Q1 D2D2 Q2Q2
clockclock
Q1=D2Q1=D2
Enable (or clock)Enable (or clock)
InputInput OutputOutput
InputInput
OutputOutput
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Positive Edge Triggered Flip-Flop
D1D1 Q1Q1 D2D2 Q2Q2
clockclock
Q1=D2Q1=D2
Enable (or clock)Enable (or clock)
InputInput OutputOutput
InputInput
OutputOutput
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Flip Flops Symbols
D
C
Q
Q
D
C
Q
Q
Positive Edge TriggeredD Flip Flop
Negative Edge TriggeredD Flip Flop
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Dual-phase Non-overlapped Clocks • In reality, enable control is not ideal• Use dual phase clocks (1 and 2) to
replace Enable and its inversion
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Q1=D2Q1=D2
InputInput
OutputOutput
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D2 follows 1 while Output follows 2
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Dual-Phase Non-overlapped Clocks
D1D1 Q1Q1 D2D2 Q2Q2InputInput OutputOutput
InputInput OutputOutput1-bit 1-bit Flip FlopFlip Flop
11 22
11 22