lec20 intro to computer engineering by hsien-hsin sean lee georgia tech -- data path
TRANSCRIPT
ECE2030 Introduction to Computer Engineering
Lecture 20: Datapath and Microcode Control
Prof. Hsien-Hsin Sean LeeProf. Hsien-Hsin Sean LeeSchool of Electrical and Computer EngineeringSchool of Electrical and Computer EngineeringGeorgia TechGeorgia Tech
22
ISA Implementation• Putting everything together• A Datapath Unit
– Register File A Collection of Registers– Operation Control
• Decoding Instruction• Generating Control Signals to Orchestrate
Hardware– Functional Units
• Arithmetic Units• Logical Units• Memory Units
33
Register File (32 32-bit Registers)32-bit register R0
031Data In Data Out
32-bit register R132-bit register R2
32-bit register R3132-bit register R30
read012
31
w
w
w
w
w
30
Reg encoding
012
3130
Reg encoding
En En
Write Read
44
Register File with Multiple Ports• Xra: X read address• Yra: Y read address• Xdo: X data out• Ydo: Y data out• Zwa: Z write address• Zdi: Z data in• we: write enable• This register file has
– 2 read ports– 1 write port– 32 registers, each 32-
bit
Xra YraZwa
Ydo
XdoZdi
32
32
5 5 5
32 RegFileRegFileClock
we
55
Adder/Subtractor Unit
32 32
Carry in
32Carry
out
Enā/s
0: add1: subtract
FFlagsOverflowZero flag
AA BB
AUAU
66
Logical Unit32 32
32
EnLF
F
AA BB
4
A B F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 10 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 11 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 11 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
A·BAB
A+BA
BĀBA+B
ABA·B
LULU
77
Logical Unit Bit Slice Implementation
LF0
LF1
LF2
LF3
An Bn
An·Bn4-to-1
Mux
0
0
0
1
1
0
0
1
LF0
LF1
LF2
LF3
An Bn
4-to-1
Mux
AnBn
88
Logical Unit Bit Slice Alternative
LF0
LF1
LF2
LF3
01
6
15
An Bn
Fn
4-to-16
Decoder
99
Shift Unit• B = shift amount• Shift Type (ST)
– 00 = no shift– 01 = logical shift– 10 = arithmetic shift– 11 = rotate
• Shift Direction (SD)– 0 = left– 1 = right
32 32
32
EnST
F
AA BB 2
SDSUSU
1010
Combined with Register File
Xra YraZwa
Ydo
XdoZdi
5 5 5
32 RegFileRegFileClock
we32 32
Cin
32Cout
Enā/s
Flags
AA BB
32
32
DatapathDatapath
AUAU
1111
Single Cycle Datapath
Xra YraZwaYdo
XdoZdi
5 5 5
32 RegFileRegFile
Clock
we
Cin
32 Cout
Enā/s
Flags
AA BB
3232
AUAU LFAA BB
LULU STAA BB
SUSU SD
1212
Arithmetic and Logic Unit (ALU)
32 32
ā/sAA BB
ALUALULF
STSD
ALS00: AU01: LU10: SU11: disable ALU
42
2
I omit some input/output e.g. carry, flags etc.
Cin
Cout
Enā/s
Flags
AA BB
AUAU LFAA BB
LULU STAA BB
SUSU SD
1313
Single Cycle DataPath
Xra YraZwa
Ydo
XdoZdi
5 5 5
32 RegFileRegFileClock
we32 32
32
AA BB
32
32
ALUALUā/sLF
STSD
42ALS2
1414
32
32
DataPath with Immediate Input
Xra YraZwa
Ydo
XdoZdi
5 5 5
32 RegFileRegFileClock
we32 32
32
AA BB
ALUALUā/sLF
STSD
42ALS2
Sign-extended immediate
321
0
Immediate Enable
1515
DataPath with Memory
32
32
Xra YraZwaYdo
XdoZdi
5 5 5
32 RegFileRegFile
Clock
we32 32
32
AA BB
ALUALUā/s
LFST
SD
42
ALS2
Sign-extended immediate
3210 Memory
Address
Data
msel r/w
ld enable load $Z, ($X)
st enable
store $Y, ($X)
1616
Instruction Execution• Instruction Fetch
– Given a PC address– Retrieve instruction from memory (or cache)
• Instruction Decode– Instruction type, operands, etc.– Control signals
• Instruction Execute– Functional unit binding
• Instruction Complete– Writeback to register or memory
• Can be done in single cycle or multiple cycles– Instruction complexity (CISC vs. RISC)– Pipelining
1717
Microcode Sequencer• For a multi-cycle implementation or a CISCy ISA
– Think about an x86 “string copy” instruction• An ISA instruction is translated into several
microinstructions or microcode • These microinstructions
– One per cycle– Harness the detailed signals inside a processor – Define low-level control signals in a given state
• Microcode Sequencer– A finite state machine – Generate microinstruction sequence
• Most of RISC instructions is one-to-one mapping• Could be implemented as a ROM or a PLA
1818
Microcode Memory
Datapath Control Signals
State register Needed for a multi-cycleinstruction implementation
Microcode Memory(ROM or PLA)
Combinational Logic
Instruction Register
1919
Microcode Memory
Datapath Control Signals
Microcode Memory(ROM or PLA)
Combinational Logic
Instruction Register
Our Single-Cycle Microcode Memory Assume all steps finish within one cycle No state needed Not really a microcode sequencer
2020
A Simple Processor
X 5Y 5Z 5
imm 16imm_en
weALS 2ā/sLF 4ST 2SDld_enst_enṝ/wmsel
Instruction Register
Microcode
Memory
(Single-Cycle Implementation)
Memory
32
Program Counter
3232
32Next
PC gen
Single CycleDatapath
2121
A Simple Processor
X=00011Y=00010Z=00100imm=0
imm_en=0we=1
ALS=00ā/s=0
LF=0000ST=00SD=0
ld_en=0st_en=0ṝ/w=0
msel=0
Microcode
Memory
Memory
Single CycleDatapath
0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 00 031
opcode rs rt rd26 25 21 20 1615 11 10 6 5 0
shamt funct
add $4, $3, $2add $4, $3, $2
2222
Datapath Control Signals
32
32
Xra YraZwaYdo
XdoZdi
5 5 5
32 RegFileRegFileClock
we32 32
32
AA BB
ALUALUā/s
LFST
SD4422
ALS22
Sign-extended immediate
3210 Memory
Address
Data
msel r/w
ld enable
st enable
imm enable
00: AU01: LU10: SU11: Disable ALU
Shift Type (ST)00: No Shift01: Logical10: Arithmetic11: Rotate
Shift Direction (SD)0: Left1: Right
Logical Flag0001: AND0011: A0101: B0110: XOR0111: OR
2323
Microcode Control (1)• Clear memory location 100, 104 (r0 hardwired to 0)
instruction sequence
X (5) Y (5) Z (5) we
Imm_en
Imm_val ALS ā/s LF ST SD ld_en
st_en
ṝ/w msel
li r1,100sw r0, (r1)
addi r1,r1,4
sw r0, (r1)
ALS00: AU01: LU10: SU11: Disable ALU
Shift Type (ST)00: No Shift01: Logical10: Arithmetic11: Rotate
Shift Direction (SD)0: Left1: Right
Logical Flag (LF)0001: AND0011: A0101: B0110: XOR0111: OR
Datapath Control Signals
2424
Microcode Control (1)• Clear memory location 100, 104 (r0 hardwired to 0)
instruction sequence
X (5) Y (5) Z (5) we
Imm_en
Imm_val ALS ā/s LF ST SD ld_en
st_en
ṝ/w msel
li r1,100 x x 00001
1 1 0x0064 01 x 0101 x x 0 0 x 0
sw r0, (r1) 00001 00000
x 0 0 x 11 x x x x 0 1 1 1
addi r1,r1,4
00001 x 00001
1 1 0x0004 00 0 x x x 0 0 X 0
sw r0, (r1) 00001 00000
x 0 0 x 11 x x x x 0 1 1 1
ALS00: AU01: LU10: SU11: Disable ALU
Shift Type (ST)00: No Shift01: Logical10: Arithmetic11: Rotate
Shift Direction (SD)0: Left1: Right
Logical Flag (LF)0001: AND0011: A0101: B0110: XOR0111: OR
2525
Microcode Control (2)• copy 4-byte data from 0xF000 to 0xA100 • clear data at 0xF000
instruction sequence
X (5) Y (5) Z (5) we
Imm_en
Imm_val ALS ā/s LF ST SD ld_en
st_en
ṝ/w msel
li r5, 0xF000
lw r6, (r5)li r7,
0xA100sw r6, (r7)sw r0, (r5)
ALS00: AU01: LU10: SU11: Disable ALU
Shift Type (ST)00: No Shift01: Logical10: Arithmetic11: Rotate
Shift Direction (SD)0: Left1: Right
Logical Flag (LF)0001: AND0011: A0101: B0110: XOR0111: OR
2626
Microcode Control (2)• copy 4-byte data from 0xF000 to 0xA100 • clear data at 0xF000
instruction sequence
X (5) Y (5) Z (5) we
Imm_en
Imm_val ALS ā/s LF ST SD ld_en
st_en
ṝ/w msel
li r5, 0xF000
X X 00101
1 1 0xF000 01 X 0101 X X 0 0 X 0
lw r6, (r5) 00101
X 00110
1 0 X 11 X X X X 1 0 0 1
li r7, 0xA100
X X 00111
1 1 0xA100 01 X 0101 X X 0 0 X 0
sw r6, (r7) 00111
00110
X 0 0 X 11 X X X X 0 1 1 1
sw r0, (r5) 00101
00000
X 0 0 X 11 X X X X 0 1 1 1
ALS00: AU01: LU10: SU11: Disable ALU
Shift Type (ST)00: No Shift01: Logical10: Arithmetic11: Rotate
Shift Direction (SD)0: Left1: Right
Logical Flag (LF)0001: AND0011: A0101: B0110: XOR0111: OR
2727
Microcode Control (3)• Perform r2 = 5*(r2 – 2*r3) + 3*r4• store r2 to location stored in r10
instruction sequence
X (5) Y (5) Z (5) we
Imm_en
Imm_val ALS ā/s LF ST SD ld_en
st_en
ṝ/w msel
sll r3, r3, 1sub r2, r2,
r3sll r5, r2, 2add r2, r5,
r2sll r6, r4, 1add r4, r6,
r4add r2, r2,
r4sw r2, (r10) ALS
00: AU01: LU10: SU11: Disable ALU
Shift Type (ST)00: No Shift01: Logical10: Arithmetic11: Rotate
Shift Direction (SD)0: Left1: Right
Logical Flag (LF)0001: AND0011: A0101: B0110: XOR0111: OR
2828
Microcode Control (3)• Perform r2 = 5*(r2 – 2*r3) + 3*r4• store r2 to location stored in r10
instruction sequence
X (5) Y (5) Z (5) we
Imm_en
Imm_val ALS ā/s LF ST SD ld_en
st_en
ṝ/w msel
sll r3, r3, 1 00011
X 00011
1 1 0x0001 10 X X 01 0 0 0 X 0
sub r2, r2, r3
00010
00011
00010
1 0 X 00 1 X X X 0 0 X 0
sll r5, r2, 2 00010
X 00101
1 1 0x0002 10 X X 01 0 0 0 X 0
add r2, r5, r2
00101
00010
00010
1 0 X 00 0 X X X 0 0 X 0
sll r6, r4, 1 00100
X 00110
1 1 0x0001 10 X X 01 0 0 0 X 0
add r4, r6, r4
00110
00100
00100
1 0 X 00 0 X X X 0 0 X 0
add r2, r2, r4
00010
00100
00010
1 0 X 00 0 X X X 0 0 X 0
sw r2, (r10) 01010
00010
X 0 0 X 11 X X X X 0 1 1 1
ALS00: AU01: LU10: SU11: Disable ALU
Shift Type (ST)00: No Shift01: Logical10: Arithmetic11: Rotate
Shift Direction (SD)0: Left1: Right
Logical Flag (LF)0001: AND0011: A0101: B0110: XOR0111: OR
2929
Instruction Fetching (PC Update)
Program Counter 32
MemoryInstruction Register 32
Microcode ROMDatapath32x32RegFile
Next PC generation
addr
data
3030
Sequential Instruction Fetch
Program Counter 32+
4
Instruction Register 32
Microcode ROMDatapath32x32RegFile
Memoryaddr
data
3131
Branch Support
Program Counter 32
+
4
beqbne(if true)
ext
01 mux
Instruction Register 32
Microcode ROMDatapath32x32RegFile
Memoryaddr
data
Offset (from Offset (from ROM)ROM)
3232
Branch and Jump Support
Program Counter 32
+
4
beqbne(if true)
ext
Offset (from Offset (from ROM)ROM)
01
01
mux
mux
01 mux
ext
Target addr Target addr (from (from ROM)ROM)
jrj
jr/j
Instruction Register 32
Microcode ROMDatapath32x32RegFile
rs
Memoryaddr
data