Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426

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Layout Design Analysis of XOR Gate by usingTransmission Gates Logic

Nikita AggarwalDepartment of ECE,National Institute of Technical Teachers’ Training & Research Chandigarh, India-

aggarwal.nikita.91@gmail.com

Abstract: This paper concerns with the designing of XORgate based on 90nm technology by using transmission gateslogic. The XOR gate has been implemented and comparing onbasis of semicustom and fully automatic design layouts. Thisproposed XOR gate consists of 3 NMOS and 3 PMOS. TheSchematic of proposed gate has been designed and Stimulatedby using DSCH3.1 and its equivalent layout has beendeveloped and analyzed by using Microwind3.1. After thelayout Simulation, the parametric analysis has been done.The performance of these different designs has been analyzedand compare in terms of power and area. The Simulationresult shows the circuit design of XOR is improved by 68%power and 20% area.

Keywords: XOR logic gate, 90nm technology, powerdissipation & Transmission gates logic.

I. INTRODUCTIONA XOR gate is an electronic logic circuit in the world oftechnology the demand of portable device are increasingday by day. Many applications depend upon XOR gate.Demand and popularity of these devices depend on thesmall silicon area, higher speed, longer better life andreliability. The core of every microprocessor, digital signalprocessor (DSP), and data processing application specificintegrated circuit (ASIC) is its data path. At the hearts ofdata paths and addressing units are arithmetic units, suchas a comparators, adders, and multipliers [1]. A lot of workhas been done in order to accommodate t logic circuitsoperating at low supply voltage (Vdd). Vdd scaling is,however,Obstructed by the minimum operating voltage Vdd(min) ofCMOS logic gates[2]. Vdd (min) is the minimum supplyvoltage that a logic circuit can tolerate without any damage& with increase in logic gates and CMOS technologydown scaling becomes possible, this can achieved byvarying channel length of transistors in such a way that forachieving ultra-low power (< 0.4 V) logic circuitsVdd(min)is reduced with transistor channel length ranging[3].When it reaches a high voltage we do not have to charge itfully. So, energy consumption is low here [4]. In VLSI(Very large scale integration) implementation, majorproblems are heat dissipation and power consumption. Tosolve these problems it is required to reduce power supplyvoltage, switching frequency and capacitance of transistor[5]. A PTL-based circuit that uses only one type of MOStransistor (NMOS), is Complementary pass-transistor logic(CPL). CPL consists of complementary inputs/outputs, aNMOS pass-transistor network, and CMOS outputinverters [6]. Area, delay and power dissipation haveemerged as the major concerns of designers. The gatedelay depends on the capacitive load of the gate. Thedominant term in power dissipation of CMOS circuits is

the power required to charge or discharges the capacitancein the circuit. Thus, by reducing capacitance we candecrease the circuit delay and power dissipation.Capacitance is in turn a function of logic cells being usedin the design [7]. All-optical logic gates are focused on on-off keying (OOK) modulation format. And logic gates forbinary phase-shift keying (BPSK) signals such as XOR,NOR all-optical logic gates are focused on on-off keying(OOK) modulation format. And logic gates for binaryphase shift keying (BPSK) signals such as XOR, NOR [8].As transmission gates logic technique is similar to a relaythat can conduct in both directions or block by a controlsignal with almost any voltage potential. The drawback ina transmission gate is that it needs inverted signal values tocontrol gates of PMOS and NMOS, respectively [9]. Somany famous technologies like 90 nm, 65 nm, 45 nm etc.are currently in working state. In this paper, thecomparison between the semicustom and fully automatichas been discussed based on 90nm technology. I representthe brief introduction of XOR designing by using lessnumber of transistors by using transmission gates logictechnique which helps in improving the speed of any logiccircuit.

II. LOGIC TYPESThe latest technology used for constructing integrated

circuits is CMOS. The technology is being used in variousdigital and analog logic circuits such as image sensors(CMOS sensor), dataconverters, and highly integrated transceivers for manytypes of applications.

Logical representation of CMOS is shown Figure1.

Figure1. Logic diagram of CMOS Logic

The XOR gate is a digital logic gate that implementsan exclusive or; that is, a true output (1/HIGH) results ifone, and only one, of the inputs to the gate is true. If bothinputs are false (0/LOW) and both are true, a false outputresults. XOR represents the inequality function, i.e., theoutput is true if the inputs are not alike otherwise theoutput is false. A way to remember XOR is "one or theother but not both".

Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426

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Table 1. Truth table of XOR gate

A B Y0 0 00 1 11 0 11 1 0

A transmission gate made up of two field effecttransistors, in which - in contrast to traditional discretefield effect transistors - the substrate terminal (Bulk) is notconnected internally to the source terminal. The twotransistors, an n-channel MOSFET and a p-channelMOSFET are connected in parallel with this, however,only the drain and source terminals of the two transistorsare connected together. Their gate terminals are connectedto each other via a NOT gate (inverter), to form the controlterminal. The symbol and truth table of transmission gateslogic is given Figure2(a) & 2(b).

Figure. 2(a) Transmission gate. 2 (b) Truth table

III. XOR SCHEMATIC DESIGNA 2 input XOR gate is designed by using CMOS onMicrowind/DSCH3.1. The Schematic of XOR gateusing Transmission gates logic is shown in figure 3. Byusing Transmission gates logic, the numberof transistors are reduced from the conventional CMOS-XOR gate.

Figure 3. Schematic of XOR

Timing Simulation is performed at Schematic design ofXOR. The timing diagram of proposed 2input XOR which is logically verified at different stages ofthe circuit, is shown in Figure 4.

Figure 4. Timing diagram of XOR

IV. LAYOUT SIMULATIONIn this section, the performance of XOR logic gate basedon transmission logic technique is evaluated on bothsemicustom layout and fully automatic custom layouts.Both the layouts are designed using 90nm technology onMicrowind3.1 CAD Tools. Manually, the layouts ofcombinational circuits sometimes become too difficult. Soby using fully automatic custom technique it becomes easyto design the layouts of typical circuits. In fully automaticcustom layout design is developed from DSCH. TheDSCH program is a logic editor and simulation. It providesone bit comparator using gate is implemented on DSCH[10] then its verilog file is generated which is compiled byMICROWIND to construct its layout that is shown inFigure5. It has been observed that average powerconsumption in fully automatic is 2.183 μW and area is43.7 μm2 .

Figure 5. Fully automatic layout of XOR.

Simulation waveform of XOR gate in fully automaticlayout design is taken by simulate the compiled file ofverilog file as shown in Figure 6. Time domainrepresentation of Layout simulations represents that theLogic ‘0’ corresponds to a zero voltage and logic ‘1’corresponds to 1.2 V.

Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426

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Figure 6. Simulation waveform of fully automatic

In semicustom layout, the design of XOR gate is createdby NMOS and PMOS devices using cell generatorprovided by Microwind3.1 tools as shown in Figure7. Themain advantage of this approach to avoid any design error.It has been observed that average power consumption insemi custom layout design is 1.736μm2 and area is 13.6μm2.

Figure 7. Semicustom layout of XOR gate.

Simulation waveform of XOR gate using Transmissionlogic based on semicustom is shown in Figure 8.

Figure 8. Simulation waveform of semicustom layout design.

V. RESULTS & COMPARISONThe different parameters of XOR gate are comparedbetween semicustom and fully automatic custom based on90nm technology. The Simulation results are shown intable 2.

Table 2. Comparison of simulation results.

S.No.

Parameters Fullycustom

Semicustom

1. Width 8.1 μm 4.4 μm

2. Height 5.4 μm 3.1 μm

3. Area 43.7μm2

13.6 μm2

4. Powerdissipation

2.183μW

1.736μW

VI. CONCLUSIONTransmission gates logic technique based XOR designingis better than the conventional XOR gate due to lessnumber of transistors usages. Both the semicustom andfully automatic custom based layouts have their ownbenefits.The computation results shows that the area of semicustomlayout is improved by 68% from fully automatic layout andpower is increased by 20%, therefore applications wherehigh speed is required, the semicustom design will bepreferred there.

VII. REFERENCES[1] Meena Aggrawal , Aastha Agrawal, Mr. Rajesh Mehra “4 Input

Decimal Adder Using 90 Nm Cmos Technology” Isor Journal OfEngineering (IOSR JEN) Vol 3. Issue 5(May- 2013), pp 48-51

[2] Tadashi Yasufuku1, Satoshi Iida1, Hiroshi Fuketa1, Koji Hirairi2,Masahiro Nomura2, Makoto Takamiya1, And Takayasu Sakurai1,“Investigation Of Determinant Factors Of Minimum OperatingVoltage Of Logic Gates In 65-Nm CMOS”, IEEE,November, 2011,pp 21-26.

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[3] Pooja Singh And Rajesh Mehra, “Design Analysis Of Xor GatesUsing CMOS & Pass Transistor Logic.” International Journal OfEngineering Science Invention Research & Development; Vol. I,Issue I July 2014, pp 1-5

[4] R. Zimmermann And W. Fitcher, “Low Power Logic Styles CmosVersus Pass-Transistor Logic”, IEEE J. Solid State Circuits, Vol 32,July 1997, pp 1079-90.

[5] Richa Singh And Rajesh Mehra, “Power Efficient Design OfMultiplexer Using Adiabatic Logic”, International Journal OfAdvances In Engineering & Technology, March. 2013, pp 247-254.

[6] D. Markovic, B. Nikolic, V.G. Oklobdzija, “A General Method InSynthesis Of Pass-Transistor Circuits”, Microelectronics, Journal 31,2000, pp 991-998.

[7] Rakeshmehrotra, Massoudpedramxunwei Wu, “Comparison BetweenNmos Pass Transistor Logic Style Vs. Cmos Complementary Cells”,IEEE, October 15, 1997, pp 130 – 135.

[8] Deming Kong ; Yan Li ; Hui Wang ; Xinping Zhang ; JunyiZhang ;Jian Wu ; Jintong Lin All-Optical Xor Gates For Qpsk SignalsBased On Four-Wave Mixing In A Semiconductor Optical Amplifier,IEEE, Volume: 24 , Issue: 12 , 2012 , pp- 988 - 990

[9]Swati Sharma, Rajesh Mehra “Area & Power Efficient Design OfXnor-Xor Logic Using 65nm Technology” National Conference OnSynergetic Trends In Engineering And Technology (Stet-2014)International Journal Of Engineering And Technical Research ISSN:2321-0869, Special Issue, pp-1-4

[10] I. Hassoune, D.Flandre, I.O’Connor And J.D. Legat,”Ulpfa:A NewEfficient Design Of Power Aware Full Adder”, IEEE, pp-2066-2074Transactions On Circuits And SystemsI-5438,2008.