layout compaction - elec 5402 - carleton university

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Layout Compaction ELEC 5402 Pavan Gunupudi Dept. of Electronics, Carleton University January 10, 2012 1 / 27

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Page 1: Layout Compaction - ELEC 5402 - Carleton University

Layout CompactionELEC 5402

Pavan Gunupudi

Dept. of Electronics, Carleton University

January 10, 2012

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Page 2: Layout Compaction - ELEC 5402 - Carleton University

Introduction• General goal is to minimize layout area

• Layout is a collection of polygons

• Generally we have rectilinear polygons

• Some technologies allow polygons to have 45-degreesegments

a) b)Rectilinear Polygon 45 degree segments

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Page 3: Layout Compaction - ELEC 5402 - Carleton University

Design Rules

a) Minimum width b) Minimum separation c) Minimum overlap

a)b)

c)

• Can only place rectangles on grid points

• Constraints imposed through design rules

• Constraints for polygons on same layer and different layers

• Expressed as minimum/maximum distance rules

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Page 4: Layout Compaction - ELEC 5402 - Carleton University

Applications of LayoutCompaction

• Removing redundant area from geometric layout

• Adapting geometric layout to new technologies

• If technology changes, design rules change• geometric layout has to be converted to symbolic layout and

then reconverted to geometric layout with new design rules

• Correcting small design rule errors

• Converting symbolic layout to geometric layout

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Page 5: Layout Compaction - ELEC 5402 - Carleton University

Problem Formulation

• Layout is a collection of rectangles

• Two groups of rectangles: rigid and stretchable

• Rigid: e.g. Transistors, contact cuts etc.

• Stretchable: e.g. Wires (not width but length)

• Layout compaction is a 2-D problem

• 2-D layout compaction is NP-Complete (heuristics needed)

• 1-D layout compaction is in P

• Repeated 1-D layout compaction in each dimension is avaluable heuristic for 2-D layout compaction

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Page 6: Layout Compaction - ELEC 5402 - Carleton University

2-D, 1-D Layout Compaction

ABC

HI

D

GFE

(a) (b)

ABC

HI

D

GFE

(c)

A

B

C

HI

D

GFE

A

B

C

H

I

D

GFE

(d)

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Page 7: Layout Compaction - ELEC 5402 - Carleton University

2-D, 1-D Layout Compaction

ABC

HID

GFE

(a) (b)

(f)

(c)

A

B

C

HI

D

GFE

A

B

C

H

I

D

GFE

(d)

A

B

C

H

I

D

GFE

(e)

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Page 8: Layout Compaction - ELEC 5402 - Carleton University

Graph Formulation

x1 x2

x5 x6

x3 x4

• Rigid rectangle - one variable

• Stretchable rectangle - two variables

• Minimum distance rule: xj − xi ≥ dij

x2 − x1 ≥ a; x3 − x2 ≥ b; x3 − x6 ≥ b

x6 − x5 ≥ a; x4 − x3 ≥ a8 / 27

Page 9: Layout Compaction - ELEC 5402 - Carleton University

Constraint Graph

v0

0 v1 v2

v3 v4

v5v6

0

ab

aab

• Vertices of the graph vi => xi (source vertex v0)

• Edges (branches) (vi, vj) with weight w((vi, vj)) = dij foreach inequality xj − xi ≥ dij

• The graph can be denoted as G(V,E); V is the set ofvertices and E is the set of edges

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Page 10: Layout Compaction - ELEC 5402 - Carleton University

Constraint Graph -Solution

v0

0 v1 v2

v3 v4

v5v6

0

ab

aab

• Length of the longest path from v0 to vi gives the minimalx-coordinate xi associated with the vertex vi

• By taking the longest path to vi we make sure that allinequalities in which xi participates are satisfied

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Page 11: Layout Compaction - ELEC 5402 - Carleton University

Maximum-DistanceConstraints

C

W

d

xC

xW

�xC� x

W� � d

• Written as xC − xW ≥ −d and xW − xC ≥ −d• Leads to cycles; solution still longest path

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Page 12: Layout Compaction - ELEC 5402 - Carleton University

Example 1

x1 x2 x3 x4

x5 x6

d1

d2 d2

d2

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Page 13: Layout Compaction - ELEC 5402 - Carleton University

Example 1

x3 − x2 ≥ d1 = 2

x2 − x1 ≥ d2 = 2

x4 − x3 ≥ d2 = 2

x6 − x5 ≥ d2 = 2

v0

v1v2 v3 v4

v5 v6

0

0

2 2 2

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Page 14: Layout Compaction - ELEC 5402 - Carleton University

Example 2

d2 d2

d2

d1

x1 x2 x3 x4

x5 x6

xw

xc

C1 C2

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Page 15: Layout Compaction - ELEC 5402 - Carleton University

Example 2

x3 − x2 ≥ d1 = 1; x2 − x1 ≥ d2 = 2 x4 − x3 ≥ d2 = 2

x6 − x5 ≥ d2 = 2; |xw − xc| ≤ C2 = 0.25; xc − x3 ≥ C1 = 0.5

x4 − xc ≥ C1 = 0.5; xc − x5 ≥ C1 = 0.5; x6 − xc ≥ C1 = 0.5

v1 v2 v3 v4

v5 v6

v0

vc vw-0.25

-0.25

0.5 0.5

0.5 0.5

22

2

1

0

0

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Page 16: Layout Compaction - ELEC 5402 - Carleton University

Longest-Path Algorithmfor DAGs

• Applicable only to directed acyclic graphs (DAGs)

• Set Q contains a list of all vertices vi for which the longestdistance from v0 is known.

• Initially only v0 ∈ Q; Gradually other vertices will beadded.

• Once the vertex is “processed” it is removed from Q

• A variable pi is associated with each vertex vi to keep trackof the vertices incident on vi that still have to be processed

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Page 17: Layout Compaction - ELEC 5402 - Carleton University

Example

v3

v1

v2

v4

v5

v0

1

5

2

2

1

1

4

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Page 18: Layout Compaction - ELEC 5402 - Carleton University

LPA - Example

Q p1 p2 p3 p4 p5 x1 x2 x3 x4 x5φ 1 2 1 2 1 0 0 0 0 0

{v0} 0 1 1 2 1 1 5 0 0 0

{v1} 0 0 1 2 0 1 5 0 0 3

{v2, v5} 0 0 0 1 0 1 5 6 6 3

{v3, v5} 0 0 0 1 0 1 5 6 6 3

{v5} 0 0 0 0 0 1 5 6 7 3

{v4} 0 0 0 0 0 1 5 6 7 3

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Page 19: Layout Compaction - ELEC 5402 - Carleton University

LPA - Pseudocodelongest-path(G)

{

for (i ← 1; i ≤ n; i ← i + 1)

pi ← “in-degree of vi ”;

Q← {v0};

while (Q 6= ∅) {

vi ← “any element from Q”;

Q← Q \{vi };

for each v j “such that” (vi , v j ) ∈ E {

x j ← max(x j , xi + di j );

p j ← p j − 1;

if (p j ≤ 0)

Q← Q ∪ {v j };

}

}

}

main ()

{

for (i ← 0; i ≤ n; i ← i + 1)

xi ← 0;

longest-path(G);

}

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Page 20: Layout Compaction - ELEC 5402 - Carleton University

Directed graphs withcycles

• The previous algorithm only works for acyclic graphs

• Two cases of cyclic graphs

• Negative cycles: Sum of edges in a cycle is negative

• Positive cycles: Sum of edges in a cycle is positive

• Finding longest path for positive cycles is NP-hard• But positive cycle in a layout means conflicting constraints• Such a layout is over-constrained• Detecting positive cycles is enough

• Two algorithms to calculate longest path for negative cyclicgraphs

• Liao-Wong algorithm• Bellman-Form algorithm

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Page 21: Layout Compaction - ELEC 5402 - Carleton University

Example

v3

v1

v2

v4

v5

v0

1

5

2

2

1

1

4

–3

–4

–1

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Page 22: Layout Compaction - ELEC 5402 - Carleton University

Liao-Wong Algorithm

• All edges are partitioned into forward edges Ef andbackward edges Eb

• Ef - Minimum inequality constraints

• Eb - Maximum inequality constraints

• Idea is to start with graph with only Ef edges

• Use the DAG longest path algorithm on it

• Add one edge from Eb, call the DAG longest pathalgorithm again

• Iterate until all the edges in Eb are added

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Page 23: Layout Compaction - ELEC 5402 - Carleton University

Solution - LW

Step x1 x2 x3 x4 x5Initialize −∞ −∞ −∞ −∞ −∞

Forward 1 1 5 6 7 3

Backward 1 2 5 6 7 3

Forward 2 2 5 6 8 4

Backward 2 2 5 7 8 4

Forward 3 2 5 7 8 4

Backward 3 2 5 7 8 4

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Page 24: Layout Compaction - ELEC 5402 - Carleton University

LW - Pseudocodecount← 0;

for (i ← 1; i ≤ n; i ← i + 1)

xi ←−∞;

x0← 0;

do { flag← 0;

longest-path(G f );

for each (vi , v j ) ∈ Eb

if (x j < xi + di j ) {

x j ← xi + di j ;

flag← 1;

}

count← count +1;

if (count > |Eb| && flag)

error(“positive cycle”)

}

while (flag);

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Page 25: Layout Compaction - ELEC 5402 - Carleton University

Bellman-Ford Algorithm

• This does not discriminate between forward and backwardedges

• This algorithm goes through several iterations until itconverges to the longest paths

• First we start with a set S1 containing the source vertex

• Update distances to all the vertices that edges of thisvertex go to: add these new vertices to S1 and remove thesource vertex

• Repeat this process with the vertices present in set S1

• Continue until convergence is attained

• If convergence does not occur in n iterations (n is thenumber of vertices in the graph then it indicates thepresence of positive cycles

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Page 26: Layout Compaction - ELEC 5402 - Carleton University

Solution - BF

S1 x1 x2 x3 x4 x5“not initialized” −∞ −∞ −∞ −∞ −∞

{v0} 1 5 −∞ −∞ −∞{v1, v2} 2 5 6 6 3

{v1, v3, v4, v5} 2 5 6 7 4

{v4, v5} 2 5 6 8 4

{v4} 2 5 7 8 4

{v3} 2 5 7 8 4

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Page 27: Layout Compaction - ELEC 5402 - Carleton University

BF - Pseudocodefor (i ← 1; i ≤ n; i ← i + 1)

xi ←−∞;

x0← 0;

count← 0;

S1← {v0};

S2←∅;

while (count ≤ n && S1 6= ∅) {

for each vi ∈ S1

for each v j “such that” (vi , v j ) ∈ E

if (x j < xi + di j ) {

x j ← xi + di j ;

S2← S2 ∪ {v j }

}

S1← S2;

S2← ∅;

count← count + 1;

}

if (count > n)

error(“positive cycle”);

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