Overview of DigitalDesign Methodologies

ELEC 5402

Pavan Gunupudi

Dept. of Electronics, Carleton University

January 5, 2012

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Introduction

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Introduction

• Driving Areas: Smart phones, mobile devices, computers,communication

• Increased complexity, miniaturization, increased operatingfrequencies

• Moores Law: Exponential - Technology and EDA Tools

• EDA Tools are an integral part of the design cycle

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CAD/EDA Tools

• Once upon a time.. microprocessors were manuallydesigned

• How do you design a circuit with 2 billion transistors??!!

• CAD tools aided in semiconductor electronics development

• Different names: CAD, CAQ, CAP, CAS, CAM (CAX forshort).

• EDA Tools achieve automation using CAX tools.

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Digital Design AbstractionsBEHAVIORAL DOMAIN

PHYSICAL DOMAIN

Physical partitions

Floorplans

Module layout

Cell layout

Transistor layout

Systems

Algorithms

Register transfers

Logic

Transfer functions

Processors

ALU’s, RAM, etc.

Gates, flip-flops, etc.

Transistors

STRUCTURAL DOMAIN

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Advantage of Abstraction

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Design FlowBEHAVIORAL DOMAIN

PHYSICAL DOMAIN

Physical partitions

Floorplans

Module layout

Cell layout

Transistor layout

Systems

Algorithms

Register transfers

Logic

Transfer functions

Processors

ALU’s, RAM, etc.

Gates, flip-flops, etc.

Transistors

STRUCTURAL DOMAIN

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Top Down Design

• Start with an idea

• Creation of specifications

• Create behavioural models (Verilog/VHDL - RTL Desc.)

• Convert the RTL description to gate level netlist(synthesis)

• Iterate between RTL and gate level using simulation

• Convert gate-level netlist to a layout

• Perform place and route

• Iterate between layout level and RTL level

• Design ready to go to fabrication

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First generation EDA Tools• Early layout was manual; polygons were cutout for mask

making

• Berkeley Spice introduced in 1975 laid foundation for EDAtools

• Polygon data for layouts was entered intocomputers/Design rule checks still a burden of the user

• Geometric checks (DRC: Design Rule Check) wereintroduced

• Layout extraction (layout versus schematic check)

• The jump from Boolean equations to Gates/Flip-flops wasmanual

• The jump from Gates/Flip-flops to polygons was alsomanual

• Only verification was automated

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Second Generation

• Started around 80s

• Automatic place and route was introduced

• Logic simulators came into being - Circuits have only threestates (0,1,X=unknown)

• The jump from behavioural to structural to attain a gatelevel netlist was manual

• All other lower level work was automated

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Third Generation

• Automation work started in universities – silicon compiler

• Automate all the way to Silicon – was not so practical

• HDL languages such as VHDL (1987) and Verilog wereintroduced

• Synopsis introduced DesignCompiler (logic synthesis) andHDL compiler (RTL synthesis)

• Acceptance for these tools was slow early on:

• Heavy price tag• Think different: think RTL not schematic• Quality was not as good as manual designs

• Universities taught HDL languages in 90s leading to lateracceptance

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Third Generation –Verification

• Automatic test pattern generation

• Large number of input datasets needed ((2ˆn) inputs +memory)

• Synthesize such that circuit is testable

• Static timing analysis

• Calculates the gate delays along signal path to verify timing• The maximum and minimum delays are considered for

further analysis

• Formal verification

• Verify by constructing original function from synthesizedcircuit

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Fourth Generation –Outlook

• Design Reuse

• Synthesis of RF/analog circuits

• Algorithmic to RTL description

• Signal Integrity

• Multidisciplinary simulation – electrical, optical thermal

• Emerging: Bio-Design-Automation; synthetic biology

Journal: IEEE Transactions on Computer-Aided Design of ICs

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