laporan 3
TRANSCRIPT
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Nama : I Made Wiratha Nungrat
NIM : 13209057
Homework 3
CMOS Inverter design for comparison between NAND and NOR CMOS gate
Inverter Gate design
Figure 1. The schematic diagram of the CMOS inverter with one nMOS at the bottom and one pMOS at the top.
Gate Design
Figure 1. Layout design of Inverter
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Logic Simulation
Figure 2. Voltage vs Time analysis from Inverter
From design above, we can see the waveform is consistent with truth table, so this design was correct and
that rise and fall time is 4 ps
Truth table of CMOS Inverter
Input Logic
Output Logic
0 1
1 0
Analog Input (V)
Analog Output (V)
0.0 1.2
1.2 0.0
Inverter Delay
Rise time from CMOS Inverter is 4 ps
Fall time from CMOS Inverter is 4 ps
Inverter design above was designed from scratch or not using chip generator because the limitation of
default layout. Manual design with strict restriction to design rule, we get (W/L)p = 15, and (W/L)n = 5.
So inverter design for (Wp/Wl) = 15/5 = 3 we got latency or delay 4 ps.
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NAND Gate Design
Figure 3. Gate symbol, Logic gate of NAND and truth table
Gate Design
Figure 4. Layout design of NAND gate
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Logic Simulation
Figure 5. Voltage vs Time analysis from NAND gate
From design above, we can see the waveform is consistent with truth table, so this design was correct and
From design above, we can see that rise and fall time is 4 ps
Truth table of NAND Gate
A B Out
0 0 1
0 1 1
1 0 1
1 1 0
NAND gate Delay
Rise time from NAND gate is 4 ps
Fall time from NAND gate is 4 ps
NAND gate design above was designed from scratch because the goal is to match the delay with inverter.
Manual design with strict restriction to design rule, we get (W/L)p = 6, and (W/L)n = 3. So NAND gate
design for (Wp/Wl) = 6/3 = 2 we got latency or delay 4 ps. This result may not be following the nature of
electron mobility and hole mobility, which is PMOS gate must be at least 3 times of NMOS width. This is
because PMOS gate is arranged with parallel position and NMOS in serial fashion.
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NOR Gate Design
Figure 6. Gate symbol, Logic gate of NOR and truth table
Gate Design
Figure 7. Layout design of NOR gate
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From design above, we can see the waveform is consistent with truth table, so this design was correct and
From design above, we can see that rise and fall time is 6 ps
Truth table of NAND Gate
A B Out
0 0 1
0 1 0
1 0 0
1 1 0
NOR gate Delay
Rise time from NAND gate is 6 ps
Fall time from NAND gate is 6 ps
NOR gate design above was designed from scratch because the goal is to match the delay with inverter.
Manual design with strict restriction to design rule, we get (W/L)p = 17, and (W/L)n = 5. So NOR gate
design for (Wp/Wl) = 17/5 = 3,5 we got latency or delay 6 ps.
Questions
1. Only NAND gate which can match the delay of inverter with 4 ps delay.
(W/L)p = 6
(W/L)n = 3
2. NOR gate have bigger size than NAND gate because the PMOS in NOR gate arranged in serial
fashion