Simulation Lab 5Introduction to VHDL – Mealy / Moore State Machines

NationalScienceFoundation

Funded in part, by a grant from the National Science FoundationDUE 1003736 and 1068182

AcknowledgementsDeveloped by Craig Kief, Alonzo Vera, and Alexandria Haddad, at the Configurable Space Microsystems Innovations & Applications Center (COSMIAC). Based on tutorial developed by Xilinix Corporation. Funded by the National Science Foundation (NSF).

IntroductionThese labs will be using what is known as a Field Programmable Gate Array (FPGA). The FPGA will be on a Digilent Nexys 3 board. FPGAs are different than traditional integrated circuits, because interconnects between the gates are programmable, which means the hardware itself is configurable.

Lab SummaryThis lab will be an introduction to design techniques for FPGAs using a hardware descriptive language (VHDL) design. Xilinx ISE 14.x is the design tool provided by Xilinx for this purpose. Xilinx makes a free version of this tool called Webpack which would be virtually identical for this purpose. The board is a Digilent Nexys 3 board with a Xilinix Spartan 6 XC6LX16-CS324 chip. Please avoid putting your fingers on the chips, as they are extremely electrostatic discharge sensitive.

Lab GoalsTo introduce the student to the concept of Finite State Machines (FSM) using both a Mealy and Moore example. Introduce the student to the difference between sequential and concurrent VHDL.

Learning Objectives1. Learn about Mealy and Moore State Machines

2. Learn about creating custom VHDL types

3. Learn about Process statements and the difference between concurrent and sequential code

4. Learn about if, case, and when statements

Grading CriteriaYour grade is determined by your instructor.

Time Required4 - 5 hours

Special Safety RequirementsWhen working with electronic components, such as the Xilinx FPGA board, there is potential of Electrostatic Discharge (ESD) hazards. Static electricity can damage the FPGA devices used in this lab. Use appropriate ESD methods to protect the devices. No serious hazards are involved in this laboratory experiment, but be careful to connect the components with the proper polarity to avoid damage.

Lab Preparation Review Lab 1-3

Print out the laboratory experiment procedure that follows.

Acquire required hardware components/equipment.

Equipment and MaterialsStudents should work in teams of two or three. Each team of students will need the following supplies:

Supplies Quantity

1. ISE® Design Suite (or WebPACK™ ) software from the Xilinx website, www.xilinx.com, if you don’t already have it installed. Your classroom should have a full working version of Xilinx ISE® Design Suite.

2. FPGA kit including download and power cable(s).

3. Free Digilent Adept software (instructions for download and installation are included at the beginning of this lab): http://www.digilentinc.com/Products/Detail.cfm?NavPath=2,66,828&Prod=ADEPT2

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Additional References The FPGA reference manual, ISE Design Suite User Guide, Digilent Adept User Guide, and any other supporting documents that may be of use.

Nexys 3 Reference Manuel:http://www.digilentinc.com/Data/Products/NEXYS3/Nexys3_rm.pdf

ISE Design Suite User Guide : http://www.xilinx.com/support/index.htm#nav=sd-nav-link-106173&tab=tab-dt

Digilent Adept User Guide: http://www.digilentinc.com/Data/Software/Adept/Adept%20Users%20Manual.pdf

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Lab Procedure (optional): Download and install Digilent Adept SoftwareIn this lab, you download and install Digilent Adept which allows you to communicate with the Digilent FPGA boards that we use in lab. If Adept is already installed on your system, you can skip this Lab Procedure.

Step 1:

Navigate your browser to http://www.digilentinc.com/Products/Detail.cfm?Prod=ADEPT2.

Figure 1. Digilent Adept Website

Step 2:

Click the Download button for Adept 2.9.4 System, 32/64-bit Windows (or latest version) and click Save file when prompted. The installation .exe file will download to your computer.

Step 3:

When the download is complete, run the .exe file and install Adept onto your computer.

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Lab Procedure 1: FPGA Overview from Lab 1 and 2Lab 1 Review: Xilinx Design Process overview:

Figure 2. VHDL Design Process

Step 1: Design Entry Two design methods: 1. HDL (Verilog or VHDL)

or 2. Schematic drawings.

For the simulation part of our class, we will use the schematic method and VHDL.

Step 2: Design Synthesis Translate VHDL and schematic files into an industry standard

format EDIF file.

Step 3: Design Implementation Translate Map, Place and Route. This process will generate a

configuration file (.BIT) for FPGA programming.

Step 4: Xilinx Device Programming Download JED file into FPGA

Lab 2 Review: Nexys 3 overview: NOTE: We used the

Digilent Nexys-3 Xilinx® Spartan 6 XC6LX16-CS324 board. Your board may be a different version or from a different vendor. However, most of the components are similar. If you have a different board, review your board’s documentation.

The Nexys-3 is a powerful digital system design platform built around a Xilinx Spartan 6 FPGA. The advantage of this board is that it is programmed and powered

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through a USB port. A list of the key features and their location on the board are shown in Figure 3.

Figure 3. Nexys 3, Spartan 6 FPGA

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Power

Power good LED

Power Select Jumper

Power Switch

Adept USB Port

10/100 Ethernet

VGA Port

USB HID Host Port

8 Slide switches8 LEDs Push buttons

Pmod Connectors

User I/OThe Nexys-3 board includes several input and output devices, and data ports allowing many implementation designs without the need for any other components. We will focus on the following inputs [slide switches, push buttons, and reset button] and outputs [LEDs, and 7-segment display].

The five pushbuttons and eight slide switches are provided for circuit inputs. There is also a reset button. Pushbuttons normally generate a low output when at rest, driven high when the pushbutton is pressed. Slide switches generate constant high or low inputs depending on their position. Pushbutton and slide switch inputs use a series resistor for protection against short circuits (a short circuit would occur if an FPGA pin assigned to a pushbutton or slide switch was inadvertently defined as an output). Figure 4 shows the pin assignments for each of the aforementioned inputs/outputs. Please refer the reference manual for any additional information.

Figure 4. FPGA Button, Switch, Anode and Cathode SchematicOriginal image from the Nexys3™ Board Reference Manual

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Lab Procedure 2: Creating a Finite State Machine We are using ISE Design Suite 14.x. ISE has the capability of implementing a variety of different design methodologies including: Schematic Capture, Finite State Machines, and Hardware Descriptive Language (VHDL or Verilog). ISE also provides its own simulation tool to test your designs before programming them on the FPGA.

Step 1: Mealy vs. Moore We will be working with two types of Finite State Machines (FSM) for this lab and exploring the difference in the VHDL. State machines are used in software and sequential logic circuits to model systems. Basically, a FSM has a finite number of states that represent the current condition or physical stage of the machine. Another part of the FSM are the conditions that trigger the transition from one state to another. We will be discussing the Mealy and Moore FSMs. The difference between these two FSMs is how the output is determined.

A Mealy FSM determines the output based on the current input and the current state of the machine. A Moore FSM determines the output based only on the current state. As you can see from Figures Figure 5 and Figure 6 this can make a big difference. For this particular FSM, the Mealy machine will light the LED transitioning to the LED_ON state. In the Moore machine the LED illuminates when the current state of the circuit is LED_ON.

Figure 5. Mealy State Machine Figure 6. Moore State Machine

reset current state input next state output1 - - IDLE 00 IDLE START = 0 IDLE 00 IDLE START = 1 LED_ON 10 LED_ON TOGGLE = 1 LED_OFF 00 LED_ON OTHERS IDLE 00 LED_OFF TOGGLE = 1 LED_ON 10 LED_OFF OTHERS IDLE 0

Table 1. Mealy State Machine Output

reset current state input next state output1 - - IDLE 00 IDLE START = 0 IDLE 00 IDLE START = 1 LED_ON 00 LED_ON OTHERS IDLE 10 LED_ON TOGGLE = 1 LED_OFF 10 LED_OFF OTHERS IDLE 00 LED_OFF TOGGLE = 1 LED_ON 0

Table 2. Moore State Machine Output

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Task A: Create a New Project1. Open Xilinx ISE Design Tool Project

Navigator.

Your system might have slightly different Start Menu options.

2. The ISE Project Navigator window opens, with the Tip of the Day displayed. Click OK to close the Tip of the Day.

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3. Start a new project by selecting File New Project from the menu. The New Project Wizard starts.

a. Type LAB5 in the Name text box.

b. Select a location on your computer to save your project files by clicking the ellipsis (…) button to the right of the Location text box.

c. Under Top-level source type, select HDL.

d. Click Next.

The Project Settings dialog box opens.

NOTE: File names must start with a letter. Use underscores ( _ ) for readability. Do not use hyphens (-); although the file name will work, the entity name will not. More on this later.

4. Select Spartan-6 SP601 Evaluation Platform from the Evaluation Development Board drop down menu.

The Product Category, Family, Device, Package, and Speed should all automatically populate (top half of the screen). You will need to set some options in the lower half of the dialog box.

Select VHDL from the Preferred Language drop down menu.

The Project Settings should resemble the figure to the right.

5. Click Next.

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NOTE: The options specified are for the Spartan 6 LX FPGA. Your board might be different than the board used for these instructions. Chip specifications are printed on the FPGA chip in the middle of the board. The board information is also listed on the box it came in.

6. Verify the file type and name are correct in the Project Summary then click Finish to complete the New Project creation process.

NOTE: For this project, the source files have already been created for you. There are four files for this project: Mealy.vhd, Mealy_tb.vhd, Moore.vhd, and Moore_tb.vhd.

The project files are in the lab5.zip file. If you don’t have the zip file you can download it from the COSMIAC website (http://cosmiac.org/Projects_FPGA.html).

7. Using Windows Explorer, extract or move these all five files to your project folder.

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8. Select Project Add Source from the menu or Right-click in the Hierarchy pane and select Add Source from the shortcut menu. The Add Source dialog box opens.

9. Select all four files that were extracted to the project directory earlier. Click the Open button. The Adding Source Files… dialog box opens.

10. Click the OK button to complete the add files process.

NOTE: All four project files display with a green checkmark to the left of the file name. This lets us know that ISE understands the design association of each of the files.

11. The files are added to the LAB5 project. Clicking the Implementation or Simulation options displays the files that were just added.

NOTE: Refer to Labs 1 – 3 for information about the file Hierarchy pane. Recall that when Implementation is selected the UCF file should be below the design file it is associated with. When Simulation is selected, the UUT should be under the associated testbench file.

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Lets take a minute to look at the code we have so far. Figure 7 shows the code for the Mealy state machine, and Figure 8 shows the code for the Moore state machine.

Looking at lines 49 – 53, for example, notice that the Mealy machine code changes the output (op) WHEN the current state is <state_name> and IF the input is <something>.

The Moore machine code on the other hand, using lines 49 – 55 as our example, changes the output (op) WHEN the current state is <state_name>. After changing the output, then the machine changes states.

There are a few other interesting things in this code that we haven’t seen up to this point in our labs, Signals, Processes, IF, WHEN, and CASE statements.

Signals are what allow us to connect our input and output port signals to the internal components of a circuit. We can define signals as any type that we would use to define our input and output ports, such as STD_LOGIC or STD_LOGIC_VECTOR, or we can define our own type, as is done in this code.

Any internal signals must be declared after architecture and before BEGIN in the Architecture block of code. Signals do not have direction, they can be used as either incoming and outgoing.

In these examples, the signal named current_state is of the type state, that can have one of three values: idle, led_on, and led_off. The signal current_state is initialized using the := to the idle value.

The next interesting thing we see is the use of the process statement. Most software programming languages’ code (such as C,

Figure 7. Mealy.vhd

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C++, Java, etc.) runs sequentially. Line 1 runs, then line 2, then line 3, and so on. Of course there are loops and such, but all the code is running in some sort of sequential order. VHDL does not work that way. It is not really a programming language, it is a Hardware Description Language. Everything is executing in parallel, or concurrently, except the lines of code inside of a PROCESS statement.

The lines of code inside of a PROCESS statement run sequentially, however, everything outside of the process runs concurrently (and if there are multiple processes, they run concurrently as well). You can set the process to run only when some signal changes by declaring those signals in the sensitivity list. The sensitivity list is declared in the parenthesis after the word PROCESS.

NOTE: There are several VHDL commands that can only be used concurrently or sequentially. A full discussion of VHDL is outside the scope of this class. There are several sources online, and in print, that discuss these commands in depth.

Inside of both PROCESS statement note the use of conditional statements using IF, ELSIF, CASE, and WHEN statements. Each of these commands can only be used inside of a PROCESS statement sequentially (except WHEN which can be used either concurrently or sequentially).

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Figure 8. Moore.vhd

Task B: Run the Mealy and Moore Simulation1. Select the Simulation pane and

select the Mealy_tb – behavior (Mealy_tb.vhd) file name. Double-click on the “Simulate Behavioral Model”.

2. The simulator will start and the Elaborating status will display. Once the simulation is complete the ISim application window will open.

3. Click the Zoom to Full View

button , then click Zoom In to better view the simulation. The resulting waveform confirms that anytime water and rub are high, meow is also high.

4. Close the ISim Window and return to the ISE Design Window.

5. Select the moore_tb – behavior (moore_tb.vhd) file name. Double-click on the “Simulate Behavioral Model”.

6. The simulator will start and the Elaborating status will display. Once the simulation is complete the ISim application window will open.

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7. Click the Zoom to Full View

button , then click Zoom In to better view the simulation. The resulting waveform confirms that anytime water and rub are high, meow is also high.

8. Close the ISim Window and return to the ISE Design Window.

Task C: Create a UCF (User Constraints File) for the Mealy and Moore State Machines1. In the sources pane, choose

Implementation.

2. Select the Mealy – Behavioral (mealy.vhd) file.

3. Right-click in the hierarchy pane and select New Source.

4. Select Implementation Constraints File from the list of sources and enter FSM as the file name. Click OK.

5. Click Finish.

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NOTE: The file that is designated as the top module is associated with the UCF. The Top Module will have a little hierarchy symbol to the left of the file name.

To set a file as the top module select the file name, and either click the Set Module as Top button or select Set as Top Module from the Source Menu.

We will create a single UCF to use with either of the two state machines. We can do this because they both have the same inputs and outputs. If you had different inputs or outputs you would need to create different UCF files.

6. Enter the text exactly as shown in the figure to the right.

7. Save the file.

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Step 3: Program to the FPGA boardAs mentioned earlier, there are four distinct stages to any FPGA project: Design, Synthesis, Implementation, and Programming. The design portion of this project is now finished. Now we can move on to the Synthesize, Implementation, and Programming stages. We will use the Generate Programming file option to go through all three stages at once.

Task A: Synthesize, Implement, Map, Place and Route, Generate Bitstream (.bit)1. Insert the small end of the USB cable into the Adept

USB Port on the FPGA board. Insert the USB end into your computer.

2. Turn on the FPGA board.

NOTE: The display may alternately flash PASS and 128 if the board’s ROM hasn’t been overwritten from the factory.

3. Select the Mealy.vhd or the Moore.vhd file and then, double-click Generate Programming File.

As the program is going through the compile process the compiling the process status icon spins and displays the current process that is running.

The Console Panel also displays textually what is happening.

4. Once the process has stopped running, and there are no errors or warnings, there will be three green checkmarks next to the Synthesize, Implement Design, and Generate Programming File processes.

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NOTE: If you have errors or warnings you will need to find and fix the errors. You may or may not need to fix warnings. Click the Errors (and/or Warnings) Panel tab to display a list of all errors (and/or warnings) (1).

Clicking the hyperlink (2) of a particular Error (or Warning) will take you to the file and line (3) of the Error (or Warning). Note in the example the semicolon is missing at the end of line 37.

Clicking the hyperlink word Error (4) (or Warning) will display context sensitive information about the particular error/warning.

After fixing any errors, re-generate the programming file. To re-generate the programming file, right-click on Generate Programming File and select Rerun All.

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Task B: Implement design to FPGA boardFinally, we will start the “Digilent Adept” program. Adept is the software provided by Digilent that allows us to communicate through the JTAG chain to the programming pins on the FPGA. Because the FPGAs we are working with use a single USB cable for power and PC connection we need to use Digilent Adept to transfer the .bit code to the board.

1. Open Digilent Adept by selecting Start All Programs Digilent Adept Adept.

NOTE: Your system might have slightly different Start Menu options.

2. Choose Nexys3 from the Connect Product drop down menu.

NOTE: If you do not see Nexys3 as an option, check the USB connection to ensure the board is connected to the computer.

3. Click the Browse button. The Open dialog box displays.

4. Navigate to the folder of the Full_Adder project and select the full_adder.bit file.

5. Click the Open button. The file is displayed in the dropdown list next to the FPGA icon.

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6. Click the Program button. The bit file is programmed to the FPGA board. The green status bar at the bottom of the Adept screen displays the status as the chip is programmed.

7. The program gets downloaded to the FPGA board.

8. Test the FPGA by sliding the programmed switches ON (up toward the middle of the board) and OFF (down toward the edge of the board). Use the center button to reset the machine

9. Repeat Procedure 3, Tasks A and B for the Moore.vhd.

NOTE: Remember you will need to set the Moore.vhd file as the top level module before Generating the Program File.

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