kalpakjian 16

ERPTACH

28.1 Introduction 790

28.2 Clean Rooms 79328.3 Semiconductors

and Silicon 79428.4 Crystal Growing and

Wafer Preparation 79528.5 Film Deposition 79828.6 Oxidation 79928.7 Lithography 800

28.8 Etching 80828.9 Diffusion and lon

lmplantation 81628.I0 Metallization and

Testing 81828.11 Wire Bonding and

Packaging 82028.I2 Yield and Reliability 82528.13 Printed Circuit

Boards 826

EXAMPLES:

28.1 Moore’s Law 80628.2 Comparison of Wet and

Dry Etching 81528.3 Processing of a p-type

Region in n-typeSilicon 817

790

Fabrication ofMicroelectronicDevices

' This chapter presents the science and the technologies involved in the productionof integrated circuits, a product that has fundamentally changed our society.

° The chapter begins by examining silicon, the preferred material for most inte-grated circuits, and its unique properties that make it attractive.

° Beginning with a cast ingot, the machining operations required to produce a

wafer are described.

° Next, the production of patterns on wafers is discussed, including the processesof lithography, wet and dry etching, and doping.

° Metallization and testing are then described, as are the approaches forobtaining electrical connections from integrated circuits to circuit boards.

° The chapter concludes with a description of the different packages used forintegrated circuits.

Typical parts produced: Computer processors, memory chips, printed circuitboards, and integrated circuits of all types.

28.1 Introduction

Although semiconducting materials have been used in electronics for a long time, it

was the invention of the transistor in 1947 that set the stage for what would becomeone of the greatest technological advancements in all of history. Microelectronicshas played an increasing role in our lives ever since integrated circuit (IC) technologybecame the foundation for calculators, Wrist watches, controls for home appliancesand automobiles, information systems, telecommunications, robotics, space travel,Weaponry, and personal computers.

The major advantages of today’s ICs are their very small size and low cost. As

fabrication technology becomes more advanced, the size of devices made (such as

transistors, diodes, resistors, and capacitors) continues to decrease. Consequently,more components can be put onto a chip-a small piece of semiconducting materialon which the circuit is fabricated. In addition, mass production and automationhave helped reduce the cost of each completed circuit.

Typical chips produced today have sizes that are as small as 0.5 >< 0.5 mmand, in rare cases, can be more than 50 >< 50 mm. In the past, no more than 100

Section 28 1 Introduction

(H) (D)

(C) (G)

FIGURE 28.| (a) A 300-mm Wafer with a large number of dies fabricated onto its surface;(b) detail view of an Intel 45-nm chip, including a 153-Mbit SRAM (static random accessmemory) and logic test circuits; (c) image of the Intel® Itanium® 2 processor; and(d) Pentium® processor motherboard. Source: Courtesy of Intel Corporation.

devices could be fabricated on a single chip; new technologies now allow densities inthe range of 10 million devices per chip (Fig. 28.1). This magnitude of integration hasbeen termed very large scale integration (VLSI). Some of the most advanced ICs maycontain more than 100 million devices, termed ultralarge-scale integration (ULSI). TheIntel Itanium® processors, for example, recently surpassed 2 billion transistors.

More recent advances include wafer-scale integration (WSI), in which an entiresilicon Wafer is used to build a single device. This approach has been of greatest inter-est in the design of massively parallel supercomputers, including three-dimensionalintegrated circuits, (3DICs) Which use multiple layers of active circuits that maintainconnections both horizontally and vertically.

This chapter describes the processes that are currently in use in the fabricationof microelectronic devices and integrated circuits and that follow the outline shovvnin Fig. 28.2. The major steps in fabricating a metal-oxide-semiconductor field-effecttransistor (MOSFET), Which is one of the dominant devices used in modern IC tech-nology, are shovvn in Fig. 28.3.

(a) Single-crystal growing

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FIGURE 28.2 Outline of the general fabrication sequence for integrated circuits.

Section 28 2 Clean Rooms Boron p+ Polysilicon

Cross section implafil

Silicon nitride I i i l l l l p-type silicon p

‘l. 2. 3

CVDPhosphorus or arsenic Si() Source Al Gate Dram2 ’ ,;,,,;,, ,,,,,,, ,,,, ,,,,,,; Yfffi: Q *se*

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nt nt pi nt nt p* n* n+ p*

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FIGURE 28.3 Cross-sectional views of the fabrication of a MOS transistor. Source: AfterR.C. jaeger.

This chapter first introduces the fundamental properties of semiconductors andof silicon and then describes each of the major fabrication steps. Packaging of the inte-grated circuits and assembling them onto circuit boards are also discussed. Finally, thechapter describes current trends and forecasts in the microelectronics industry.

28.2 Clean Rooms

Clean rooms are essential for the production of most integrated circuits-a fact thatcan be appreciated by noting the scale of manufacturing to be performed. Integratedcircuits are typically a few millimeters in length, and the smallest features in a tran-sistor on the circuit may be as small as a few tens of nanometers. This size range is

smaller than particles that we don’t normally consider harmful, such as dust, smoke,perfume, and bacteria. However, if these contaminants are present on a silicon waferduring processing, they can seriously compromise the performance of the entiredevice. Thus, it is essential that all of the potentially harmful particles be eliminatedfrom the IC manufacturing environment.

There are various levels of clean rooms, which are defined by the class of theroom. The classification system refers to the number of 0.5-/.tm or larger particleswithin a cubic metre of air. Thus, a Class-0.35 clean room has 0.35 >< 103 or fewersuch particles per cubic metre. Clearly, the size and the number of particles are im-portant in defining the class of a clean room, as shown in Fig. 28.4. Most cleanrooms for microelectronics manufacuring range from Class 0.035 to Class 0.35. Incomparison, the contamination level in modern hospitals is on the order of 350,000particles per cubic metre.

To obtain controlled atmospheres that are free from particulate contamina-tion, all Ventilating air is passed through a high-efhciency particulate air (HEPA) fil-ter. In addition, the air usually is conditioned so that it is at 21°C and 45% relativehumidity.

794 Chapter 28 Fabrication of Microelectronic Devices

3500 The largest source of contaminants in a clean.9?Q room is the workers themselves. Skin particles,g E 350 O hair, perfume, makeup, clothing, bacteria, and35 451% viruses are given off naturally by people and in suf-

mg Q, 35 52% 9,90 ficiently large numbers to quickly compromise a\ _"’ § Q9 ‘9 0 Class-3.5 clean room. For these reasons, most clean9 E 3 5 619 G60 .

fé Q C229 63 rooms require special coverings, such as white lab-gg Q GQS oratory coats, gloves, and hairnets, as well as the“Eng 35' C29 $55190 avoidance of perfumes and makeup. The most25 c Q9 1? strin ent clean rooms re uire full-bod coverin s_Q G, 0 035 _ Q0 is g <1 Y 5E ,-E 0 called bunn suits. There are other strin ent re-, _ s y g P

E gn cautions as well. For example, the use of a pencil,*Q is instead of a ballpoint pen, can producel- `5 objectionable graphite particles, and special clean-

0.05 0.1 0.51.0 5 10 100Particle diameter (um)

room paper is required to prevent the accumulationof paper particles in the air.

Clean rooms are designed such that the clean-liness at critical processing locations is greater than

FIGURE 28.4 Allowable particle size counts for different clean-room classes. in the clean room in general. This is accomplished

by directing the filtered Ventilating air so that it dis-places ambient air and directs dust particles awayfrom the process-a goal that can be facilitated by

laminar-flow hooded work areas.

28.3 Semiconductors and Silicon

As the name suggests, semiconductor materials have electrical properties that lie

between those of conductors and insulators and that exhibit resistivities between1O`3 and 108 Q-cm. Semiconductors have become the foundation for electronicdevices because their electrical properties can be altered when controlled amounts ofselected impurity atoms are added to their crystal structures. These impurity atoms,also known as dopants, have either one more valence electron (n-type, or negative,dopant) or one less valence electron (p-type, or positive, dopant) than the atoms in

the semiconductor lattice.For silicon, which is a Group IV element in the Periodic Table, typical ii-type

and p-type dopants include, respectively, phosphorus (Group V) and boron (Group III).The electrical operation of semiconductor devices can be controlled through the cre-ation of regions with different doping types and concentrations.

Although the earliest electronic devices were fabricated on germanium, siliconhas become the industry standard. The abundance of alternative forms of silicon in

the Earth is second only to that of oxygen, making it attractive economically.Silicon’s main advantage over germanium is its large energy gap (1.1 eV) comparedwith that of germanium (0.66 eV). This energy gap allows silicon-based devices tooperate at temperatures of about 15 0°G higher than devices fabricated on germani-um, which operate at about 100°C.

Another important processing advantage of silicon is that its oxide (silicondioxide, SiO2) is an excellent electrical insulator and can be used for both isolationand passivation purposes. By contrast, germanium oxide is water soluble and unsuit-able for electronic devices. Furthermore, the oxidized form of silicon allows the pro-duction of metal-oxide-semiconductor (MOS) devices, which are the basis for MOStransistors. These materials make up memory devices, processors, and the like, andare by far the largest volume of semiconductor material produced worldwide.

Section 28.4

CQ/ '

V)¢

Crystal Growing and Wafer Preparation

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FIGURE 28.5 Crystallographic structure and Miller indices for silicon. (a) Construction of a

diamond-type lattice from interpenetrating face-centered cubic cells; one of eight penetrating cellsis shown. (b) Diamond-type lattice of silicon; the interiors have been shaded in color. (c) Millerindices for a cubic lattice.

Structure of Silicon. The crystallographic structure of silicon is a diamond-typefcc structure, as shown in Fig. 28.5, along with the Miller indices of an fcc material.Miller indices are a useful notation for identifying planes and directions within aunit cell. A crystallographic plane is defined by the reciprocal of its intercepts withthe three axes. Since anisotropic etchants preferentially remove material in certaincrystallographic planes, the orientation of the silicon crystal in a wafer is an impor-tant consideration.

In spite of its advantages, silicon has a larger energy gap (1.1 eV) than germa-nium oxide and, therefore, has a higher maximum operating temperature (about200°C). This limitation has encouraged the development of compound semiconduc-tors, specifically gallium arsenide. Its major advantage over silicon is its ability toemit light, thus allowing the fabrication of devices such as lasers and light-emittingdiodes (LEDs).

Devices fabricated on gallium arsenide also have much higher operating speedsthan those fabricated on silicon. Some of gallium arsenide’s disadvantages are itsconsiderably higher cost, greater processing complications, and, most critically, thedifficulty of growing high-quality oxide layers, the need for which is emphasizedthroughout the rest of this chapter.

28.4 Crystal Growing and Wafer Preparation

Silicon occurs naturally in the forms of silicon dioxide and various silicates. It must,however, undergo a series of purification steps in order to become the high-quality,defect-free, single-crystal material that is required for semiconductor device fabrica-tion. The process begins by heating silica and carbon together in an electric furnace,which results in a 95-to-98% pure polycrystalline silicon. This material is converted

Chapter 28 Fabrication of Microelectronic Devices

to an alternative form, commonly trichlorosilane, which in turn is purified anddecomposed in a high-temperature hydrogen atmosphere. The resulting product is

extremely high quality electronic-grade silicon (EGS).Single-crystal silicon usually is obtained through the Czochralski, or CZ,

process, described in Section 11.5. The process utilizes a seed crystal that is dippedinto a silicon melt and is then pulled out slowly while being rotated. At this point,controlled amounts of impurities can be added to obtain a uniformly doped crystal.The result of the CZ process is a cylindrical single-crystal ingot, typically 100 to300 mm in diameter and over 1 m in length. However, the technique does not allowfor exact control of the ingot diameter. Therefore, ingots commonly are grown a fewmillimeters larger than the required size and are ground to a precise diameter.Silicon wafers then are produced from silicon ingots by a sequence of machining andfinishing operations, as illustrated in Fig. 28.6.

Silicon Pulleyln90t Silicon ingot , ;__ __ g/

Diamond metal-bonded wheel

Electroplated band saw

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InternalDiamond rT1ela|~ diameter Saw ° ° ° 0 0

bonded wheel ._ ,, W4 A , Silicon

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C D ,, ,,;, _....... Silicon Polishing pad wafer

Silicon Wafer ?f §7 ¢7° ' ?f’? ¥

edging wheelSlurry

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FIGURE 28.6 Finishing operations on a silicon ingot to produce wafers: (a) sawing the endsoff the ingot; (b) grinding of the end and cylindrical surfaces of a silicon ingot; (c) machiningof a notch or flat; (d) slicing of wafers; le) end grinding of wafers; (f) chemical-mechanicalpolishing of wafers.

Next, the crystal is sliced into individualwafers by using an inner-diameter diamond-encrusted blade (Fig. 24.25f). In this method,a rotating, ring-shaped blade with its cuttingedge on the inner diameter is utilized. Whilethe substrate depth required for most elec-tronic devices is no more than several mi-crons, wafers typically are cut to a thicknessof about 0.5 mm. This thickness provides thenecessary physical support for the absorptionof temperature variations and the mechanicalsupport needed during subsequent fabrica-tion.

The vvafer is then ground along its edgeswith a diamond wheel. This operation givesthe Wafer a rounded profile that is more re-sistant to chipping. Finally, the wafers must bepolished and cleaned to remove surface dam-age caused by the sawing process. This is

commonly performed by chemical-mechanicalpolishing (also referred to as chemical-mechanical planarization), as described inSection 26.7.

In order to properly control the manu-facturing process, it is important to deter-mine the orientation of the crystal in a Wafer.Wafers, therefore, have notches or flats ma-chined into them for identification, as shownin Fig. 28.7. Most commonly, the (100) or(111) plane of the crystal defines the Wafersurface, although (110) surfaces also can beused for micromachining applications.Wafers are also identified by a laser scribemark produced by the manufacturer. Laser

Section 28.4 Crystal Growing and Wafer Preparation 797

Pl'lmaVY Primary8 flat“‘* fl t

V)Secondaryflat

{111} n-type {111} p-type

TTSQ*

Secondaryi Primary Primaryflat flat flat

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{100} n-type {‘| OO} p-type

(fi)

{11O} plane {100} planeSecondary I V

fl ta v 5 Primary ,,,g , /l flat

(D)

FIGURE 28.7 Identification of single-crystal wafers of silicon. Thisidentification scheme is common for 150-mm diameter wafers, butnotches are more common for larger wafers.

scribing of information may take place on the front or on the back side of the wafer.The front side of some wafers has an exclusion edge area, 3 to 10 mm in size, re-served for the scribe information, such as lot numbers, orientation, and a uniqueWafer identification code.

Device fabrication takes place over the entire Wafer surface. Wafers are typi-cally processed in lots of 25 or 50, with 150 to 200 mm diameters each, or lots of12 to 25 with 300-mm diameters each. In this Way, they can be easily handled andtransferred during processing steps. Because of the small device size and large Waferdiameter, thousands of individual circuits can be placed on one Wafer. Once pro-cessing is completed, the Wafer is sliced into individual chips, each containing onecomplete integrated circuit.

At this point, the single-crystal silicon Wafer is ready for the fabrication of theintegrated circuit or device. Fabrication takes place over the entire Wafer surface,and many chips are produced at the same time, as shown in Fig. 28.1a. The num-ber of chips that can be produced is dependent on the cross-sectional area of theWafer. For this reason, a number of advanced-circuit manufacturers have movedtowards using larger single-crystal cylinders, and 300-mm diameter wafers nowhave increasingly become common.


28.5 Film Deposition

Films of many different types are used extensively in microelectronic-device process-ing, particularly insulating and conducting films, Commonly deposited films includepolysilicon, silicon nitride, silicon dioxide, tungsten, titanium, and aluminum. lnsome instances, the wafers merely serve as a mechanical support on which customepitaxial layers are grown.

Epitaxy. Defined as the growth of a vapor deposit, epitaxy (or electrodeposit)occurs when the crystal orientation of the deposit is related directly to the crystalorientation in the underlying crystalline substrate. The advantages of processing onthese deposited films, instead of on the actual wafer surface, include fewer impuri-ties (notably carbon and oxygen), improved device performance, and the tailoring ofmaterial properties (which cannot be done on the wafers themselves).

Some of the major functions of deposited films are masking and protecting thesemiconductor surface. In masking applications, the film must inhibit the passage ofdopants and concurrently display an ability to be etched into patterns of high reso-lution. Upon completion of device fabrication, films are applied to protect the un-

derlying circuitry. Films used for masking and protecting include silicon dioxide,phosphosilicate glass (PSG), and silicon nitride. Each of these materials has distinctadvantages, and they often are used in combination.

Conductive films are used primarily for device interconnection. These filmsmust have a low resistivity, be capable of carrying large currents, and be suitablefor connection to terminal packaging leads with wire bonds. Generally, aluminumand copper are used for this purpose. Increasing circuit complexity has requiredup to six levels of conductive layers, all of which must be separated by insulatingfilms.

Film Deposition. Films may be deposited by a number of techniques, which involvea variety of pressures, temperatures, and vacuum systems (see also Chapter 34):

° One of the simplest and oldest methods is evaporation, used primarily fordepositing metal films. ln this process, the metal is heated in a vacuum to itspoint of vaporization; upon evaporation, the metal forms a thin layer on thesubstrate surface. The heat for evaporation usually is generated by a heatingfilament or electron beam.

° Sputtering involves bombarding a target with high-energy ions (usually argon,Ar+) in a vacuum. Sputtering systems generally include a DC power source toproduce the energized ions. As the ions impinge on the target, atoms areknocked off and subsequently deposited on wafers mounted within the system.

Although some argon may be trapped within the film, sputtering results in

highly uniform coverage. Advances in this field include using a radio-frequencypower source (RF sputtering) and introducing magnetic fields (magnetronsputtering).

° In one of the most common techniques, chemical-vapor deposition (CVD),film is deposited by way of the reaction and/or decomposition of gaseous com-pounds. Using this technique, silicon dioxide is deposited routinely by the oxi-dation of silane or a chlorosilane. Figure 28.8a shows a continuous CVDreactor that operates at atmospheric pressure.

A similar method that operates at lower pressures is referred to as low-pressure chemical-vapor deposition (LPCVD) and is shown in Fig. 28.8b.Capable of coating hundreds of wafers at a time, this method results in a muchhigher production rate than that of atmospheric-pressure CVD and provides

Section 28.6 Oxidatron

N2 GHS N2 Pressure* * * wafers sensorElf' Q 3-zone furnace g _ errrr »r» »r rrrr, . rrrr . r r rrr r,e, r _r rrr rir . Heater

_> Pump

Conveyor Load G88Exhaust ben door inlet Wafefs

(H) (bl

FIGURE 28.8 Schematic diagrams of (a) a continuous, atmospheric-pressure CVD reactorand (b) a low-pressure CVD. Source: After S.M. Sze.

superior film uniformity with less consumption of carrier gases. The technique is

commonly used for depositing polysilicon, silicon nitride, and silicon dioxide.° Plasma-enhanced chemical-vapor deposition (PECVD) involves the processing

of wafers in an RF plasma containing the source gases. This method has theadvantage of maintaining a low wafer temperature during deposition.

Silicon epitaxy layers, in which the crystalline layer is formed using thesubstrate as a seed crystal, can be grown by a variety of methods. If the silicon is

deposited from the gaseous phase, the process is known as vapor-phase epitaxy(VPE). In another variation, the heated substrate is brought into Contact with aliquid solution containing the material to be deposited, a process called liquid-phaseepitaxy (LPE).

Another high-vacuum process utilizes evaporation to produce a thermal beamof molecules that are deposited on the heated substrate. Called molecular-beam epi-taxy (MBE), this process results in a very high degree of purity. In addition, since thefilms are grown one atomic layer at a time, it is possible to have excellent controlover doping profiles. This level of control is important especially in gallium-arsenidetechnology. However, the MBE process has relatively low growth rates as comparedto other conventional film-deposition techniques.

28.6 Oxidation

The term oxidation refers to the growth of an oxide layer as a result of the reactionof oxygen with the substrate material. Oxide films also can be formed by the previ-ously described deposition techniques. Thermally grown oxides, described in thissection, display a higher level of purity than deposited oxides, because they aregrown directly from the high-quality substrate. However, deposition methods mustbe used if the composition of the desired film is different from that of the substratematerial.

Silicon dioxide is the most widely used oxide in IC technology today, and itsexcellent characteristics are one of the major reasons for the widespread use of sili-con. Aside from its effectiveness in dopant masking and device isolation, silicondioxide’s most critical role is that of the “gate oxide” material. Silicon surfaces havean extremely high affinity for oxygen, and a freshly sawed slice of silicon will grow anative oxide of 30 to 40 A thickness (A = 1O`7 mm) quickly.


saoz

FIGURE 28.9 Growth of silicon dioxide, showing consumptionof silicon. Source: After S.M. Sze.

/SiO2 surface ° Dry oxidation is a relatively simple process and is

Qrigina| accomplished by elevating the substrate tempera-Si interface ture, typically to about 750° to 1100°C, in an

oxygen-rich environment. As a layer of oxideSilicon SUbSTr&1i9 forms, the oxidizing agents must be able to pass

through the oxide and reach the silicon surface,where the actual reaction takes place. Thus, anoxide layer does not continue to grow on top of it-

self, but rather, it grows from the silicon surfaceoutward. Some of the silicon substrate is con-sumed in the oxidation process (Fig. 28.9).

The ratio of oxide thickness to the amount of silicon consumed is foundto be 1:0.44. Thus, to obtain an oxide layer 1000 thick, approximately 440 A

of silicon will be consumed. This requirement does not present a problem, as

substrates always are grown sufficiently thick.One important effect of the consumption of silicon is the rearrangement

of dopants in the substrate near the interface. Because different impurities havedifferent segregation coefficients or mobilities in silicon dioxide, some dopantsbecome depleted away from the oxide interface while others pile up there.Consequently, processing parameters must be adjusted to compensate for thiseffect.

° Wet oxidation utilizes a water-vapor atmosphere as the agent. This methodresults in a considerably higher growth rate than that of dry oxidation, but it

suffers from a lower oxide density and, therefore, a lower dielectric strength.The common practice in industry is to combine both dry and wet oxidationmethods by growing an oxide in a three-part layer: dry-wet-dry. This approachcombines the advantages of wet oxidation’s much higher growth rate and dry

oxidation’s high quality.The foregoing two oxidation methods are useful primarily for coating the

entire silicon surface with oxide; however, it also may be necessary to oxidize

only certain portions of the surface. The procedure of oxidizing only certainareas is called selective oxidation and uses silicon nitride, which inhibits the

passage of oxygen and water vapor. Thus, by covering certain areas with siliconnitride, the silicon under these areas remains unaffected while the uncoveredareas are oxidized.

28.7 Lithography

Lithography is the process by which the geometric patterns that define devices are

transferred to the substrate surface. A summary of lithographic techniques is given

in Table 28.1, and a comparison of the basic lithography methods is shown in

Fig. 28.10. There are many forms of lithography, but the most common form used

today is photolithography. Electron-beam and X-ray lithography are of great inter-est because of their ability to transfer patterns of higher resolution, which is a neces-

sary feature for the increased miniaturization of integrated circuits. Most IC

applications can be manufactured successfully with photolithography.

Photolithography. Photolithography uses a reticle, also called a photomask or

mask, which is a glass or quartz plate with a pattern of the chip deposited onto it witha chromium film. The reticle image can be the same size as the desired structure onthe chip, but it is often an enlarged image, usually 5>< to 20>< larger, although 10><

Section 28 7 Lithography

TABLE 28.|

General Characteristics of Lithography Techniques

Method Wavelength (nm) Finest feature size (nm)

Ultraviolet (Photolithography) 365 350Deep UV 248 250Extreme UV 10-20 30-100X-ray 0.01-1 20-100Electron beam - 80Immersion 1 93 1 1

Source: After P.K. Wright.

Visible photons Elecirons

Air Vacuum O 5 e” e`Contact mask ‘_ ' 'um Direct write\\

_Resist Resist S“”S"a‘@

is ._ it N Substrate

Photolithography Electron-beam lithographyline widths routinely 2-3 ,um line widths of 0.1 ,um

(8) (D)

X-rays Ions

l l l iProximity mask Air f V if acuum

R95-iSl Resist Direct write X-ray lithography lon-beam lithography

line widths of 0.2 /tm line widths of 0.1 pm

(C) (d)

FIGURE 28.I0 Comparison of lithography techniques. Note that (a) and (c) involve masking toachieve pattern transfer; while (b) and (d) scribe the pattern Without a mask, known as direct writing.

magnification is the most common. Enlarged images then are focused onto a Waferthrough a lens system; this operation is referred to as reduction lithography.

In current practice, the lithographic process is applied to each microelectroniccircuit as many as 25 times-each time using a different reticle to define the differentareas of the working devices. Typically designed at several thousand times their finalsize, reticle patterns undergo a series of reductions before being applied permanentlyto a defect-free quartz plate. Computer-aided design (CAD; see Section 38.4) hashad a major impact on reticle design and generation.


Cleanliness is especially important in lithography, and many manufacturersnow use robotics and specialized wafer-handling apparatus in order to minimizecontamination from dust and dirt. Once the film deposition process is completedand the desired reticle patterns have been generated, the wafer is cleaned and coatedwith an organic polymer known as a photoresist (PR).

A photoresist consists of three principal components:

I. A polymer that changes its structure when exposed to radiation.

2. A sensitizer that controls the reactions in the polymer.

3. A solvent, in order to deliver the polymer in liquid form.

Photoresist layers 0.5 to 2.5 /.im thick are produced by applying the PR to thesubstrate and then spinning it at several thousand rpm for 30 or 60 seconds to give

uniform coverage (Fig. 28.11).The next step in photolithography is prebaking the wafer to remove the sol-

vent from the photoresist and harden it. This step is carried out on a hot plate heat-ed to around 100°C. The pattern is transferred to the wafer through stepper orstep-and-scan systems. With wafer steppers (Fig. 28.12a), the full image is exposedin one flash, and the reticle pattern is then refocused onto another adjacent sectionof the wafer. With step-and-scan systems (Fig. 28.12b), the exposing light source is

focused into a line, and the reticle and wafer are translated simultaneously in oppo-site directions to transfer the pattern.

The wafer must be aligned carefully under the desired reticle. In this crucialstep called registration, the reticle must be aligned correctly with the previous layeron the wafer. Once the reticle is aligned, it is subjected to ultraviolet (UV) radiation.Upon development and removal of the exposed photoresist, a duplicate of the reticlepattern will appear in the photoresist layer.

As seen in Fig. 28.13, the reticle can be a negative image or a positiveimage of the desired pattern. A positive reticle uses the UV radiation to breakdown the chains in the organic film, so that these films are removed preferen-tially by the developer. Positive masking is more common than negative masking,because, with negative masking, the photoresist can swell and distort, making itunsuitable for small geometries. Newer negative photoresist materials do nothave this problem.

Photoresist SkinSubstrate Liquid resist

Chuck

1. 2.

2Liquid resist Evaporation1.3 spun outfrom ; ; § Q ofsolventbeneath skin$2 <> L.>

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FIGURE 28.I I Spinning of an organic coating on a Wafer.

Section 28.7 Lithography

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UV radiation Positive reticle 1. 2. 3.

SiO2 etched Developed imagePh t tremo ed

OO J '_ _'ni--Q -if *i *'* / 6. 5. 4.

FIGURE 28.13 Pattern transfer by photolithography. Note that the mask in Step 3 can be apositive or negative image of the pattern.

Following the exposure and development sequence, postbaking the vvaferdrives off the solvent and toughens and improves the adhesion of the remainingresist. In addition, a deep UV treatment (baking the Wafer to about 150° to 200°C inultraviolet light) can be used to further strengthen the resist against high-energyimplants and dry etches. The underlying film not covered by the photoresist is thenetched avvay (Section 28.8) or implanted (Section 28.9).

80 Chapter 28 Fabncation of Microelectronic Devices

After lithography, the developed photoresist must be removed in a processcalled stripping. In wet stripping, the photoresist is dissolved by solutions such as

acetone or strong acids. Dry stripping involves exposing the photoresist to an oxy-

gen plasma, which also is referred to as ashing. Dry stripping has become more pop-ular, because it (a) does not involve the disposal of consumed hazardous chemicals

and (b) is easier to control and can result in exceptional surfaces. Wet strippingsolutions tend to lose potency in use.

One of the major issues in lithography is line width, the width of the smallestfeature imprintable on the silicon surface. As circuit densities have escalated over theyears, device sizes and features have become smaller and smaller. Today, commer-cially feasible minimum line widths are 45 nm, with considerable research directedat obtaining 32-nm or smaller line widths.

Because pattern resolution and device miniaturization have been limited by the

wavelength of the radiation source used, the need has arisen to move to wavelengthsshorter than those in the UV range, such as deep UV wavelengths, extreme UV

wavelengths, electron beams, and X-rays. In these technologies, the photoresist is

replaced by a similar resist that is sensitive to a specific range of shorter wave-lengths. Alternatively, fluids with a refractive index higher than that of water are

being investigated to increase the resolutions of immersion lithography.

Extreme Ultraviolet Lithography. The pattern resolution in photolithographyand immersion lithography is ultimately limited by light diffraction. Qne of themeans of reducing the effects of diffraction is to use ever shorter wavelengths.Extreme ultraviolet lithography (EUV) uses light at a wavelength of 13 nm in orderto obtain features in the range from 30 to 100 nm. The waves are focused throughhighly reflective molybdenum-silicon mirrors, instead of glass lenses, which absorbEUV light, through the mask to the wafer surface.

X-ray Lithography. Although photolithography is the most widely used lithogra-phy technique, it has fundamental resolution limitations associated with light dif-fraction. X-ray lithography is superior to photolithography because of the shorterwavelength of the radiation and the very large depth of focus. These characteristicsallow much finer patterns to be resolved and make X-ray lithography far less sus-

ceptible to dust than photolithography. Furthermore, the aspect ratio (defined as theratio of depth to lateral dimension) can be higher than 100 with X-ray lithography,but is limited to around 10 with photolithography. However, to achieve this benefit,synchrotron radiation is required, which is expensive and available at only a fewresearch laboratories.

Given the large capital investment required for a manufacturing facility, indus-

try has preferred to refine and improve optical lithography instead of investing newcapital into X-ray-based production. Currently, X-ray lithography is not wide-spread; however, the LIGA process (see Section 293) fully exploits the benefits of

the technique.

Electron-beam and lon-beam Lithography. Like X-ray lithography, electron-hearn (e-beam) and ion-hearn (i-beam) lithography are superior to photolithogra-phy in terms of attainable resolutions. These two methods involve high currentdensity in narrow electron or ion beams (known as pencil sources), which scan a

pattern one pixel at a time onto a wafer. The masking is done by controlling thepoint-by-point transfer of the stored pattern, using software (called direct writing).These techniques have the advantages of accurate control of exposure over smallareas of the wafer, large depth of focus, and low defect densities. Resolutions are

Section 28 7 Lithography

limited to about 10 nm because of electron scatter, although 2-nm resolutions havebeen reported for some materials.

It should be noted that the scan time significantly increases as the resolutionincreases, because more highly focused beams are required. The main drawbackof these techniques is that electron and ion beams have to be maintained in a vac-

uum, which significantly increases equipment complexity and production cost.Furthermore, the scan time for a wafer is much slower than that for other litho-graphic methods.

SCALPEL. Figure 28.14 shows the SCALPEL (scattering with angular limitationprojection electron-beam lithography) process, in which a mask is produced from

about a 0.1-/.tm-thick membrane of silicon nitride and is patterned with an approx-imately 50-nm-thick coating of tungsten. High-energy electrons pass through boththe silicon nitride and the tungsten, but the tungsten scatters the electrons widely,

whereas the silicon nitride results in very little scattering. An aperture blocks the

scattered electrons, resulting in a high-quality image at the wafer.

The limitation to the SCALPEL process is the small-sized masks that are cur-

rently in use; however, the process has high potential. Perhaps its most significantadvantage is that energy does not need to be absorbed by the reticle; instead, it is

blocked by the aperture, which is not as fragile or expensive as the reticle.

Electron Yiflff "f"‘ iE'€§`>1>I2ZJE1ilIf~ffQ.f'7Y???"'? I- ie»if meM ksta \‘*»”,a',,~fr”i

Step i x,y wafer

Lens . Q APe"‘"e _. W: ;, _,_,,..;.f.rr; _,,~.,,,,._.,,,,,,;._,;,_,,_. ,rf

Stitching i 5deflector _ Q? fygr i ~ ,; Wafer

Wafer stage Scan

ilu*Step

FIGURE 28.l4 Schematic illustration ofthe SCALPEL process.


EXAMPLE 28.| Moore’s Law

G. Moore, an inventor of the IC and past chairmanof Intel Corporation, observed in 1965 that the sur-face area of a single transistor is reduced by 50%every 12 months. In 1975, he revised this estimate toevery two years, and the resulting estimate is nowwidely known as Moore’s law. This law has beenremarkably accurate. Figure 28.15 shows the histori-cal progression of feature size in dynamic random ac-cess memory (DRAM) bits, as well as projected futuredevelopments. Looking ahead, however, one can see

some major impediments to the continued reliabilityof Moore’s law. Among the more important ones arethe following:

° To produce ever smaller features in the transis-tor requires that even more stringent manufac-turing tolerances be achieved. For example,180-nm line widths require :1;14-nm dimen-sional tolerances, whereas 50-nm line widthsrequire 11:4 nm. Either requirement is especiallyproblematic for the metal connection lineswithin the transistor.

° Smaller transistors can operate only if thedopant concentration is increased. However,above a certain limit, the doping atoms clustertogether. The result is that p-type and n-typesilicon cannot be produced reliably at smalllength scales.

' The gate-switching energy of transistors hasnot been reduced at the same rate as their size;

the result is increased power consumption in

integrated circuits. This effect has a seriousconsequence in that it is very difficult todissipate the heat produced.

° At smaller length scales, microprocessors re-quire smaller voltages for proper operation.However, since the power consumption is stillrelatively high, very large currents are neededbetween the power-conversion devices andcentral-processing units of modern micro-processors. These large currents result in resis-tive heating, thus compounding the heat-extraction problems.

° Quantum effects play a large role at the smalllength scales, and system stability becomes anissue.

Much research is being directed towardsovercoming these limitations. Moore’s law wasintended as a prediction of the short-term future ofthe semiconductor industry and was put forward at a

time when photolithography was the only option.During the four decades since the law was firststated, researchers often have identified seeminglyinsurmountable problems that, in turn, have beenovercome.

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Section 28 7 L|thography 0

PDMS

Developed photoresist Cured PDMS Stamp

1 "" 5 ~' eee,e 3357 S‘"°°'“Q ,L Substrate

1. 2. 3.

FIGURE 28.I6 Production of a polydimethylsiloxane (PDMS) mold for soft lithography. 1. A

developed photoresist is produced through standard lithography (see Fig. 28.13). 2. A PDMSstamp is cast over the photoresist. 3. The PDMS stamp is peeled off the substrate to produce a

stamp. The stamp shown has been rotated to emphasize the replication of surface features; themaster pattern can be used several times. Source: After Y. Xia and G.M. Whitesides.

Soft Lithography. Soft lithography refers to several processes for pattern trans-fer, all of which require that a master mold be created by one of the standardlithography techniques previously described. The master mold is then used toproduce an elastomeric pattern, or stamp, as shown in Fig. 28.16. An elastomerthat has been commonly used for the stamp is silicone rubber, or polydimethyl-siloxane (PDMS), because it is chemically inert, is not hygroscopic (it does notswell with humidity), and has good thermal stability, strength, durability, andsurface properties.

Several PDMS stamps can be produced from the same pattern, and eachstamp can be used several times. Some of the common soft lithography processesare the following:

a. Microcontact printing (MCP). In microcontact printing, the PDMS stamp is

coated with an “ink” and then pressed against a surface. The peaks of thepattern are in contact with the opposing surface, and a thin layer of the inkis transferred, often only one molecule thick (called a self-assembled mono-layer or boundary film; see Section 33.6). This thin film can serve as a maskfor selective wet etching, described shortly, or it can be used to impart adesired chemistry onto the surface.

b. Microtransfer molding (/.tTM). In this process, shown in Fig. 28.17a, therecesses in the PDMS mold are filled with a liquid polymer precursor andthen pushed against a surface. After the polymer has cured, the mold is

peeled off, leaving behind a pattern suitable for further processing.

c. Micromolding in capillaries. In this technique (MIMIC), shown in Fig. 28.1 7b,the PDMS stamp pattern consists of channels that use capillary action towick a liquid into the stamp, either from the side of the stamp or fromreservoirs within the stamp. The liquid can be a thermosetting polymer, aceramic sol gel, or suspensions of solids within liquid solvents. Good pat-tern replication can occur, as long as the channel aspect ratio is moderateand the actual channel dimensions allow fluid flow; the dimensions re-quired depend on the liquid used. The MIMIC process has been used toproduce all-polymer field-effect transistors and diodes, and has variousapplications in sensors (Section 37.7).


4 44 { 4

M / .. 4 A ,

iifl if if

- T == ; ,,,, ;' 1 Prepare PDl\/IS stamp 1. Prepare PDMS stamp

Liquid polymerStamp droplet

MK/ Substrate

2 Fill cavities with polymer precursor 2. Press stamp against surface; apply dropof liquid polymer to end of stamp.

V;ki;kyyy `.f.;;;;;~_

. pf

3 Press stamp against surface; allow 3. Remove excess liquid; allow polymerprecursor to cure to cure

'_ __;_~ if uffm' "

Peel off stamp 4. Peel off stamp

(H) (D)

FIGURE 28.17 Soft lithography techniques. (a) Microtransfer molding (/.iTM), and (b) micro-molding in capillaries (MIMIC). Source: After Y. Xia and G.M. Whitesides.

28.8 Etching

Etching is the process by which entire films or particular sections of films are re-

moved, and it plays an important role in the fabrication sequence. One of the keycriteria in this process is selectivity-that is, the ability to etch one material withoutetching another. A summary of etching processes and etchants is given in Tables 28.2and 28.3.

In silicon technology, an etching process must etch the silicon-dioxide layereffectively and with minimal removal of either the underlying silicon or the resistmaterial. In addition, polysilicon and metals must be etched into high-resolutionlines with vertical Wall profiles and also with minimal removal of either the underly-ing insulating film or the photoresist. Typical etch rates range from hundreds toseveral thousands of angstroms per minute, and selectivities (defined as the ratio ofthe etch rates of the two films) can range from 1:1 to 100:1.

Section 28.8 Etching 809

TABLE 28.2

General Characteristics of Silicon Etching Operations

Temperature Etch rate {111}/ {100} Nitride etch SiO; etch rate(°C) (/im/min) selectivity rate (nm/min) (nm/min) p++ etch stop

Wet etchingHF:HNO3:CH3COOH 25 1-20 - Low 10-30 NO

KOH 70-90 0.5-2 100:1 <1 10 Yes

Ethylene-diamine 1 15 0.75 35: 1 0.1 0.2 Yes

pyrocatechol (EDP)N(CH3)4OH (TMAH) 90 0.5-1.5 50:1 <0.1 <0.1 Yes

Dry (plasma) etchingSF6 0-100 0.1-0.5 - 200 10 NoSF6/C4F8 (DRIE) 20-80 1-3 - 200 10 No

Source: Adapted from N. Maluf, An Introduction to Microelectrornec/vanical Systems Engineering, Artech House, 2000.

28.8.l Wet Etching

Wet etching involves immersing the wafers in a liquid solution, usually acidic. Oneprimary feature of most wet-etching operations is that they are isotropic; that is,they etch in all directions of the workpiece at the same rate. This isotropy results inundercuts beneath the mask material (see, for example, Figs. 27.3b and 28.18a) andlimits the resolution of geometric features in the substrate.

Effective etching requires the following conditions:

I. Etchant transport to the surface.

2. A chemical reaction.

3. Transport of reaction products away from the surface.

4. Ability to stop the etching process rapidly (known as etch stop) in order toobtain superior pattern transfer, usually by using an underlying layer with highselectivity.

If the first or third condition listed limits the speed of the process, agitation orstirring of the solution can be employed to increase etching rates. If the second con-dition limits the speed of the process, the etching rate will depend strongly on tem-perature, etching material, and solution composition. Reliable etching thus requiresboth good temperature control and repeatable stirring capability.

lsotropic Etchants. These etchants are widely used for

° Removing damaged surfaces.° Rounding of sharply etched corners to avoid stress concentrations.° Reducing roughness after anisotropic etching.° Creating structures in single-crystal slices.° Evaluating defects.

Fabrication of microelectronic devices and microelectromechanical systems,described in Chapter 29, requires the precise machining of structures, done throughmasking. However, masking is a challenge with isotropic etchants. The strong acids(a) etch aggressively at a rate of up to 50 /.tm/min with an etchant of 66% HNG3and 34% HF, although etch rates of 0.1 to 1 /.tm/s are more typical, and (b) producerounded cavities. Furthermore, the etch rate is highly sensitive to agitation, andtherefore, lateral and vertical features are difficult to control.

Because the size of the features in an integrated circuit determines its perform-ance, there is a strong desire to produce well-defined, extremely small structures.

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Such small features cannot be attained through isotropic etching because of thepoor definition resulting from undercutting of masks.

Anisotropic Etching. This situation takes place when etching is strongly de-pendent on compositional or structural variations in the material. There are twobasic kinds of anisotropic etching: orientation-dependent etching (ODE) and1/ertical etching, although most vertical etching is done with dry plasmas and is

described later. Orientation-dependent etching commonly occurs in a single crys-tal when etching takes place at different rates in different directions, as shown inFig. 28.1811

When used properly, anisotropic etchants produce geometric shapes withwalls defined by the crystallographic planes that resist the etchants. For example,Fig. 28.19 shows the vertical etch rate for silicon as a function of temperature. Ascan be seen, etching is more than one order of magnitude slower in the [111]crystal direction than in the other directions; therefore, well-defined walls can beobtained along the [111] crystal direction.

The anisotropy ratio for etching is defined by

EiAR = _ 28.1E2 < >

where E is the etch rate in a crystallographic direction of interest, and the sub-scripts refer to two directions or materials of interest. The anisotropy ratio is

unity for isotropic etchants and can be as high as 400/200/1 for (1 10)/(100)/(111)silicon. The <111> planes always etch the slowest, but the <100> and <110>planes can be controlled through etchant chemistry.

Masking is also a concern in anisotropic etching, but for different reasonsthan with isotropic etching. Anisotropic etching is slow, typically 3 /.tm/min; thus,anisotropic etching through a wafer may take several hours. Silicon oxide mayetch too rapidly to use as a mask; hence, a high-density silicon-nitride mask maybe needed.

Often, it is important to rapidly halt the etching process. This is typicallythe case when thin membranes are to be manufactured or features with veryprecise thickness control are needed. Conceptually, rapid halting can be

Temperature (°C)102 120 100 80 60 40

_

1; 1012 <11O>Q _

&E _ <100>5 100-cu :

E

5 10-1'l-U T

Q <111>1OT2

2.5 2.7 2.9 3.1 3.31/T(>< 10-3 Kel)

FIGURE 28.l9 Etch rates of silicon in different crystallographic orientations, using ethylene-diamine/pyrocatechol-in-water as the solution. Source: After H. Seidel.

Section 28.8 Etching 8| I

Undercut Mask layer

4-1)Etch material(e.g_, silicon)

Etch front

(H)

{111} face

' 4.7°Etch front Final shape

(b)

Etch front

(C)

FIGURE 28.I8 Etching direc-tionality. (a) Isotropic etching:Etch proceeds vertically andhorizontally at approximatelythe same rate, with significantmask undercut. (b) Orientation-dependent etching (ODE): Etchproceeds vertically, terminatingon {111} crystal planes withlittle mask undercut. (c) Verticaletching: Etch proceeds verti-cally with little mask under-cut. Source: Courtesy of K.R.Williams, Agilent Laboratories.


Boron doped W SiO2 a . SiO? ss.._-,- ._ _ »,»» SiO2

SiO2 SiO2 W W SiO2

1. Oxidation 2. Lithography and 3. Boron diffusiondevelopment

Boron-doped silicondoes not etch Membfane ~»~»~ f,,,

M NW M J \c... 3i02

Orifice Orifice4. Anisotropic etching 5. Stripping and reoxidation

FIGURE 28.20 Application of a boron etch stop and back etching to form a membrane andorifice. Source: After l. Brodie and ].]. Murray.

accomplished by removing the Wafer from the etching solution. However, etchingdepends to a great extent on the ability to circulate fresh etchants to the desired lo-cations. Since the circulation varies across a Wafer’s surface, this strategy for haltingthe etching process would lead to large variations in the etched depth.

The most common approach to obtain uniform feature sizes across a Wafer is

to use a boron etch stop, Where a boron layer is diffused or implanted into silicon.Examples of common etch stops are the placement of a boron-doped layer beneathsilicon or the placement of silicon dioxide (SiO2) beneath silicon nitride (Si3N4).Since anisotropic etchants do not attack boron-doped silicon as aggressively as theydo undoped silicon, surface features or membranes can be created by back etching.An example of the boron etch-stop approach is shown in Fig. 28.20.

Several etchant formulations have been developed, including hydroHuoricacid, phosphoric acid, mixtures of nitric acid and hydrofluoric acid, potassium hy-drochloride, and mixtures of phosphoric acid, nitric acid, acetic acid, and Water.Wafer cleaning is done with a solution consisting of sulfuric acid and peroxide(Piranha solution, a trade name). Photoresist can be removed with these solutions,although acetone is used more commonly for this purpose.

28.8.2 Dry Etching

Modern integrated circuits are etched exclusively by dry etching, which involves theuse of chemical reactants in a low-pressure system. In contrast to the wet-etching process,dry etching can have a high degree of directionality, resulting in highly anisotropic etch-ing profiles (Fig. 28.1 Sc). Also, the dry-etching process requires only small amounts ofthe reactant gases, whereas the solutions used in the Wet-etching process have to be re-freshed periodically. Dry etching usually involves a plasma or discharge in areas ofhigh electric and magnetic fields; any gases that are present are dissociated to formions, photons, electrons, or highly reactive molecules. Table 28.2 lists some of themore common dry etchants, their target materials, and typical etch rates.

There are several specialized dry-etching techniques.

Sputter Etching. Sputter etching removes material by bombarding the surface withnoble gas ions, usually Ar+. The gas is ionized in the presence of a cathode and ananode (Fig. 28.21). If a silicon wafer is the target, the momentum transfer associatedwith the bombardment of atoms causes bond breakage and material to be ejected or

Section 28 8 Etching

Io Neutral Volatile productn

(al (bl

Neutral Ion Volame product Neutral lon Volatile product Inhibitor

(C) ld)

FIGURE 28.21 Machining profiles associated with different dry-etching techniques: (a) sput-tering; (b) chemical; (c) ion-enhanced energetic; (cl) ion-enhanced inhibitor. Source: AfterM. Madou.

sputtered. If the silicon chip is the substrate, then the material in the target is depositedonto the silicon after it has been sputtered by the ionized gas.

The major concerns in sputter etching are the following:

° The ejected material can be redeposited onto the target, especially with largeaspect ratios.

° Sputtering can cause damage or excessive erosion of the material.° Sputter etching is not material selective, and because most materials sputter at

about the same rate, masking is difficult.° Sputter etching is slow, with etch rates limited to tens of nanometers per

minute.° The photoresist is difficult to remove.

Reactive Plasma Etching. Also referred to as dry chemical etching, reactiveplasma etc/Qing involves chlorine or fluorine ions (generated by RF excitation) andother molecular species that diffuse into and chemically react with the substrate,forming a volatile compound, which is then removed by a vacuum system. Themechanism of reactive plasma etching is shown in Fig. 28.22 and is as follows:

I. A reactive species, such as CF4, is produced and dissociates upon impact withenergetic electrons to produce fluorine atoms.

2. The reactive species then diffuses into the surface.

3. It becomes adsorbed.

4. The reactive species chemically reacts to form a volatile compound.

5. The reactant then desorbs from the surface.

6. lt diffuses into the bulk gas, where it is removed by a vacuum system.

Some reactants polymerize on the surface and thus require additional removal,either with oxygen in the plasma reactor or by an external ashing operation. Theelectrical charge of the reactive species is not high enough to cause damage throughimpact on the surface, so no sputtering occurs. Thus, the etching is isotropic and un-dercutting of the mask takes place (Fig. 28.18a).


O O.

AR) O Q

1. Generation ot Q) QD

etchant species

O 0 eO\ O % 6. Diffusion

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3. Adsor tion 0 5- GSOVPUOVW

p . Q Q \ ’;», 2 If' Film (H) (D)

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FIGURE 28.22 (a) Schematic illustration of reactive plasma etching. (b) Example of a deepreactive-ion etched trench. Note the periodic undercuts, or scallops. (C) Near-vertical sidewallsproduced through deep reactive-ion etching (DRIE), an anisotropic-etching process. (d) An

example of cryogenic dry etching, showing a 145-um deep structure etched into silicon withthe use of a 2.0-/,tm-thick oxide masking layer. The substrate temperature was -140°C duringetching. Source: (a) After M. Madou. (b) through (d) After R. Kassing and LW Rangelow,University of Kassel, Germany.

Physical-chemical Etching. Processes such as reactive ion-beam etching (RIBE)

and chemically assisted ion-heafn etching (CAIBE) combine the advantages of physi-cal and chemical etching. These processes use a chemically reactive species to drivematerial removal, but this is assisted physically by the impact of ions onto the surface.In RIBE, also known as deep reactive-ion etching (DRIE), vertical trenches hundredsof nanometers deep can be produced by periodically interrupting the etching processand depositing a polymer layer, as shown in Fig. 28.22d.

In CAIBE, ion bombardment can assist dry chemical etching by

° Making the surface more reactive.° Clearing the surface of reaction products and allowing the chemically reactive

species access to the cleared areas.° Providing the energy to drive surface chemical reactions; however, the neutral

species do most of the etching.

Section 28.8 Etching 8 I 5

Physical-chemical etching is extremely useful because the ion bombardment is

directional, so that etching is anisotropic. Also, the ion-bombardment energy is lowand does not contribute much to mask removal, thus allowing the generation ofnear-vertical walls with very large aspect ratios. Since the ion bombardment doesnot remove material directly, masks can be used.

Cryogenic Dry Etching. This method is used to obtain very deep features with ver-tical walls. The workpiece is lowered to cryogenic temperatures, and then theCAIBE process takes place. The very low temperatures involved ensure that insuffi-cient energy is available for a surface chemical reaction to take place, unless ionbombardment is normal to the surface. Oblique impacts, such as those occuring onsidewalls in deep crevices, cannot drive the chemical reactions.

Since dry etching is not selective, etch stops cannot be applied directly. Dry-etching reactions must be terminated when the target film is removed. Optical emis-sion spectroscopy often is used to determine the end point of a reaction. Filters canbe used to capture the wavelength of light emitted during a particular reaction.A noticeable change in light intensity at the point of etching will be detected.

EXAMPLE 28.2 Comparison of Wet and Dry Etching

Consider the case where a < 100> wafer has an oxidemask placed on it in order to produce square or rec-tangular holes. The sides of the square are orientedprecisely Within the <110> direction (see Fig. 28.5 )

of the wafer surface, as shown in Fig. 28.23.Isotropic etching results in the cavity shown in

Fig. 28.23a. Since etching occurs at constant rates inall directions, a rounded cavity that undercuts themask is produced. An orientation-dependent etchantproduces the cavity shown in Fig. 28.23b. Becauseetching is much faster in the <100> and <11O>directions than in the <111> direction, sidewallsdefined by the <111> plane are generated. For

silicon, these sidewalls are at an angle of 54.74° tothe surface.

The effect of a larger mask or shorter etch timeis shown in Fig. 28.23c. The resultant pit is definedby <111> sidewalls and by a bottom in the <100>direction parallel to the surface. A rectangular maskand the resulting pit are shown in Fig. 28.23d. Deepreactive-ion etching is depicted in Fig. 28.23e. Notethat a polymer layer is deposited periodically ontothe hole sidewalls to allow for deep pockets, butscalloping (greatly exaggerated in the figure) is

unavoidable. A hole resulting from CAIBE is shownin Fig. 28.23f.

1,1 1,1 11,111 1191 1,1 1,1

(8) (bl (C) (G) (G) (f)

FIGURE 28.23 Various holes generated from a square mask in (a) isotropic (wet) etching; (b) orientation-dependent etching (ODE); (c) ODE with a larger hole; (d) ODE of a rectangular hole; (e) deep reactive-ionetching; and (f) vertical etching. Source: After M. Madou.


28.9 Diffusion and lon Implantation

Recall that the electrical operation of microelectronic devices depends on regionsthat have different doping types and concentrations. The electrical character of theseregions is altered through the introduction of dopants into the substrate, accom-plished by the diffusion and ion-implantation processes. This step in the fabricationsequence is repeated several times, since many different regions of microelectronicdevices must be defined.

In the diffusion process, the movement of atoms is a result of thermal excita-tion. Dopants can be introduced to the substrate surface in the form of a depositedfilm, or the substrate can be placed in a vapor containing the dopant source. Theprocess takes place at elevated temperatures, usually 800° to 1200°C. Dopantmovement within the substrate is strictly a function of temperature, time, and the

diffusion coefficient (or diffusivity) of the dopant species, as well as the type andquality of the substrate material.

Because of the nature of diffusion, the dopant concentration is very high at the

substrate surface and drops off sharply away from the surface. To obtain a moreuniform concentration within the substrate, the wafer is heated further to drive in

the dopants in a process called drive-in diffusion. Diffusion, whether desired or not,always occurs at high temperatures; this phenomenon is always taken into accountduring subsequent processing steps. Although the diffusion process is relatively in-

expensive, it is highly isotropic.Ion implantation is a much more extensive process and requires specialized

equipment (Fig. 2824; see also Section 34.7). Implantation is accomplished by ac-

celerating the ions through a high-voltage field of as much as 1 million electron voltsand then by choosing the desired dopant by means of a mass separator. In a mannersimilar to that of cathode-ray tubes, the beam is swept across the wafer by sets of de-flection plates, thus ensuring uniform coverage of the substrate. The complete im-plantation operation must be performed in a vacuum.

The high-velocity impact of ions on the silicon surface damages the latticestructure and results in lower electron mobilities. This condition is undesirable, butthe damage can be repaired by an annealing step, which involves heating the sub-strate to relatively low temperatures, usually 400° to 800°C, for a period of 15 to 30min. Annealing provides the energy that the silicon lattice needs to rearrange andmend itself.

Another important function of annealing is driving in the implanted dopants.Implantation alone imbeds the dopants less than half a micron below the siliconsurface; annealing enables the dopants to diffuse to a more desirable depth of a fewmicrons.

Aperture X-V beamdeflector

lon beam

Mass Separator ,,........, .....,..... Target

Accelerator n -- -- Indexing

Source Magnet Wafers

FIGURE 28.24 Schematic illustration of an apparatus for ion implantation.

Section 28.9 Diffusion and lon Implantation 8| 7


28.|0 Metallization and Testing

The preceding sections focused on device fabrication. Generating a complete andfunctional integrated circuit requires that these devices be interconnected, and this

must take place on a number of levels (Fig. 2826). Interconnections are made withmetals that exhibit low electrical resistance and good adhesion to dielectric insulatorsurfaces. Aluminum and aluminum-copper alloys remain the most commonly used

materials for this purpose in VLSI technology today.However, as device dimensions continue to shrink, electromigration has become

more of a concern with aluminum interconnects. Electromigration is the process by

which aluminum atoms are moved physically by the impact of drifting electronsunder high currents. In extreme cases, electromigration can lead to severed or shortedmetal lines. Solutions to the problem include (a) the addition of sandwiched metallayers such as tungsten and titanium, and, more recently, (b) the use of pure copper,

which displays lower resistivity and has significantly better electromigration perform-ance than aluminum.

Metals are deposited by standard deposition techniques, and interconnectionpatterns are generated through lithographic and etching processes, as previously

described. Modern ICs typically have one to six layers of metallization, each layer of

metal being insulated by a dielectric.

Level O-I nterconnects l ,- ---- L -DIP .

le;V§;1 g,,g_

,';sz::,i.,;z;"*@° au f

Level 3-Busses Level 4-Cableharness

it éismem i|m¢r¢¢5n§¢fa°5Level example method

Level O Transistor within an IC IC metalllzation

ICs, other discrete Package leads orLevel 1 components module interconnections

Level 2 IC packages Printed circuit board

Level 3 Printed circuit boards Connectors (busses)

Level 4 Chassis or box Connectors/Cableharnesses

Level 5 System, e.g., computer

FIGURE 28.26 Connections between elements in the hierarchy for integrated circuts

Section 28.10 Metallization and Testing 8

Planarization (i.e., producing a planar surface) of these interlayer dielectrics is

critical to the reduction of metal shorts and the line width variation of the intercon-nect. A common method used to achieve a planar surface is a uniform oxide-etchprocess that smoothens out the peaks and valleys of the dielectric layer.

However, today’s standard for planarizing high-density interconnects hasquickly become chemical-mechanical polishing (CMP), described in Section 26.7.This process entails physically polishing the wafer surface in a manner similar tothat by which a disc or belt sander flattens the ridges in a piece of wood. A typicalCMP process combines an abrasive medium with a polishing compound or slurryand can polish a wafer to within 0.03 /.tm of being perfectly flat, with a Rq rough-ness (see Section 4.4) on the order of 0.1 nm for a new, bare silicon wafer.

Layers of metal are connected together by vias, and access to the devices on thesubstrate is achieved through contacts (Fig. 28.27). In recent years, as devices havebecome smaller and faster, the size and speed of some chips have become limited bythe metallization process itself.

Wafer processing is completed upon application of a passivation layer, usuallysilicon nitride (Si3N4). The silicon nitride acts as a barrier to sodium ions and alsoprovides excellent scratch resistance.

The next step is to test each of the individual circuits on the wafer (Fig. 28.28).Each chip, also known as a die, is tested by a computer-controlled probe platformcontaining needle-like probes that access the bonding pads on the die. The probesare of two forms:

I. Test patterns or structures. The probe measures test structures (often outsideof the active dice) placed in the scribe line (the empty space between dies).These probes consist of transistors and interconnect structures that measurevarious processing parameters, such as resistivity, contact resistance, andelectroinigration.

2. Direct probe. This approach uses 100% testing on the bond pads of each die.

Via Second-levelmetal

metal

n y ,.

(H) (D)

FIGURE 28.27 (a) Scanning-electron microscope (SEM) photograph of a two-level metalinterconnect. Note the varying surface topography. (b) Schematic illustration of a two-levelmetal interconnect structure. Source: (a) Courtesy of National Semiconductor Corporation.(b) After R.C. jaeger.

First-level Si02

Silicon


FIGURE 28.28 A probe (top center) checking for defects in a Wafer; an ink mark is placed oneach defective die. Source: Courtesy of Intel Corp.

The platform scans across the Wafer and uses computer-generated timingwaveforms to test whether each circuit is functioning properly. If a defective chip is

encountered, it is marked with a drop of ink. Up to one-third of the cost of a micro-electronic circuit can be incurred during this testing.

After the Wafer-level testing is completed, back grinding may be done to re-move a large amount of the original substrate. The final die thickness depends on thepackaging requirement, but anywhere from 25 to 75% of the wafer thickness maybe removed. After back grinding, each die is separated from the Wafer. Diamondsau/ing is a commonly used separation technique and results in very straight edgeswith minimal chipping and cracking damage. The chips are then sorted, the func-tional dice are sent on for packaging, and the inked dice are discarded.

28.ll Wire Bonding and Packaging

The Working dice must be attached to a more rugged foundation to ensure reliability.One simple method is to fasten a die to its packaging material with an epoxy cement;another method makes use of a eutectic bond made by heating metal-alloy systems(see Section 4.3). One Widely used mixture is 96.4% Au and 3.6% Si, and it has aeutectic point at 370°C.

Once the chip has been attached to its substrate, it must be connected electri-cally to the package leads. This is accomplished by wire bonding very thin (25 /J.m

diameter) gold Wires from the package leads to bonding pads located around theperimeter or down the center of the die (Fig. 2829). The bonding pads on the dieare typically drawn at 75 to 100 /.tm per side, and the bond wires are attached bymeans of thermocompression, ultrasonic, or thermosonic techniques (Fig. 2830).

The connected circuit is now ready for final packaging. The packaging processlargely determines the overall cost of each completed IC, since the circuits are mass

Section 28.11 Wire Bonding and Packaging

(a) (D) (C)

FIGURE 28.29 (a) SEM photograph of Wire bonds connecting package leads (left-handside) to die bonding pads. (b) and (c) Detailed views of (a). Source: Courtesy of MicronTechnology, Inc.

G ld

Wim °'amP""' ' O me ' 'Force Gold wireQE Bomd Arcgenerator_°" Bond Dad M

DIG Die Package lead

1.Arcing forms gold ball 2. Ball bonds while 3. Position tip overapplying neat and/or package leadultrasonic vibration

_ -ForceWife loop Wire loop if

Die Package lead Die Package lead

4. Stitch bond on lead 5. Break wire

FIGURE 28.30 Schematic illustration of thermosonic Welding of gold wires from packageleads to bonding pads.

produced on the Wafer, but are then packaged individually. Packages are available ina Wide variety of styles; the appropriate one must reflect the operating requirements.Consideration of a circuit’s package includes the chip size, number of external leads,operating environment, heat dissipation, and power requirements. For example, ICsused for military and industrial applications require packages of particularly highstrength, toughness, and temperature resistance.

Packages are produced from polymers, metals, or ceramics. Metal containersare produced from alloys such as Kovar (an iron-cobalt-nickel alloy with a lowcoefficient of expansion; see Section 3.6), which provide a hermetic seal and goodthermal conductivity, but are limited in the number of leads that can be used.Ceramic packages usually are produced from aluminum oxide (AIZO3), are hermetic,


Ceramic cover

Moldingcompound as

fa Xe io »o Monollthic circuit die B°“d W"eS Eutectic Bonding pad preform (fYPiCa| 10 D|aC9S)¥- ,i, l 5

2; Glass seal 43 I (typical for fy 21

Spotpme ' 10leads) Lead frame _ Die Die-support B0'“d'"Q Wlfe

Paddle /’ A `*= Ceramic67 package base10

(al (D)

So|der Signal- Wire Mold Die Plated copper gg ground via bond compound pad conductor

Through-hole Buttjoint an ~

Solder BT epoxy lC Thermal- SolderCrow’s foot Gull wing mask PCB ground via bump

(C) (Ol)

FIGURE 28.3| Schematic illustrations of various IC packages: (a) dual-in-line package(DIP); (b) flat ceramic package; (c) common surface-mount configurations; (d) ball-gridarrays.

and have good thermal conductivity, but have higher lead counts than metal pack-ages; however, they are also more expensive. Plastic packages are inexpensive andhave high lead counts, but they have high thermal resistance and are not hermetic.

An older style of packaging is the dual-in-line package (DIP), shovvn schemat-ically in Fig. 28.31a. Characterized by lovv cost and ease of handling, DIP packagesare made of thermoplastics, epoxies, or ceramics and can have from 2 to 500 exter-nal leads. Designed for use over a broader temperature range and in high-reliabilityand military applications, ceramic packages cost considerably more than plasticpackages.

Figure 28.31b shows a flat ceramic package in which the package and all ofthe leads are in the same plane. This package style does not offer the ease of han-dling or the modular design of the DIP package. For that reason, it usually is affixedpermanently to a multiple-level circuit board in which the lovv profile of the flatpackage is necessary.

Surface-mount packages have become common for today’s integrated circuits.Some examples are shown in Fig. 28.31c, Where it can be seen that the main differ-ence among them is in the shape of the connectors. The DIP connection to the sur-face board is z/ia prongs (which are inserted into corresponding holes), while asurface mount is soldered onto a specially fabricated pad or land-a raised solderplatform for interconnections among components in a printed circuit board.

Section 28.11 Wire Bonding and Packaging

Package size and layouts are selected from standard patterns and usually requireadhesive bonding of the package to the board, followed by Wave soldering of theconnections, described in Section 32.3.3.

Faster and more versatile chips require increasingly tightly spaced connections.Pin-grid arrays (PGAS) use tightly packed pins that connect onto printed circuitboards by way of through-holes. However, PGAS and other in-line and surface-mount packages are extremely susceptible to plastic deformation of the wires andlegs, especially with small-diameter, closely spaced wires. One way of achieving tightpacking of connections and avoiding the difficulties of slender connections is

through ball-grid arrays (BGAS), as shown in Fig. 28.31d. This type of array has asolder-plated coating on a number of closely spaced metal balls on the underside ofthe package. The spacing between the balls can be as small as 5 0 um, but more com-monly it is standardized as 1.0 mm, 1.27 mm, or 1.5 mm.

Although BGAS can be designed with over 1000 connections, this is extremelyrare and usually 200 to 300 connections are sufficient for demanding applications.By using reflow soldering (Section 32.3.3), the solder serves to center the BGA bysurface tension, resulting in well-defined electrical connections for each ball. Afterthe chip has been sealed in the package, it undergoes final testing. Because one ofthe main purposes of packaging is isolation from the environment, testing at thisstage usually involves heat, humidity, mechanical shock, corrosion, and vibration.Destructive tests also are performed to investigate the effectiveness of sealing.

Chip on Board. Chip on board (COB) designs refer to the direct placement of chipsonto an adhesive layer on a circuit board. Electrical connections are then made by wirebonding the chips directly to the pads on the circuit board. After wire bonding, final en-capsulation with an epoxy is necessary not only to attach the IC package more securelyto the printed circuit board, but also to transfer heat evenly during its operation.

Flip-chip on Board. The Flip~c/vip on Board (FGB) technology, illustrated inFig. 28.32, involves the direct placement of a chip with solder bumps onto an array ofpads on the circuit board. The main advantage to flip chips (and ball-grid array pack-ages) is that the space around the package normally reserved for bond pads is saved.Thus, a higher level of miniaturization can be achieved.

System in Package. A trend that allows for more compact devices involves incor-porating more than one integrated circuit into a package. Figure 28.33 illustrates themajor categories of Silicon in package (SiP) designs. Although these packages can be

'III'

3. 4.

FIGURE 28.32 Illustration of flip-chip technology. Flip-chip package with 1. solder-platedmetal balls and pads on the printed circuit board; 2. flux application and placement; 3. reflowsoldering; 4. encapsulation.

24 Chapter 28 Fabrication of lviicroelectronic Devices

integrated horizontally, vertical integration through stacked or embedded structures(Figs. 28.33b and c) has the advantage of achieving performance increases overconventional packages. These benefits have been described as “more than Moore”(see Example 281), although SiPs also have other advantages as Well, namely, that

First level Second levelconnection connection

I I Flip chip type

(2)

Wire bonds r e as at §X.. ,..,. ..,».....`.........ILZIZ" ” "”" FWZ., , V Q re

is as x flip Chip type Flip chip type

Thin slide M ..,.. n

Thin die- BGA packageattach film solder balls

ff \f ‘glint \3' ‘v ¢¢ ,,‘- ,, I

» 4 “Krg~`\ " ~ f= |1|¢ :__‘:i`: f':‘5tt:‘ 6 "4 ~ 35§§}§;j"‘ y " .._ ,_!V’., IV E 11

'i 4 e wit# ~ is ‘ ti s s s

gt is f==§=§‘;’;` Eii* 23

5 ' 3 g a x A

=

Q

BGA packageinterposer substrate

(bi

Through-hole electrode

Silicon through-hole electrode Silicon through-hole electrode

:f 2:-E ilUQ QS

P K Ei ac age

Substrate e;_§€;s`e;;ee§€;§€;§e;3°e_(C)

Chip (WLP) Embedded + 3D Chip embeddedchip on surface type type

WLP Emb dded + chip onsurface type

(dl

FIGURE 28.33 Major categories of system-in-package designs. (a) Horizontal placement, or

multichip modules (MCl\/Is); (b) interposer-type stacked structure; (c) interposerless stackedstructure with through-silicon vias; (d) embedded structure. WLP = Wafer level package.

Section 28.12

they present a reduced size and less noise, and cross talk between chips can be betterisolated; also, individual chips can be upgraded more easily. These packages are morecomplex, require higher power density and associated heat extraction, and are moreexpensive, than conventional packages.

SiP packages can, however, be made very simple by incorporating more thanone chip inside a single package, as shown in Fig. 28.33a. To preserve area on a cir-cuit board, chips and/or flip chips can be stacked and bonded to a circuit board, asillustrated in Fig. 28.33b. Here, an interposing layer (commonly an adhesive) sepa-rates the chips and electrically isolates adjacent layers. An alternative is to employ aso-called interposerless structure using through-silicon vias (TSVS) instead of wirebonding to provide electrical connections to all layers. TSVS are sometimes consid-ered a packaging feature, but it has been noted that this is perhaps a case of 3D in-tegration ofa wafer, as shown in Fig. 28.330

28.|2 Yield and Reliability

Yield is defined as the ratio of functional chips to the total number of chips pro-duced. The overall yield of the total IC manufacturing process is the product of thewafer yield, bonding yield, packaging yield, and test yield. This quantity can rangefrom only a few percent for new processes to more than 90% for mature manufac-turing lines. Most yield loss occurs during wafer processing due to its more complexnature. Wafers are commonly separated into regions of good and bad chips. Failuresat this stage can arise from point defects (such as oxide pinholes), film contamina-tion, metal particles, and area defects (such as uneven film deposition or nonunifor-mity of the etch).

A major concern about completed ICs is their reliability and failure rate. Sinceno device has an infinite lifetime, statistical methods are used to characterize the ex-pected lifetimes and failure rates of microelectronic devices. The unit of failure rateis the FIT, defined as one failure per 1 billion device-hours. However, complete sys-tems may have millions of devices, so the overall failure rate in entire systems is cor-respondingly higher.

Equally important in failure analysis is determining the failure mechanism-that is, the actual process that causes the device to fail. Common failures due to pro-cessing involve the following:

° Diffusion regions (nonuniform current flow and junction breakdown).° Oxide layers (dielectric breakdown and accumulation of surface charge).° Lithography (uneven definition of features and mask misalignment).° Metal layers (poor contact and electromigration resulting from high current

densities).° Other failures originating in improper chip mounting, poorly formed wire

bonds, or loss of the package’s hermetic seal.

Because device lifetimes are very long, it is impractical to study device failureunder normal operating conditions. One method of studying failures efficiently is

accelerated life testing, which involves accelerating the conditions whose effectscause device breakdown. Cyclic variations in temperature, humidity, voltage, andcurrent are used to stress the components. Chip mounting and packaging arestrained by cyclical temperature variations. The statistical data taken from thesetests are then used to predict device-failure modes and device life under normaloperating conditions.

Yield and Reliability 82


28.13 Printed Circuit Boards

Packaged ICs seldom are used alone; rather, they usually are combined with otherICs to serve as building blocks of a yet larger system. A printed circuit board (PCB)

is the substrate for the final interconnections among all of the completed chips andserves as the communication link between the outside world and the microelectroniccircuitry within each packaged IC. In addition to possessing ICs, circuit boards usu-ally contain discrete circuit components (such as resistors and capacitors), whichtake up too much “real estate” on the limited silicon surface, have special power-dissipation requirements, or cannot be implemented on a chip. Other commondiscrete components are inductors (which cannot be integrated onto the silicon sur-face), high-performance transistors, large capacitors, precision resistors, and crystals(for frequency control).

A PCB is basically a plastic (resin) material containing several layers of copperfoil (Fig. 2834). Single-sided PCBs have copper tracks on only one side of an insu-lating substrate; double-sided boards have copper tracks on both sides. Multilayeredboards also can be constructed from alternating layers of copper and insulator, butsingle-sided boards are the simplest form of circuit board.

Double-sided boards usually must have locations where electrical connectivityis established between the features on both sides of the board; this is accomplishedwith vias, as shown in Fig. 28.34. Multilayered boards can have partial, buried, orthrough-hole vias to allow for extremely flexible PCBs. Double-sided and multilay-ered boards are beneficial, because IC packages can be bonded to both sides of theboard, allowing for more compact designs.

The insulating material is usually an epoxy resin 0.25 to 3 mm thick, rein-forced with an epoxy-glass fiber and is referred to as E-glass (see Section 9.2.1).The assembly is produced by impregnating sheets of glass fiber with epoxy andpressing the layers together between hot plates or rolls. The heat and pressure curethe board, resulting in a stiff and strong basis for printed circuit boards.

Surface signalt

DIP package Insertion hole Buried ` rackvia hole Hi .gl/I A Internal signal track

Solder 1 Insulation il if layers

Lead g)Surface-mount

Part|ally_bu|;ied |andvia oe ......., ,,,,.,, InternalJi Gull wing signal track »---f surface-mount lead

removed for clarity *ZVia hole

FIGURE 28.34 Printed circuit board structures and design features.

Boards are first sheared to a desired size, and about 3-mm-diameter locatingholes are then drilled or punched into the board’s corners to permit alignment andproper location of the board within the chip-insertion machines. Holes for vias andconnections are punched or produced through CNC drilling (Section 37.3); stacksof boards can be drilled simultaneously to increase production rates.

The conductive patterns on circuit boards are defined by lithography, althoughoriginally they were produced through screen-printing technologies-hence the termprinted circuit board or printed wiring board (PWB). In the subtractii/e inet/ood, acopper foil is bonded to the circuit board. The desired pattern on the board is de-fined by a positive mask developed through photolithography, and the remainingcopper is removed through wet etching. In the additive inet/rod, a negative mask is

placed directly onto an insulator substrate to define the desired shape. Electrolessplating and electroplating of copper serve to define the connections, tracks, andlands on the circuit board.

The ICs and other discrete components are then fastened to the board by sol-dering. This is the final step in making both the ICs and the microelectronic devicesthey contain into larger systems through connections on PCBs. Wave soldering andreflow paste soldering (see Section 32.3.3 and Example 32.1) are the preferredmethods of soldering ICs onto circuit boards.

Some of the design considerations in laying out PCBs are the following:

l. Wave soldering should be used only on one side of the board; thus, allthrough-hole mounted components should be inserted from the same side ofthe board. Surface-mount devices placed on the insertion side of the boardmust be reflow soldered in place; surface-mount devices on the lead side can bewave soldered.

2. To allow good solder flow in wave soldering, IC packages should be laid outcarefully on the PCB. Inserting the packages in the same direction is advanta-geous for automated placing, because random orientations can cause problemsin the flow of solder across all of the connections.

3. The spacing of ICs is determined mainly by the need to remove heat duringthe operation. Sufficient clearance between packages and adjacent boards is

required to allow forced airflow and heat convection.

4. There should also be sufficient space around each IC package to allow forreworking and repairing without disturbing adjacent devices.

SUMMARY

° The microelectronics industry continues to develop rapidly, and possibilities fornew device concepts and circuit designs appear to be endless. The fabrication ofmicroelectronic devices and integrated circuits involves several different typesof processes, many of which have been adapted from those of other fields ofmanufacturing.

° A rough shape of single-crystal silicon is first obtained from the Czochralskiprocess. This shape is ground to a cylinder of well-controlled dimensions, and anotch or flat is machined into the cylinder. The cylinder is then sliced into wafers,which are ground on their edges and subjected to chemical-mechanical polishingto complete the wafer.

Summary


KEY TERMS

Accelerated-life testingBondingChemical-mechanical

polishingChemical-vapor depositionChipChip on boardContactsCzochralski processDie

DiffusionDopantsDry etchingDry oxidationDual-in-line packageElectromigration

After bare wafers have been prepared, they undergo repeated oxidation or filmdeposition and lithographic or etching steps to open windows in the oxide layerin order to access the silicon substrate.

Wet etching is isotropic and relatively fast. However, dry etching (using gas plas-mas) is anisotropic and allows for more accurate lithography and large-scale inte-gration of integrated circuits.

After each of the processing cycles is completed, dopants are introduced into var-ious regions of the silicon structure through diffusion and ion implantation. Thedevices are then interconnected by multiple metal layers, and the completed cir-cuit is packaged and made accessible through electrical connections.

Lastly, the packaged circuit and other discrete devices are soldered to a printedcircuit board for final installation.

Epitaxy Micromolding in capillaries Silicon

Etching Microtransfer molding Soft lithographyEvaporation Oxidation SputteringFailure rate Packaging Surface-mount packageFilm deposition Photoresist System in packageFlip-chip on board Planarization Very large scale integrationGallium arsenide Postbaking ViasIntegrated circuit Prebaking Wafer

Ion implantation Printed circuit board Wafer-scale integrationLine width Registration Wet etching

Lithography Reliability Wet oxidationMasking Reticle Wire bondingMetal-oxide-semiconductor SCALPEL Yield

field-effect transistor Selective oxidationMetallization SelectivityMicrocontact printing Semiconductor

BIBLIOGRAPHY

Campbell, S.A., The Science and Engineering of Micro-electronic Fabrication, 2nd ed., Oxford University Press,2001.

Coombs, C.F., ]r. (ed.), Printed Circuits Handbook, 6th ed.,McGraw-Hill, 2007.

Doering, R., and Nishi, Y., Handbook of SemiconductorManufacturing Technology, 2nd. ed., CRC Press,2008.

Harper, C_A. (ed.), Electronic Packaging and InterconnectionHandbook, 4th ed., McGraw-Hill, 2004.

Humpston, G., and Jacobson, D.M., Principles of Soldering,ASM International, 2004.

International Technology Roadmap for Semiconductors,published annually, www.itrs.org.

jackson, K.A., and Schroter, W (eds.), Handbook ofSemiconductor Technology, Vol. 2: Processing ofSemiconductors, Wiley, 2000.

]udd, M., and Brindley, K., Soldering in ElectronicsAssembly, 2nd ed., Newnes, 1999.

Khandour, R.S., Printed Circuit Boards, McGraw-Hill, 2005.Lambert, L.P., Soldering for Electronic Assemblies, Marcel

Dekker, 1988.Lau, ].H. (ed.), Electronic Packaging: Design, Materials,

Process, and Reliability, McGraw-Hill, 1998.Madou, M.]., Manufacturing Techniques for Microfabrication

and Nanotechnology, CRC Press, 2009.---, Applications of Microfabrication and Nano-technology, CRC Press, 2009.

Mahajan, S., and Harsha, K.S.S., Principles of Growth andProcessing of Semiconductors, McGraw-Hill, 1998.

Marks, L., Printed Circuit Assembly Design, McGraw-Hill,2000.

Matisoff, B.S., Handbook of Electronics Manufacturing,3rd ed., Chapman 85 Hall, 1996.

May, G.S., and Spanos, C.]., Fundamentals of SemiconductorManufacturing and Process Control, Wiley, 2006.

Ohring, M., Reliability and Failure of Electronic Materialsand Devices, Academic Press, 1999.

Rizvi, S., Handbook of Photomask Manufacturing Technology,CRC Press, 2005.

Runyan, WR., and Shaffner, T.]., Semiconductor Measure-ments and Instrumentation, 2nd ed., McGraw-Hill,1998.

Schroder, D.K., Semiconductor Material and DeviceCharacterization, 3rd ed., Wiley-Interscience, 2006.

Taur, Y., and Ning, T.H., Fundamentals of Modern VLSIDevices, Cambridge, 1998.

REVIEW QUESTIONS

Qualitative Problems 829

Tummala, R., Rymaszewski, E.]., and Klopfenstein, A.G.,Microelectronics Packaging Fundamentals, Chapman Sc

Hall, 1999.Ulrich, R.K., and Brown, WD. (eds.), Advanced Electronic

Packaging, Wiley, 2006.Van Zant, P., Microchip Fabrication, Sth ed., McGraw-Hill,

2004.Wolf, WH., Modern VLSI Design: Systems on Silicon, 2nd ed.,

Prentice Hall, 1998Yeap, G., Practical Low Power Digital VLSI Design, Kluwer

Academic Pub., 1997.Yu, P.Y., and Cardona, M., Fundamentals of Semiconductors:

Physics and Materials Properties, Springer, 2006.

28.l. Define the terms wafer, chip, die, device, integratedcircuit, line width, registration, surface mount, accelerated-life testing, and yield.

28.2. Why is silicon the semiconductor most used in ICtechnology?

28.3. What do the abbreviations BJT, MOSFET, VLSI, IC,CVD, CMP, and DIP stand for?

28.4. Explain the differences between wet and dry oxidation.28.5. What are the purposes of prebaking and postbakingin lithography?

28.6. Define selectivity and isotropy and their importancein relation to etching.

28.7. Compare the diffusion and ion-implantation processes.

28.8. Explain the difference between evaporation andsputtering.

28.9. What are the levels of interconnection?

28.|0. Which is cleaner, a Class-0.35 or a Class-0.035 cleanroom?

QUALITATIVE PROBLEMS

28.| I. Comment on your observations regarding the con-tents of Fig. V.1.

28.|2. Describe how n~type and [7-type dopants differ.

28.l3. How is epitaxy different from other techniques usedfor deposition? Explain.

28.I4. Note that, in a horizontal epitaxial reactor (seeFig. P28.14), the wafers are placed on a stage (susceptor) thatis tilted by a small amount, usually 1° to 3°. Explain why thisis done.

Inductionheating coil \

O O O O O O OWafers

Gas inlet -> ->VentSusceptor

0 0 0 0 0 0 O

FIGURE P28. I 4

28.l5. The table that follows describes three wafer-manufacturing changes: increasing the wafer diameter, reduc-ing the chip size, and increasing process complexity. Completethe table by filling in “increase,” “decrease,” or “no change,”and indicate the effect that each change would have on thewafer yield and on the overall number of functional chips.

Effects of Manufacturing Changes

Number ofChange Wafer yield functional chips

Increase wafer diameterReduce chip sizeIncrease process complexity


28.|6. The speed of a transistor is directly proportional tothe width of its polysilicon gate; thus, a narrower gate resultsin a faster transistor and a wider gate in a slower transistor.Knowing that the manufacturing process has a certain varia-tion for the gate width (say, j;0.1 ,u.m), how would a designermodify the gate size of a critical circuit in order to minimizeits variation in speed? Are there any negative effects of thischange?

28.l7. A common problem in ion implantation is channel-ing, in which the high-velocity ions travel deep into the mate-rial via channels along the crystallographic planes beforefinally being stopped. How could this effect be avoided?Explain.

28.l8. Examine the hole profiles shown in Fig. P28.18 andexplain how they might be produced.

QUANTITATIVE PROBLEMS

28.l9. Referring to Fig. 28.23, sketch the shape of the holesgenerated from a circular mask.

WWWi\-/ii from

(d) (G) (f)

noun: |>za.|a

|I28.20. A certain wafer manufacturer produces two equal-sized wafers, one containing 500 chips and the other contain-ing 200. After testing, it is observed that 50 chips on eachwafer are defective. What are the yields of these two wafers?Can any relationship be drawn between chip size and yield?

|]28.2|. A chlorine-based polysilicon etching process dis-plays a polysilicon-to-resist selectivity of 5:1 and a polysilicon-to-oxide selectivity of 60:1. How much resist and exposedoxide will be consumed in etching 3500 A of polysilicon?What would the polysilicon-to-oxide selectivity have to be in

order to reduce the loss to only 40 A of exposed oxide?

|]28.22. During a processing sequence, three silicon-dioxide layers are grown by oxidation to 2500 A, 4000 A, and1500 A, respectively. How much of the silicon substrate is

consumed?

|]28.23. A certain design rule calls for metal lines to be noless than 2 /rm wide. If a 1-/.tm-thick metal layer is to be wetetched, what is the minimum photoresist width allowed(assuming that the wet etching is perfectly isotropic)? Whatwould be the minimum photoresist width if a perfectlyanisotropic dry-etching process is used?

SYNTHESIS, DESIGN, AND PROJECTS

28.24. Describe products that would not exist today with-out the knowledge and techniques described in this chapter.Explain.

28.25. Inspect various electronic and computer equipment,take them apart as much as you can, and identify componentsthat may have been manufactured by the techniques de-scribed in this chapter.

28.26. Describe your understanding of the important fea-tures of clean rooms and how they are maintained.

28.27. Make a survey of the necessity for clean rooms in

various industries, including the medical, pharmacological,and aerospace industries, and what their requirements are.

28.28. Review the technical literature, and give further de-tails regarding the type and shape of the abrasive wheel used

in the wafer-cutting process shown in Step 2 in Fig. 28.2. (Seealso Chapter 26.)

28.29. List and discuss the technologies that have enabledthe manufacture of the products described in this chapter.

28.30. Microelectronic devices may be subjected to hostile en-vironments, such as high temperature, humidity, and vibration,as well as physical abuse, such as being dropped onto a hardsurface. Describe your thoughts on how you would go abouttesting these devices for their endurance under these conditions.Are there any industry standards regarding such tests? Explain.

28.3 I. Review the specific devices, shown in Fig. V2. Chooseany one of these devices, and investigate what they are, whattheir characteristics are, how they are manufactured, and whattheir costs are.

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