COVER STORY

IR DROP in High-Speed IC Packages and PCBs

Neckdowns, low-weight copper and Swiss cheese effectsare conspiring to wreak havoc on your high-speed design.Get the drop on them. by SAM CHITWOOD and JI ZHENG

Today’s low-voltage, high-current designs require DC IRdrop analysis for off-chip power distribution systems in orderto optimize end-to-end voltage margins for every device onthe distribution. This article will introduce the basics of IRdrop analysis, exemplify the significance of IR drop associat-ed with IC packages and PCBs, and demonstrate typical IRdrop simulations for the identification of problematic powerdistributions.

As system complexity and operational speeds increase,the power consumption of integrated circuits increases dra-matically. Additionally, the IC supply voltage continues todrop with the inevitable scaling of VLSI technology. With theswitch to 90 nm technologies from 130 nm technology, sup-ply voltages have shrunk to 1.2 V and below. According tothe International Technology Roadmap for Semiconductors,1

this trend is expected to continue. See FIGURE 1. Reducing the nominal supply voltage is accompanied by

a reduction in device noise margins, making components

more vulnerable to power supply noise. This noise consists ofthe dynamic AC voltage fluctuation due to the frequency-dependent distributed parasitics inherent in today’s powerdistribution systems, and the DC voltage drop (i.e., “IR”drop, according to Ohm’s Law V=I*R, where R is the equiv-alent path DC resistance between the source location and thedevice location and I is the average current the chip drawsfrom the supply).

IR Drop BasicsAs illustrated in FIGURE 2, Ohm’s Law relates conductioncurrent to voltage drop, and at DC, the relation coefficient isa constant representing the resistance of the conductor. Con-ductors also dissipate power due to their resistance. Bothvoltage drop and power dissipation are proportional to theresistance of the conductor.

Resistance is determined by a metal’s conductivity andthe path geometry of the conduction current. Conductivity(σ) is the measure of a metal’s capability to conduct currentand is an intrinsic property of the material. The most com-mon metal used in IC packages and PCBs is copper, whoseconductivity is approximately 5.8 X 107 siemens per meter.

DC resistance can be found analytically for conductors ofsimple geometries, such as the metal bar of uniform cross-section shown in FIGURE 3. The sheet resistance concept isintroduced in FIGURE 4 as plane structures are widely used inIC package and PCB power distribution systems. Finally, theclosed formula for plane resistance between two via contactsis given in FIGURE 5.

Various kinds of metal structures including planes, viasand traces constitute the power distribution system betweenthe supply source and one or more IC components. The sup-ply source is typically implemented as a DC-DC converterand referred to as a voltage regulator module (VRM).

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1.3

1.2

1.1

1.0

0.9

0.82003 2004 2005 2006 2007 2008 2009

Year

Volts

Chip power supply - Vdd

FIGURE 1. ITRS projects the core IC supply voltages by year.

Assuming the current requirements aremet, the IR drop is determined by theeffective path resistance between theVRM and the IC components. In amicroelectronic system, the system’s IRdrop may be budgeted into three por-tions: on-chip, package and board.

On-chip IR drop has been exten-sively studied because the resistive lossis severe due to the fine feature-size (afew microns and below) of the on-diepower grid. On the other hand, pack-age and board-level IR drop have notbeen given much attention due to theirmuch smaller contribution to the over-all path resistance and hence voltagedrop. However, due to increased cur-rent requirements and reduced supplyvoltage noise margins, package andboard IR drop (in the range of tens tohundreds of millivolts) now can have asignificant impact on the operation ofhigh-speed devices.

Several factors contribute toincreased off-chip path resistances. Inmultilayer IC packages such as BGAs,for example, the power distributionusually traverses multiple layers fromthe balls to the controlled collapse chipconnect (C4) bumps, as shown in FIG-URE 6. These paths are much shorterthan those on the board; however,package power and ground planes usu-

ally require much more irregularshapes to accommodate the chip I/Obreakout and usually are not allowedto fill an entire plane. Many packagesalso contain a number of powerdomains, but a very limited number oflayers are available for their distribu-tion. Therefore, it is very common forpower distributions to contain com-plex shapes such as neckdowns (smallcopper widths for short lengths) andother non-ideal routing.

Printed circuit boards have theirown share of issues as well. In large,complex PCBs the power distributionsystem may have to traverse severalfeet of planes and traces to reach thefar-end devices. Therefore, far-enddevices will see a larger voltage dropcompared to devices closer to theVRM. The ICs themselves also con-

tribute to the board designers’ prob-lems. Higher-density, high-pin-countcomponents have large via fields andtheir associated anti-pads create a“Swiss cheese” effect in the power dis-tribution layers of both IC packagesand PCBs. See FIGURE 7 and FIGURE 8.This Swiss cheese effectively creates asmaller equivalent conductor of higherresistance. Finally, the situation hasbeen further exacerbated by materialsuppliers who have reduced their cop-per weights (thickness) to the IPC stan-dard minimums.

Because of the long distributionpaths, neckdowns, low weight copper,and Swiss cheese effects, it is possiblefor designs to deliver insufficient volt-age to some devices. Therefore, forhigh-current and low-voltage designs,it is becoming critically important toinclude package and board IR dropinto the total noise budget of the sys-tem.

IR Drop Simulation Unfortunately, calculating the IR dropof modern power distributions is aformidable task. The amount of infor-mation required is not overwhelming,but the complexity of the distribu-tion’s geometry is daunting. To accu-

APRIL 2005 PRINTED CIRCUIT DESIGN & MANUFACTURE 17

+ V

R

-I

Dissipated powerP = V . I= I2 R

= V2 / R

V = I . RResistance (ohms)

G = 1R

Conductance (Siemens)

FIGURE 2. Ohm’s Law and power dissipation equations are shown.

R =

S

1

2

V

l

J, E, I

l

� · S

I = ∫ J · ds = J · SS

V = ∫ E · dl = E · l 2

1

IS

= Vl

�

FIGURE 3. Example details the resistance of a metal bar of uniformcross-section.

The resistance Rs of a plane conductorfor a unit length and unit width is calledthe surface resistivity (ohms per square).

Rs = =

R = Rs ·

L

Wt

1σ · t

lw

t

ρ

FIGURE 4.The basics of sheet resist-ance are useful when determining IRdrop for IC package and PCB structures that contain planes.

planecurrent

Via1 (radius=a)Via2 (radius=a)

R =cosh-1 (d / 2a)

π · σ · t

td

FIGURE 5. Plane resistance is depictedbetween two via contacts.

FIGURE 6.This cross-section showsa view of BGA package power distribution from bumps to balls.

FIGURE 7. IR drop (in volts) is depict-ed for a typical PCB distribution.

rately analyze package and board IRdrop, the actual geometry of the dis-tribution must be properly modeledand simulated.

Let us investigate the single-layerdistribution example shown in FIGURE7. Three large ASICs draw currentfrom this rail; two devices are on theupper portion of the distribution andthe third device is on the bottom. TheVRM is located on the left side of theboard. In addition to the layout, thedevice currents, the stackup and the

metal’s conductivity must be known.Figure 7 shows the IR drop at

every location along the distribution.The results indicate that the ASIC far-thest from the VRM will see 18.5 mVof IR drop, while the other ASICs havedrops of 11 mV and 14 mV. If thenominal voltage of this rail is 3.3 V, theIR drop is 0.5% of nominal. However,if the rail’s nominal is 1.2 V, the IRdrop is 1.5% of nominal. For systemswith noise budgets of +/- 5%, IR dropmust be allocated 30% of this budget,leaving only 70% for AC noise.

IR drop is not the only DC proper-ty of interest. Current produces a heat-ing effect in the planes and for somepackage designs, it must be accountedfor in the system’s thermal budget. Iftoo much current passes through asmall path, a potential hot spot candevelop. Neighboring planes may actas heatsinks, but Swiss cheese limitsthis effect as well. The effects of hotspots can range from insignificant tomelted dielectrics.

In addition to IR drop, simulationcalculates the current distribution on

the planes as well (see FIGURE 8). Thesedistributions quickly identify potentialhot spots and the results can beimported by system-level thermalanalysis tools.

DC analysis for off-chip power dis-tribution systems is becoming manda-tory for high-current, low-voltagedesigns. Simulation allows adjustmentof VRM nominals, strategic placementof sense lines and early identification ofproblematic distributions. Budgetingfor AC noise and system-level IR dropwill optimize the voltage margins forevery device on the distribution. PCD&M

SAM CHITWOOD is a field applicationengineer at Sigrity Inc. He can bereached at samchitwood@sigrity.com.JI ZHENG is a member of Sigrity’s sen-ior technical staff. He can be reached atjizheng@sigrity.com.

REFERENCES1. International Technology Roadmap for Semi-

conductors Web site: http://public.itrs.net.

COVER STORY

PRINTED CIRCUIT DESIGN & MANUFACTURE APRIL 200518

FIGURE 8. Current distribution is shownin a typical IC package layer.