integrated-circuit technologyj.guntzel/ine5442/csi_aulas05-08.pdf · 1 integrated-circuit...
TRANSCRIPT
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INTEGRATED-CIRCUIT TECHNOLOGY
1. Processing Steps
1.1. Photolitography
1.2. Oxidation
1.3. Layer Deposition
1.4. Etching
1.5. Diffusion
1.6 Backend: assembly, test
2. Bipolar Technology
3. CMOS Technology
0. Silicon crystal growth and wafer preparation
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CRYSTAL GROWTH
• Czochralski Process is a
Technique in Making
Single-Crystal Silicon
• A Solid Seed Crystal is
Rotated and Slowly
Extracted from a Pool of
Molten Si
• Requires Careful Control
to Give Crystals Desired
Purity and Dimensions
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Wafer Slicing & Polishing
The silicon ingot is grown and individual wafers are sliced.
The silicon ingot is sliced into
individual wafers, polished, and
cleaned.
silicon wafer
p+ silicon substrate
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Photoresist Coating Processes
p- epi
p+ substrate
field oxide
photoresist
PhotoresistsNegative Photoresist *
Positive Photoresist *
Other Ancillary Materials (Liquids)Edge Bead Removers *
Anti-Reflective Coatings *
Adhesion Promoters/Primers (HMDS) *
Rinsers/Thinners/Corrosion Inhibitors *
Contrast Enhancement Materials *
DevelopersTMAH *
Specialty Developers *
Inert GasesAr
N2
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Exposure Processes
p- epi
p+ substrate
field oxide
photoresist
ExposeKr + F2 (gas) *
Inert GasesN2
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1. Photolitography – Basic Concept
Photolitography – Basic Concept
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Photolitography using positive photoresist
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The simplest method of producing an oxide layer
consists of heating a silicon wafer in an oxidizing
atmosphere.
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Oxidation of the silicon surface
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6min20min1.7hWet O2
15min40min1.7h6h30hDry O2
1200°C1100°C1000°C900°C800°CAmbient
Times required to grow 0.1µµµµm of oxide on (III) silicon
Silicon Melting Point, 1410°C
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Selective SiO2 growth, using local oxidation
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Vapor deposition. PVD (a) and CVD(b).
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Chemical Vapor Deposition (CVD) Dielectric
* High proportion of the total product use
CVD DielectricO2
O3
TEOS *
TMP *
TEOSSource
LPCVDChamber
TransferChamber
Gas Inlet
Exhaust
RF Power
Wafer
MeteringPump
Inert MixingGas
Process Gas
Vaporizer
DirectLiquid
Injection
n-w ell
p-channel transistor
p-w ell
n-channel transistorp+ substrate
Metal 1insulator layer 2
Chemical Reactions
Si(OC2H5)4 + 9 O3 → SiO2 + 5 CO + 3 CO2 + 10 H2O
Process Conditions (ILD)
Flow Rate: 100 to 300 sccm
Pressure: 50 Torr to Atmospheric
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Epitaxy and mechanisms of
defect formation in the epitaxial layer
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Epitaxial Silicon DepositionGasInput Lamp
Module
QuartzLamps
Wafers
Susceptor
Exhaust
* High proportion of the total product use
Chemical Reactions
Silicon Deposition: HSiCl3 + H2 → Si + 3 HCl
Process Conditions
Flow Rates: 5 to 50 liters/min
Temperature: 900 to 1,100 degrees C.
Pressure: 100 Torr to Atmospheric
silicon wafer
p- silicon epi layer
p+ silicon substrate
Dopants
AsH3
B2H6
PH3
Etchant
HCl
Carriers
Ar
H2 *
N2
Silicon Sources
SiH4
H2SiCl2HSiCl3 *
SiCl4 *
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Wet etching.
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Dry etching.
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Conductor Etch
* High proportion of the total product use
EtchChambers
Cluster ToolConfiguration
TransferChamber
Loadlock
Wafers
RIE Chamber
TransferChamber
Gas Inlet
Exhaust
RF Power
Wafer
p+ substrate
p-w ell
n-channel transistor
n-w ell
p-channel transistor
source-drain areas
gate linew idth
gate oxide
Polysilicon EtchesHBr *
C2F6
SF6 *
NF3 *
O2
Aluminum EtchesBCl3 *
Cl2
DiluentsAr
He
N2
Chemical Reactions
Silicon Etch: Si + 4 HBr → SiBr4 + 2 H2
Aluminum Etch: Al + 2 Cl2 → AlCl4Process Conditions
Flow Rates: 100 to 300 sccm
Pressure: 10 to 500 mTorr
RF Power: 50 to 100 Watts
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Dielectric Etch
* High proportion of the total product use
EtchChambers
Cluster ToolConfiguration
TransferChamber
Loadlock
Wafers
RIE Chamber
TransferChamber
Gas Inlet
Exhaust
RF Power
Wafer
Contact locations
n-w ell
p-channel transistor
p-w ell
n-channel transistorp+ substrate
Chemical Reactions
Oxide Etch: SiO2 + C2F6 → SiF4 + CO2 + CF4 + 2 CO
Process Conditions
Flow Rates: 10 to 300 sccm
Pressure: 5 to 10 mTorr
RF Power: 100 to 200 Watts
Plasma Dielectric EtchesCHF3 *
CF4
C2F6
C3F8
CO *
DiluentsAr
He
N2
CO2
O2
SF6
SiF4
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Diffusion mechanism
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2.00.7Arsenic
2.10.8Antimony
4.61.60.5Phosphorus
7.33.61.50.9Boron
1200°C1100°C1000°C950°CDopant
Representative junction depths, in microns
(1020 atoms/cm3 source, 1016 atoms/cm3 background,
15min predeposition, 1h drive-in)
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Diffusion of dopants through a window in the SiO2 layer.
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Ion Implantation
180 kV
ResolvingAperture
Ion Source
Equipment Ground
Acceleration Tube
90°Analyzing Magnet
Terminal Ground
20 kV
Focus Neutral beam and beam path gated
Beam trap andgate plate
Wafer in waferprocess chamber
X - axisscanner
Y - axisscanner
Neutral beam trap and beam gate
GasesAr
AsH3
B11F3 *
He
N2
PH3
SiH4
SiF4
GeH4
SolidsGa
In
Sb
LiquidsAl(CH3)3
* High proportion of the total product use
junction depth
p- epi
p+ substrate
field oxide
photoresist mask
n-w ell
p-channel transistor
phosphorus
(-) ions
Process Conditions
Flow Rate: 5 sccm
Pressure: 10-5 Torr
Accelerating Voltage: 5 to 200 keV
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Chemical Mechanical Planarization (CMP)
* High proportion of the total product use.
Platen
PolishingHead
PadConditioner
Carousel
HeadSweep Slide
Load/UnloadStation
Wafer HandlingRobot & I/O
Polishing Pad
SlurryDelivery
Platen
WaferCarrier
Wafer
n-w ell
p-channel transistor
p-w ell
n-channel transistorp+ substrate
Backing (Carrier) FilmPolyurethane
PadPolyurethane
Pad ConditionerAbrasive
CMP (Oxide)Silica Slurry
KOH *
NH4OH
H2O
CMP (Metal)Alumina *
FeNO3
Process Conditions (Oxide)
Flow: 250 to 1000 ml/min
Particle Size: 100 to 250 nm
Concentration: 10 to 15%, 10.5 to 11.3 pH
Process Conditions (Metal)
Flow: 50 to 100 ml/min
Particle Size: 180 to 280 nm
Concentration: 3 to 7%, 4.1 - 4.4 pH
*
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Electrical Test Probe
Defective IC
Individual integrated circuits are tested to distinguish good
die from bad ones.
n-well
p-channel transistor
p-well
n-channel transistorp+ substrate
bonding padnitride
Metal 2
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Die Cut and AssemblyGood chips are attached to a lead frame package.
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Die Attach and Wire Bonding
lead frame gold wire
bonding pad
connecting pin
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Final Test
Chips are electrically tested under varying environmental conditions.
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2. Bipolar Technology
Diffusion of the buried layer. Segment of
the mask (a) and cross-section of
the npn transistor (b) after the diffusion.
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Island formation. Segment of the mask (a) and
cross-section of the npn transistor (b) after diffusion of
the p-type isolation.
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Transistor base p-type diffusion. Segment of the mask (a) and
cross-section of the npn transistor (b) after
base diffusion
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Emitter diffusion. Segment of the mask (a) and
cross-section of the npn transistor (b) after
emitter diffusion.
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Layout (a) and cross-section of the complete
npn transistor (b).
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Active regions in the n-well CMOS inverter.
Edges of active regions in the mask (a) and cross-section
of the inverter (b).
3. CMOS Technology
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Polysilicon region in the n-well CMOS inverter.
Window in the mask (a) and cross-section of the
inverter (b).
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Implantation of n-channel transistor drain and source.
Window in the n-select mask (a) and cross-section of the
inverter (b).
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CMOS inverter. Composite layout (a),
cross-section (b), and electrical diagram (c).
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References
1. W. Maly, Atlas of IC Technologies, Benjamin/Cummings Publications,
1987
2. Conrad T. Sorenson, “Semiconductor Manufacturing Technology:
Semiconductor Manufacturing Processes,”
http://www.erc.arizona.edu/Education/MME%20Course%20Materials/
MME%20Modules/Manufacturing%20Module/Manufac%20Overview.p
pt
3. Young Soon Song. et. al., “EE 4345 - Semiconductor Electronics
Design Project. Silicon Manufacturing,”
www.uta.edu/ronc/4345sp02/lectures/L09a_4345_Sp02.ppt