integrated circuit devices
DESCRIPTION
Integrated Circuit Devices. Professor Ali Javey Summer 2009. MOS Capacitors Reading: Chapter 16. MOS Capacitors. MOS: M etal- O xide- S emiconductor. MOS transistor. MOS capacitor. Ideal MOS Capacitor. Oxide has zero charge, and no current can pass through it. - PowerPoint PPT PresentationTRANSCRIPT
Integrated Circuit Devices
Professor Ali Javey
Summer 2009
MOS CapacitorsReading: Chapter 16
EE143 – Ali Javey
MOS: Metal-Oxide-Semiconductor
SiO2
metalgate
Si body
Vg
SiO2
gate
P-body
Vg
N+N+
MOS capacitor MOS transistor
MOS Capacitors
Ideal MOS Capacitor
– Oxide has zero charge, and no current can pass through it.
– No charge centers are present in the oxide or at the oxide-semiconductor interface.
– Semiconductor is uniformly doped M = S = + (EC – EF)FB
Ideal MOS CapacitorAt Equilibrium:
Ideal MOS CapacitorUnder Bias
– Let us ground the semiconductor and start applying different voltages, VG, to the gate
– VG can be positive, negative or zero with respect to the semiconductor
– EF,metal – EF,semiconductor = – q VG
– Since oxide has no charge (it’s an insulator with no available carriers or dopants), d Eoxide / dx = / = 0; meaning that the E-field inside the oxide is constant.
Inversion conditionIf we continue to increase the positive gate voltage, the bands at the semiconductor bends more strongly. At sufficiently high voltage, Ei can be below EF indicating large concentration of
electrons in the conduction band.
We say the material near the surface is “inverted”. The “inverted” layer is not gotten by chemical doping, but by applying E-field. Where did we get the electrons from?
When Ei(surface) – Ei(bulk) = 2 [EF – Ei(bulk)], the condition is start of “inversion”, and the voltage VG applied to gate is called VT (threshold voltage). For VG > VT, the Si surface is inverted.
Ideal MOS Capacitor – n-type Si
Electrostatic potential, (x)Define a new term, (x) taken to be the potential inside the semiconductor at
a given point x. [The symbol instead of V used in MOS work to avoid confusion with externally applied voltage, V]
)]((bulk)[1
)( ii xEEq
x
(surface)](bulk)[1
iiS EEq
](bulk)[1
FiF EEq
Potential at any point x
Surface potential
F > 0 means p-type F < 0 means n-type
| F | related to doping concentration
Electrostatic potential
S = 2F at the depletion-inversion
transition point (threshold voltage)
S is positive if the bands bend\ …….?
Charge Density - Accumulation
p-type silicon accumulation condition
The accumulation charges in the semiconductor are ……. , and appear
close to the surface and fall-offrapidly as x increases.
One can assume that the free carrier concentration at the oxide-semiconductor
interface is a -function.
M O S
VG < 0
p-Si
Accumulation of holes
Charge on metal = QM
Charge on semiconductor = (charge on metal)
|QAccumulation| = |QM|
x
Charge Density - Depletionp-type Si,
depletion conditionThe depletion charges in Si are
immobile ions - results in depletionlayer similar to that in pn
junction or Schottky diode.VG > 0
M O S
p-Si
Depletion of holes
wQM|q NA A W| = |QM| () (+)
If surface potential is s, then the depletion layer width W will be
SA
Si2 qN
W
Charge Density - Inversion
VG>>0
M O S
p-Si
Depletion of holes
wQM
Inversion electrons:-function-like
p-type Si, strong inversion
Once inversion charges appear, they remain close to the
surface since they are …….. Any additional voltage to the gate results in extra QM in gate and get compensated by extra inversion
electrons in semiconductor.
So, the depletion width does not change during inversion. Electrons appear as -function near the surface. Maximum depletion layer width W = WT
MOS C-V characteristics
•The measured MOS capacitance (called gate capacitance) varies with the applied gate voltage
– A very powerful diagnostic tool for identifying threshold voltage, oxide thickness, substrate doping concentration, and flat band voltage.
– It also tells you how close to an ideal MOSC your structure is.
•Measurement of C-V characteristics
– Apply any dc bias, and superimpose a small (15 mV) ac signal (typically 1 kHz – 1 MHz)
C-V: under accumulation
VG < 0
M O S
p-Si
Accumulation of holes
x
Consider p-type Si under accumulation.
VG < 0.Looks similar to parallelplate capacitor.
CG = Cox
where Cox = (ox A) / xox
CG is constant as a function of VG
C-V: under depletionDepletion condition:VG > 0
CG is Cox in series with Cs where Cs can be defined as “semiconductor capacitance”
Cox=ox A / xox
Cs = Si A / W
CG = Cox Cs / (Cox + CS)
sA
Si2
qNW
where s is surface potential
VG > 0
M O S
p-type Si
Depletion of holes
WQM
Cox Cs
CG decreases with increasing VG
C-V: under inversion (high frequency)
VG >>0
M O S
p-Si
Depletion of holes
WQM
Inversion electrons- function
Cox Cs
VG = VT and VG > VT
Inversion condition s = 2 F
FA
SiT 2
2
NqWW
At high frequency, inversionelectrons are not able to respondto ac voltage.
Cox=ox A / xox
Cs = Si A / WT
CG ( ) = Cox Cs / (Cox + CS)
CG will be constant for VG VT
At low frequency, the inversion electrons will be able to respond to the ac voltage. So, the gate capacitance will be equal to the “oxide capacitance” (similar to a parallel plate capacitance).
CG ( 0) = Cox
= ox A / xox
Ideal MOSC (p-type Si)
C-V: under inversion (low frequency)
CG increases for VG VT until it reaches Cox
CCox
accumulation depletion inversionVgVfb Vt
high frequency
low frequency