input output organisation
DESCRIPTION
Sanjeev Patel 4xTRANSCRIPT
INPU
T-OUTP
UT
ORGANIZAT
ION
BYMD
SH
AKEB AYAZ
8145
INTERFACE
A conversion of signal values may be required
raquo CPU(Electronics) HDD(Electromechanical and Electromagnet)
A synchronization mechanism may be needed
raquo The data transfer rate of peripherals is usually slower than the transfer rate of the CPU
Data codes and formats in peripherals differ from the word format in the CPU and Memory
The operating modes of peripherals are different from each other 4 modes
raquo Each peripherals must be controlled so as not to disturb the operation of other peripherals connected to the CPU
bull Special hardware components between the CPU and peripherals
bull Supervise and Synchronize all input and output transfers
IO BUS AND INTERFACE MODULES
IO BUS VERSUS MEMORY BUS
Computer buses can be used to communicate with memory and IO
1) Use two separate buses one for memory and the other for IO
bull IO Processor separate memory bus and IO bus
2) Use one common bus for both memory and IO but have separate control lines for each Isolated IO or IO Mapped IO
bull IN OUT IO Instruction
bull MOV or LD Memory readwrite Instruction
3) Use one common bus for memory and IO with common control lines Memory
Mapped IO
bull MOV or LD IO and Memory readwrite Instruction
4 IO port Data port A Data port B ControlStatusbull 8255 PIO ( port A B C ControlStatus )Address Decode bull CS RS1 RS0
Exam
ple
EXAMPLE OF IO INTERFACE
ASYNCHRONOUS DATA TRANSFER
Synchronous Data Transfer
bull All data transfers occur simultaneously during the occurrence of a clock pulse
bull Registers in the interface share a common clock with CPU registers
Asynchronous Data Transfer
bull Internal timing in each unit (CPU and Interface) is independent
bull Each unit uses its own private clock for internal registers
ASYNCHRONOUS DATA TRANSFER
Strobe Control signal to indicate the time at which data is being transmitted
1) Source-initiated strobe 2) Destination-initiated strobe
Destin
atio
n-in
itiate
d stro
be
Sourc
e-i
nit
iate
d s
trobe
ASYNCHRONOUS SERIAL TRANSFER
Synchronous transmission
raquo The two unit share a common clock frequency
raquo Bits are transmitted continuously at the rate dictated by the clock pulses
1048698 Asynchronous transmission
raquo Special bits are inserted at both ends of the character code
raquo Each character consists of three parts
1048698 1) start bit always ldquo0rdquo indicate the beginning of a character
1048698 2) character bits data
1048698 3) stop bit always ldquo1rdquo
ASYNCHRONOUS TRANSMISSION RULES NO PARITY
raquo When a character is not being sent the line is kept in the 1-state
raquoThe initiation of a character transmission is detected from the start bit which is
always ldquo0rdquo
raquoThe character bits always follow the start bit
raquo After the last bit of the character is transmitted a stop bit is detected when the line
returns to the 1-state for at least one bit time (stop bits 1 15 2)
Thank you
- Input-Output Organization
- Interface
- IO Bus and Interface Modules
- IO Bus versus Memory Bus
- Example of Io interface
- Asynchronous Data Transfer
- Asynchronous Data Transfer (2)
- Asynchronous Serial Transfer
- Asynchronous transmission rules no parity
- Slide 10
-
INTERFACE
A conversion of signal values may be required
raquo CPU(Electronics) HDD(Electromechanical and Electromagnet)
A synchronization mechanism may be needed
raquo The data transfer rate of peripherals is usually slower than the transfer rate of the CPU
Data codes and formats in peripherals differ from the word format in the CPU and Memory
The operating modes of peripherals are different from each other 4 modes
raquo Each peripherals must be controlled so as not to disturb the operation of other peripherals connected to the CPU
bull Special hardware components between the CPU and peripherals
bull Supervise and Synchronize all input and output transfers
IO BUS AND INTERFACE MODULES
IO BUS VERSUS MEMORY BUS
Computer buses can be used to communicate with memory and IO
1) Use two separate buses one for memory and the other for IO
bull IO Processor separate memory bus and IO bus
2) Use one common bus for both memory and IO but have separate control lines for each Isolated IO or IO Mapped IO
bull IN OUT IO Instruction
bull MOV or LD Memory readwrite Instruction
3) Use one common bus for memory and IO with common control lines Memory
Mapped IO
bull MOV or LD IO and Memory readwrite Instruction
4 IO port Data port A Data port B ControlStatusbull 8255 PIO ( port A B C ControlStatus )Address Decode bull CS RS1 RS0
Exam
ple
EXAMPLE OF IO INTERFACE
ASYNCHRONOUS DATA TRANSFER
Synchronous Data Transfer
bull All data transfers occur simultaneously during the occurrence of a clock pulse
bull Registers in the interface share a common clock with CPU registers
Asynchronous Data Transfer
bull Internal timing in each unit (CPU and Interface) is independent
bull Each unit uses its own private clock for internal registers
ASYNCHRONOUS DATA TRANSFER
Strobe Control signal to indicate the time at which data is being transmitted
1) Source-initiated strobe 2) Destination-initiated strobe
Destin
atio
n-in
itiate
d stro
be
Sourc
e-i
nit
iate
d s
trobe
ASYNCHRONOUS SERIAL TRANSFER
Synchronous transmission
raquo The two unit share a common clock frequency
raquo Bits are transmitted continuously at the rate dictated by the clock pulses
1048698 Asynchronous transmission
raquo Special bits are inserted at both ends of the character code
raquo Each character consists of three parts
1048698 1) start bit always ldquo0rdquo indicate the beginning of a character
1048698 2) character bits data
1048698 3) stop bit always ldquo1rdquo
ASYNCHRONOUS TRANSMISSION RULES NO PARITY
raquo When a character is not being sent the line is kept in the 1-state
raquoThe initiation of a character transmission is detected from the start bit which is
always ldquo0rdquo
raquoThe character bits always follow the start bit
raquo After the last bit of the character is transmitted a stop bit is detected when the line
returns to the 1-state for at least one bit time (stop bits 1 15 2)
Thank you
- Input-Output Organization
- Interface
- IO Bus and Interface Modules
- IO Bus versus Memory Bus
- Example of Io interface
- Asynchronous Data Transfer
- Asynchronous Data Transfer (2)
- Asynchronous Serial Transfer
- Asynchronous transmission rules no parity
- Slide 10
-
IO BUS AND INTERFACE MODULES
IO BUS VERSUS MEMORY BUS
Computer buses can be used to communicate with memory and IO
1) Use two separate buses one for memory and the other for IO
bull IO Processor separate memory bus and IO bus
2) Use one common bus for both memory and IO but have separate control lines for each Isolated IO or IO Mapped IO
bull IN OUT IO Instruction
bull MOV or LD Memory readwrite Instruction
3) Use one common bus for memory and IO with common control lines Memory
Mapped IO
bull MOV or LD IO and Memory readwrite Instruction
4 IO port Data port A Data port B ControlStatusbull 8255 PIO ( port A B C ControlStatus )Address Decode bull CS RS1 RS0
Exam
ple
EXAMPLE OF IO INTERFACE
ASYNCHRONOUS DATA TRANSFER
Synchronous Data Transfer
bull All data transfers occur simultaneously during the occurrence of a clock pulse
bull Registers in the interface share a common clock with CPU registers
Asynchronous Data Transfer
bull Internal timing in each unit (CPU and Interface) is independent
bull Each unit uses its own private clock for internal registers
ASYNCHRONOUS DATA TRANSFER
Strobe Control signal to indicate the time at which data is being transmitted
1) Source-initiated strobe 2) Destination-initiated strobe
Destin
atio
n-in
itiate
d stro
be
Sourc
e-i
nit
iate
d s
trobe
ASYNCHRONOUS SERIAL TRANSFER
Synchronous transmission
raquo The two unit share a common clock frequency
raquo Bits are transmitted continuously at the rate dictated by the clock pulses
1048698 Asynchronous transmission
raquo Special bits are inserted at both ends of the character code
raquo Each character consists of three parts
1048698 1) start bit always ldquo0rdquo indicate the beginning of a character
1048698 2) character bits data
1048698 3) stop bit always ldquo1rdquo
ASYNCHRONOUS TRANSMISSION RULES NO PARITY
raquo When a character is not being sent the line is kept in the 1-state
raquoThe initiation of a character transmission is detected from the start bit which is
always ldquo0rdquo
raquoThe character bits always follow the start bit
raquo After the last bit of the character is transmitted a stop bit is detected when the line
returns to the 1-state for at least one bit time (stop bits 1 15 2)
Thank you
- Input-Output Organization
- Interface
- IO Bus and Interface Modules
- IO Bus versus Memory Bus
- Example of Io interface
- Asynchronous Data Transfer
- Asynchronous Data Transfer (2)
- Asynchronous Serial Transfer
- Asynchronous transmission rules no parity
- Slide 10
-
IO BUS VERSUS MEMORY BUS
Computer buses can be used to communicate with memory and IO
1) Use two separate buses one for memory and the other for IO
bull IO Processor separate memory bus and IO bus
2) Use one common bus for both memory and IO but have separate control lines for each Isolated IO or IO Mapped IO
bull IN OUT IO Instruction
bull MOV or LD Memory readwrite Instruction
3) Use one common bus for memory and IO with common control lines Memory
Mapped IO
bull MOV or LD IO and Memory readwrite Instruction
4 IO port Data port A Data port B ControlStatusbull 8255 PIO ( port A B C ControlStatus )Address Decode bull CS RS1 RS0
Exam
ple
EXAMPLE OF IO INTERFACE
ASYNCHRONOUS DATA TRANSFER
Synchronous Data Transfer
bull All data transfers occur simultaneously during the occurrence of a clock pulse
bull Registers in the interface share a common clock with CPU registers
Asynchronous Data Transfer
bull Internal timing in each unit (CPU and Interface) is independent
bull Each unit uses its own private clock for internal registers
ASYNCHRONOUS DATA TRANSFER
Strobe Control signal to indicate the time at which data is being transmitted
1) Source-initiated strobe 2) Destination-initiated strobe
Destin
atio
n-in
itiate
d stro
be
Sourc
e-i
nit
iate
d s
trobe
ASYNCHRONOUS SERIAL TRANSFER
Synchronous transmission
raquo The two unit share a common clock frequency
raquo Bits are transmitted continuously at the rate dictated by the clock pulses
1048698 Asynchronous transmission
raquo Special bits are inserted at both ends of the character code
raquo Each character consists of three parts
1048698 1) start bit always ldquo0rdquo indicate the beginning of a character
1048698 2) character bits data
1048698 3) stop bit always ldquo1rdquo
ASYNCHRONOUS TRANSMISSION RULES NO PARITY
raquo When a character is not being sent the line is kept in the 1-state
raquoThe initiation of a character transmission is detected from the start bit which is
always ldquo0rdquo
raquoThe character bits always follow the start bit
raquo After the last bit of the character is transmitted a stop bit is detected when the line
returns to the 1-state for at least one bit time (stop bits 1 15 2)
Thank you
- Input-Output Organization
- Interface
- IO Bus and Interface Modules
- IO Bus versus Memory Bus
- Example of Io interface
- Asynchronous Data Transfer
- Asynchronous Data Transfer (2)
- Asynchronous Serial Transfer
- Asynchronous transmission rules no parity
- Slide 10
-
EXAMPLE OF IO INTERFACE
ASYNCHRONOUS DATA TRANSFER
Synchronous Data Transfer
bull All data transfers occur simultaneously during the occurrence of a clock pulse
bull Registers in the interface share a common clock with CPU registers
Asynchronous Data Transfer
bull Internal timing in each unit (CPU and Interface) is independent
bull Each unit uses its own private clock for internal registers
ASYNCHRONOUS DATA TRANSFER
Strobe Control signal to indicate the time at which data is being transmitted
1) Source-initiated strobe 2) Destination-initiated strobe
Destin
atio
n-in
itiate
d stro
be
Sourc
e-i
nit
iate
d s
trobe
ASYNCHRONOUS SERIAL TRANSFER
Synchronous transmission
raquo The two unit share a common clock frequency
raquo Bits are transmitted continuously at the rate dictated by the clock pulses
1048698 Asynchronous transmission
raquo Special bits are inserted at both ends of the character code
raquo Each character consists of three parts
1048698 1) start bit always ldquo0rdquo indicate the beginning of a character
1048698 2) character bits data
1048698 3) stop bit always ldquo1rdquo
ASYNCHRONOUS TRANSMISSION RULES NO PARITY
raquo When a character is not being sent the line is kept in the 1-state
raquoThe initiation of a character transmission is detected from the start bit which is
always ldquo0rdquo
raquoThe character bits always follow the start bit
raquo After the last bit of the character is transmitted a stop bit is detected when the line
returns to the 1-state for at least one bit time (stop bits 1 15 2)
Thank you
- Input-Output Organization
- Interface
- IO Bus and Interface Modules
- IO Bus versus Memory Bus
- Example of Io interface
- Asynchronous Data Transfer
- Asynchronous Data Transfer (2)
- Asynchronous Serial Transfer
- Asynchronous transmission rules no parity
- Slide 10
-
ASYNCHRONOUS DATA TRANSFER
Synchronous Data Transfer
bull All data transfers occur simultaneously during the occurrence of a clock pulse
bull Registers in the interface share a common clock with CPU registers
Asynchronous Data Transfer
bull Internal timing in each unit (CPU and Interface) is independent
bull Each unit uses its own private clock for internal registers
ASYNCHRONOUS DATA TRANSFER
Strobe Control signal to indicate the time at which data is being transmitted
1) Source-initiated strobe 2) Destination-initiated strobe
Destin
atio
n-in
itiate
d stro
be
Sourc
e-i
nit
iate
d s
trobe
ASYNCHRONOUS SERIAL TRANSFER
Synchronous transmission
raquo The two unit share a common clock frequency
raquo Bits are transmitted continuously at the rate dictated by the clock pulses
1048698 Asynchronous transmission
raquo Special bits are inserted at both ends of the character code
raquo Each character consists of three parts
1048698 1) start bit always ldquo0rdquo indicate the beginning of a character
1048698 2) character bits data
1048698 3) stop bit always ldquo1rdquo
ASYNCHRONOUS TRANSMISSION RULES NO PARITY
raquo When a character is not being sent the line is kept in the 1-state
raquoThe initiation of a character transmission is detected from the start bit which is
always ldquo0rdquo
raquoThe character bits always follow the start bit
raquo After the last bit of the character is transmitted a stop bit is detected when the line
returns to the 1-state for at least one bit time (stop bits 1 15 2)
Thank you
- Input-Output Organization
- Interface
- IO Bus and Interface Modules
- IO Bus versus Memory Bus
- Example of Io interface
- Asynchronous Data Transfer
- Asynchronous Data Transfer (2)
- Asynchronous Serial Transfer
- Asynchronous transmission rules no parity
- Slide 10
-
ASYNCHRONOUS DATA TRANSFER
Strobe Control signal to indicate the time at which data is being transmitted
1) Source-initiated strobe 2) Destination-initiated strobe
Destin
atio
n-in
itiate
d stro
be
Sourc
e-i
nit
iate
d s
trobe
ASYNCHRONOUS SERIAL TRANSFER
Synchronous transmission
raquo The two unit share a common clock frequency
raquo Bits are transmitted continuously at the rate dictated by the clock pulses
1048698 Asynchronous transmission
raquo Special bits are inserted at both ends of the character code
raquo Each character consists of three parts
1048698 1) start bit always ldquo0rdquo indicate the beginning of a character
1048698 2) character bits data
1048698 3) stop bit always ldquo1rdquo
ASYNCHRONOUS TRANSMISSION RULES NO PARITY
raquo When a character is not being sent the line is kept in the 1-state
raquoThe initiation of a character transmission is detected from the start bit which is
always ldquo0rdquo
raquoThe character bits always follow the start bit
raquo After the last bit of the character is transmitted a stop bit is detected when the line
returns to the 1-state for at least one bit time (stop bits 1 15 2)
Thank you
- Input-Output Organization
- Interface
- IO Bus and Interface Modules
- IO Bus versus Memory Bus
- Example of Io interface
- Asynchronous Data Transfer
- Asynchronous Data Transfer (2)
- Asynchronous Serial Transfer
- Asynchronous transmission rules no parity
- Slide 10
-
ASYNCHRONOUS SERIAL TRANSFER
Synchronous transmission
raquo The two unit share a common clock frequency
raquo Bits are transmitted continuously at the rate dictated by the clock pulses
1048698 Asynchronous transmission
raquo Special bits are inserted at both ends of the character code
raquo Each character consists of three parts
1048698 1) start bit always ldquo0rdquo indicate the beginning of a character
1048698 2) character bits data
1048698 3) stop bit always ldquo1rdquo
ASYNCHRONOUS TRANSMISSION RULES NO PARITY
raquo When a character is not being sent the line is kept in the 1-state
raquoThe initiation of a character transmission is detected from the start bit which is
always ldquo0rdquo
raquoThe character bits always follow the start bit
raquo After the last bit of the character is transmitted a stop bit is detected when the line
returns to the 1-state for at least one bit time (stop bits 1 15 2)
Thank you
- Input-Output Organization
- Interface
- IO Bus and Interface Modules
- IO Bus versus Memory Bus
- Example of Io interface
- Asynchronous Data Transfer
- Asynchronous Data Transfer (2)
- Asynchronous Serial Transfer
- Asynchronous transmission rules no parity
- Slide 10
-
ASYNCHRONOUS TRANSMISSION RULES NO PARITY
raquo When a character is not being sent the line is kept in the 1-state
raquoThe initiation of a character transmission is detected from the start bit which is
always ldquo0rdquo
raquoThe character bits always follow the start bit
raquo After the last bit of the character is transmitted a stop bit is detected when the line
returns to the 1-state for at least one bit time (stop bits 1 15 2)
Thank you
- Input-Output Organization
- Interface
- IO Bus and Interface Modules
- IO Bus versus Memory Bus
- Example of Io interface
- Asynchronous Data Transfer
- Asynchronous Data Transfer (2)
- Asynchronous Serial Transfer
- Asynchronous transmission rules no parity
- Slide 10
-
Thank you
- Input-Output Organization
- Interface
- IO Bus and Interface Modules
- IO Bus versus Memory Bus
- Example of Io interface
- Asynchronous Data Transfer
- Asynchronous Data Transfer (2)
- Asynchronous Serial Transfer
- Asynchronous transmission rules no parity
- Slide 10
-