implementation fully depleted a-channel soi nmosfet and software problems. my appreciation extends...

Implementation of a Fully Depleted A-Channel

SOI NMOSFET

A thesis submitted in conformi@ with the requirements for the degree of Master of Applied Science

Edward S. Rogers Sr. Department of Electrical and Computer Engineering

University of Toronto 2000

O Copyright by Zhixian Jiao 2000

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Implementation of a Fuily Depleted A-charnel SOI NMOSFET

Master of Applied Science, 2000 Zhixian Jiao

Edward S. Rogers Sr. Department of Electrical and Computer Engineering University of Toronto

Silicon-On-lnsulator (SOI) CMOS technology is a potential technology for future

VLSI system implementations. Owing to complete dielectric isolation, SOI technology

offers superior MOS devices with suppressed CMOS latch-up, higher packing density and

higher speed.

SOI hlly depleted ultrathin-film MOSFET structures offer many advantages including

ided subthreshold slope, reduced floating body effects, supenor transconductance and

superior current drive. However, stringent control of silicon film uniformity is needed.

In this thesis, a fully depleted A-channel SOI NMOSFET strucnire is proposed. The

key feanire is the triangle-shaped channel implemented in a thick SOI film using anisotropic

etching technique of silicon. The gate electrode exhibits an irnproved control over the

channel potential and entire depletion of the channel is obtained. The proposed structure

eliminates floating body effects and works in fully depleted regime with bulk effective

mobility in the channel region.

A CMOS-compatible process for the fabrication of the proposed A-channel SOI

NMOSFET was developed. The device was successfully manufacnired and electrically

characterized. The A-channel SOI NMOSFET exhibited a threshold voltage of 370 mV and

an excellent subthreshold slope of 67 mV1dec. No kink was observed in the output

charactenstics. Enhanced transconductance and current driving capability were observed

due to buk mobiiity in the channel. FIoating body effects were substantially suppressed and

îüliy depleted SOI MOS performance was achieved.

In memory of my father.

Acknowledgments

I would like to express my sincere gratitude to Professor C.A.T. Salama for his

insightful guidance and invaluable assistance throughout the course of this work.

1 am indebted to Dana Deem and Richard Barber for technical assistance and English

improvement. Without their help and fnendship, 1 do not think that my work would have

been completed. Thanks to Jaro Pristupa for his assistance in dealing with cornputer

hardware and software problems.

My appreciation extends to a11 the staff and students in Microelectronic Research

Laboratory, especially, Wei Yang, Shuo Chen, Yucai Zhang, Farhang Vessai, Song Ye,

Hongfei Lu. Wei An, Heng Jin, Anthoula Kampouris, Jeewika Ranaweera, Mehrdad

Ramezani, Dusan Suvakovic, Dod Chettiar and John 2. Ren for their help and fnendship.

1 would like to take this opportunity to express my sincere gratitude to my husband

Xijun and my son Zhaoda for their patience, support and love. 1 would like to thank my

Mom and rny brother who have been a constant source of support and encouragement to

endure through it ail. Thanks to Qingming Zeng and Lizhang Hou for their help and

friends hip.

Financial support provided by Micronet, Gennum Corporation, Mitel and Norte1

Networks is greatly appreciated.

Table of Contents

Page

CRAPTER 1 Introduction ............................................................................................ ...l 1.1 SOI CMOS Technology and its Advantages over Conventional Si CMOS

...................................................................................... Technology ................... ...... 2

..................................... 1.1.1 Challenges in Conventional Si CMOS Technology -2

....................................................... 1.1.2 Development of SOI CMOS Technology 4

1.1.3 Advantages of SOI CMOS Technology over Conventional Si CMOS

.............................................................................................................. Technology 5

............................................................... 1.2 Design Issues in SOI CMOS Technology 8

................ 1.2.1 Distinction between Partially and Fully Depleted SOI MOSFETs 8

....................... 1.2.2 Floating Body Effects in Partially Depleted SOI MOSFETs 10

............................................ 1.2.3 Challenges in Fully Depleted SOI Technology I l

............................................................................ 1.3 Novel Fully Depleted Structures 13

.................................................................. 1.4 Objectives and Outlines of the Thesis 14

.................................................................................................................. References -16

CEIAPTER 2 Fully Depleted A-Channel SOI NMOSFET Design and Simulation .... 18

........................................................................................................... 2.1 Introduction 1 8

.................................................................................................... 2.2 Device S tmcture -19

.................................................................................................... 2.3 Process Structure 20

.............................................................................. 2.4 Process Design Considerations 22

.......................................................................................................... 2.5 Process Flow 25

......................................................................................... . 2.6 Process S imdation ,.. 1

2.7 Device Simulation Setup ....................................................................................... 33

.......................................................................... 2.8 Simulated Device Characteristics 36

......................................... 2.9 Enhanced Conduction in A-ChmneI SOI NMOSFETs 40

2.10 Summary .............................................................................................................. 42

..................................................................................................................... Reference 43

3.1 Introduction ............................................................................................................ 45

..................................................................... 3.2 Development of the Etching Process 45

....................................................................... .................... 3.3 Test Pattern Design .. 48

3.4 Test Chip Implementation ...................................................................................... 50

........................................................................................ 3.5 Process Characterization 51

......................................................................................... 3.6 Device Characterization 52

3.7 Summary ............................................................................................................. 59

..................................................................................................................... Reference 60

CHAPTER 4 Conclusion ...........m...m.... ................................................... 61

APPENDIX A Mask Design Rule .......................... ......... ...... 6

List of Figures Page

Figure 1.1 : Parasitic Capacitances between the Junction and the Substrate. and between

the Junction and the Channel Stop in a Bulk Device ........................................ 3

Figure 1.2: (a) Parasitic B ipolar Transistors in a CMOS Structure

(b) Equivalent SCR Structure ............................................................................ 3

Figure 1.3. Cross Section of Bulk CMOS (a) and SOI CMOS (b) Inverters ....................... 5

Figure 1.4: Parasitic DrainiSource-to-substrate Capacitances in Buik (a) and SOI (bj

MOSFETs .......................................................................................................... 6

Figure 1.5: (a) Cross Section of an SOI MOSFET

(b) Equivalent Gate-to-substrate Capacitance Network ................................. 7

................................. Figure 1.6. Layout of Bulk CMOS (a) and SOI CMOS (b) Inverten 8

Figure 1.7: Cross Section of a Partially Depleted SOI (a) and a Fully Depleted SOI (b)

MOSFETs .................... .,,, ................................................................................. 9

Figure 1.8: Roating Body Effects in SOI MOSFETs: (a) Kink Effect;

......................................................................... (b) Single Transistor Latchup IO

Figure 1.9: Threshold Voltage Variation versus SOI Film Thickness in FD SOI

..................................................................................................... MOSFETs 1 2

Figure 1.10. Cross Section of DELTA Structure ............................................................ 14

..................... Figure 2.1. Cross Section of the FulIy Depleted A-channel SOI MOSFET 20

Figure 2.2: Fully Depleted A-channel SOI MOSFET (a) and Cross Section along

Line AA' (b) .............................................................................................. 2 1

Figure 2.3: Fabrication of the Triangular Silicon Islands Located on the Buried Oxide .. 23

.................................. Figure 2.4. Process Flow of Fabricating A-channel SOI MOSFET 28

Figure 2.5: A-channel SOI MOSFET: Cross Section (a) and TSUPREM4 Structure (b)

......................................................................................................................... 32

Figure 2.6: Doping Profile in the Channel Region (a) and in the Sourceldrain Region @)

......................................................................................................................... 32

Figure 2.7. Device Structure in DAVINCI Simulation .................................................... 34

................................ Figure 2.8. Right-angled Triangle Approximation of the A channel 35

............................................................. Figure 2.9. Definition of the Triangle Channel 35

Figure 2.10: Transfer (a) and Subthreshold (b) Characteristics for a A-channel SOI

NMOSFET ................................................................................................... 37

Figure 2.1 1: Transfer (a) and Output Characteristics for a Conventional SOI NMOSFET

....................................................................................................................... 37

Figure 2.12: Threshold Voltage as a Function of Gate Length in the Conventional SOI

and A-channel SOI NMOSFETs ............................... ,., ............................... 38

Figure 2.13: Output Charactenstics of a Conventional SOI (a) and a A-channel SOI (b)

NMOSFET ................................................................................................... 39 ................................................ Fi-me 2.14. Breakdown Characteristics when V, - = O V 39

Figure 2.15: Gate Transfer (a) and Output Characteristics (b) of the A-channel SOI

NMOSFET Using the Concentration Dependent Mobility Mode1 ............... 41

Figure 3.1 : Cross Section of the Etched Trench nlustrating Relevant Dimensions ......... 46

Figure 3.2. SEM Micrographs of Cross Sections in the Silicon Etching Process (#1) ...... 47

Figure 3.3. SEM Micrographs of Cross Sections in the Silicon Etching Process (#2) ...... 48

Figure 3.4. Test Chip Layout ............................................................................................ 49

........................................................ Figure 3.5. Micrograph of the Fabricated Test Chip 50

Figure 3.6: Top Views of Fabricated SOI NMOSFETs (a) One Silicon Island

...................................................................... (b) 50 Silicon Islands in Parallel SI

Figure 3.7: SEM Micrograph of a Fabricated Ashannel (a) and a Conventional SOI

.................................................................................................... NMOSFET .52

Figure 3.8: Transfer (a) and Subthreshold (b) Characteristics for the Conventional SOI

..................................................................................................... NMOSFET 53

Figure 3.9: Transfer (a) and subthreshold (b) Characteristics for the A-channel SOI

NMOSFET ....................................... .., ........... -54

Figure 3.10: Transconductance g, as a Function of Vg, for the Conventional (a) and

the A-channel (b) SOI NMOSFETs .............................................................. 55

Figure 3.1 1 : Output Characteristics of the A-channel (a) and the Conventional (b)

SOI NMOSFETs ................... .... ................................................................... 56

Figure 3.12: Output Conductances gd, as a Function of Vp, for the Conventionai (a) and

................... the A-channel (b) SOI NMOSFETs when Vd, Approaches O V 58

Figure 3.13: Breakdown Characteristics of the A-channel and the Conventional SOI

NMOSFETs ........................... ......... ..............................................~............... 59

........................ ............................... Figure A . 1: illustration of Layout Design Rules .. *.63

List of Tables

Page

Table 1.1: Cornparison of Bulk MOS. Partially Depleted and Fully Depleted SOI

MOSFETs .............................................~........................................................ 1 3

............. .......................... Table 2.2. A-channe1 SOI NMOSET Process Parameters ....... 2 1

.......................................................... Table 2.2. A-channel SOI MOSFET Process Flow 29

..................................................................... Table 2 3: Parameters in Device Simulation 33

Table 2.4: Simulated Device Performance of a Conventional SOI NMOSFET and a

A-channel SOI NMOSFET ............................................................................... 40

................................................................ Table 3.l. Etch Rates for 10% TMAH at 75OC 47

.................................................................................. Table 3.2. Process Characterization 52

Table A . 1: Summary of Layout Design Rules .................................................................. 64

CHAPTER 1

Introduction

Silicon Complementary Metal-Oxide-Semiconductor (CMOS) is currently the ieading

technology for VLSI system implementation [I l . However, in CMOS, there exist inherent

parasitic couplings between devices, and between devices and the substrate. These give rise

to a range of problems in circuit applications, such as high parasitic capacitance, latchup

and short channel effects. With advancements in technology, the minimum feature length

has been shnnking continuously, resulting in these problems becoming increasingly

prominent. AIthough some special processing techniques and design methods have been

introduced to mitigate these problems, they cannot be eliminated completely.

The use of Silicon-On-Insulator (SOI) in CMOS technology to improve the

performance of devices, circuits and systems started in the 1970s. However, it was only

after recent breakthroughs in material fabrication, such as Separation by IMpiantation of

OXygen (SIMOX) [2] and Bond-and-Etch-back SOI (BESOI) [3], that SOI CMOS

technology has become more commonly available.

The benefits of SOI are obvious: simplified process, enhanced performance and

increased integration density. CMOS-based SOI microchips offer a 30% improvement in

speed and a 30% reduction in power consumption, a two-year performance gain over an

equivalent bulk CMOS technology can be achieved [4]. SOI CMOS is iikely to become the

dominant technology for the funire generations of VLSI systems.

Deparmient of Elecaical and Computer Engineering, University of Toronto 1

In this chapter, SOI CMOS technology and its advantages over conventional Si M O S

technology are described. The design issues in SOI are discussed in detail. Some advanced

SOI device structures are then introduced and the objectives of the thesis are outlined.

1.1 SOI CMOS Technology and its Advantages over

Conventional Si CMOS Technology

1.1.1 Challenges in Conventional Si CMOS Technology

In the development of Si CMOS technology, the miniatunzation of device dimensions

not only increases the packing density, but also greatly improves the performance of devices

and circuits [SI. In scaled devices, the power supply is scaled proportionally and the

physical dimensions are decreased, both honzontally and vertically, as well the subtnte

concentration is increased proportionally.

As the device feature size is scaled down, the fundamental limitations present in bulk

devices become more pronounced. One of these is the parasitic capacitance associated with

the diffused source/drain regions and the substrate. This capacitance limits the high-

frequency response of the device and depends on the doping in the substrate and becomes

more noticeable in modem CMOS devices where the substrate doping concentration is

high. As shown in Figure 1.1, for a conventionai CMOS structure, the drain (or source)-to-

substrate capacitance consists of two components which are of concem: (1) the depletion

capacitance Cd associated with the source/drain junctions, and (2) the capacitance Ci

between the junctions and the channet stop which is highly doped to prevent any inversion

under the field oxide.

Department of Electrical &d cchputer Engineering, University of Toronto 2

[ Substrate 1

Figure 1.1 Parasitic Capacitances between the Junction and the Subsuate, ana between the Junction and the Channel Stop in a Bulk Device

The second limitation of the CMOS stnicture is the inherent PNPN thyristor (SCR)

constituted by the parasitic bipolar transistors as illustrated in Figure 1.2. When the

horizontal dimensions are reduced, the gain of these transistors is enhanced, resulting in an

increased risk of tuming on the thyristor structure. thus causing latchup.

well Lateral pnp

vss (+)

?

Figure 1.2 (a) Parasitic Bipolar Transistors in a CMOS Structure (b) Equivaient SCR Structure

In scaled MOSFETs, short channel effects are a severe problem which originates from

the partiai loss of gate control over the channel region. The potential distribution in the

- -

Department of ~lectric&nd Computer ~ G n e e r i n ~ , University of Toronto 3

channel becomes two dimensional, restncted by both the gate voltage and the drain biasing.

This two dimensional potential results in a degradation of the subthreshold behavior. As

bulk CMOS quickly approaches the 0.1 pm regime, short channel effects become a

challenge for both device and circuit engineee.

In summary, fundamental limitations in scaied CMOS are driving the development of

new technologies, such as SOI CMOS which appears to be the most promising for VLSI

system realization.

1.1.2 Development of SOI CMOS Technology

SOI technology started when Silicon-On-Sapphire (SOS) wafers were produced by

heteroepitay [6]. In the 1970s, the SOS wafers became commercially available. In 1976, a

16-bit rnicroprocessor was reported [7] and two years later RCA implemented a 16k CMOS

SRAM [8]. However, because of lattice and thermal mismatches, the defect density in the

silicon film grown on the sapphire substrate remained quite high.

In the early 1980s, SOI material technology was used to synthesize an insulating layer

to separate the active semiconductor layer from the semiconductor substrate. Many

techniques to achieve this objective have been developed. These include Zone-Melting-

Recrystallization (ZMR) [9], Separation by IMpIantation of OXygen (SIMOX) [2], Full

Isolation by Porous Oxidized Silicon (FIPOS) [IO], Bond and Etch-back SOI (BESOI) (31,

and Srnart Cut [1 Il. SIMOX and BESOI are currently the leading technologies in SOI film

market and seem to be the ideal candidates for VLSI CMOS applications. The carrier

rnobilities and lifetimes in these layers are reported to be comparable to those in bulk silicon

materials [ 12- 141.

SOI wafer quality has greatiy irnproved over the past decade. SOI technology has been

used to implement high speed circuits, gate may, DRAMs, SRAMs and other VLSI circuits

Department of Electrical and Computer Engineering, University of Toronto 4

1.1.3 Advantages of SOI CMOS Technology over Conventional Si CMOS Technology

SOI CMOS technology offers many advantages over the conventional CMOS

technology, such as: dielectric isolation, simple process and layout, and irnrnunity from

short channel effects.

1. Dielectric isolation

In SOI, device islands are located on the buried oxide. They are electrically isolated

from each other, and from the underlying substrate as shown in Figure 1.3 (b). Cornpared

with the conventional CMOS (Figure 1.3 (a)), the SOI CMOS topology has no current path

between the active region and the substrate, which makes up the SCR structure in bulk

CMOS. Latchup just disappears in SOI technology.

d 1 pnp I

d

I n substrate 1

SOI

Figure 1.3 Cross Section of Bulk CMOS (a) and SOI CMOS (b) Inverters

Another superior feature of SOI devices obtained by dielectric isolation is illustrated in

Figure 1.4. Unlike bulk MOSFETs, the sourceldrain capacitance in SOI structure has only

one component: the parasitic capacitance Cd between the junction and the substrate. This

capacitance is significantly reduced, thus contributing to the speed enhancement of SOI

Deparûnent of EileacaÏand Cornputer Engineering, u&ersity of Toronto -

5

CMOS circuits and resulting in the power-delay product of SOI CMOS being rnuch srnaller

than that of bulk CMOS 1161. Furthemore, the junction to isolation capacitance Cj in the

SOI structure is completed eliminated.

Bulk SOI

Si Substratel

(b)

Figure 1.4 Parasitic DraidSource-to-Substrate Capaciiances in Bulk (a) and SOI (b) MOSFETs

In addition, due to the complete dielectric isolation, SOI devices possess nearly ided

subthreshold characteristics. The subthreshold slope in a SOI MOSFET can be expressed as

1171:

and al is an interface coupling coefficient

as illustrated in Figure 1.5, where CoXl and Cod are the fiont gate oxide capacitance and the

buried oxide capacitance respectively. Cil] and Cit2 are the top and bottom interface trap

capacitances respectively. Cs is the silicon film capacitance defined by Csi= / t s where

is the silicon film thickness and is the silicon dielectric constant

Department of Electrical and Cornputer Engineering, University of Toronto 6

Gate oxide

Figure 1.5 (a) Cross Section of an SOI MOSFET (b) Equivalent Gate-to-substrate Capacitance Network (Thin-film Fully-depleted SOI)

Usually, Cd « Csi, Co.d cc Cm,, and the interface trap capacitance Citl and Cit2 are

negligible, ihus ai « 1, resulting in a subthreshold dope S close to the theoretical lirnit

The improvement of the subthreshold characteristics enhances the speed performance

of an SOI device and reduces the standby power consumption. Further, compared with bulk

MOSFETs, the excellent value of the subthreshold swing in SOI devices allows smaller

values of threshold voltage without increasing the leakage current, making SOI technology

suitable for low-power low-voltage applications.

2. Processing and circuit design issues

SOI technology also provides benefits in processing and in layout design. In buik

CMOS, the isolation is realized by reverse-biased PN junctions. These junctions as well as

the P or N wells require extra layout space. On the other hand, in SOI, the devices are

dielectrically isolated from each other. The separation between individual devices is only

subject to the resolution of photolithography as displayed in Figure 1.6. Therefore, in

addition to a simplified process, higher packing density can be achieved.

Department of Electncal and Cornputer Engineering, University of Toronto 7

Buk SOI

kweU Gnd Pi"' vss (+)

Weil contac

1- type substrate YY In

Figure 1.6 Layout of Bulk CMOS (a) and SOI CMOS (b) Inverten

3. Short channel effects

SOI devices are also immune from the short channel effects which originate from the

charge sharing between the gate and the source/drain junctions. In a conventional small-

geometry MOS device, the depletion regions induced by the source/drain junctions become

relatively significant and impede the gate control over the channel space-charge region. In

SOI, however, the extension of the source/dr;iin depletion region is substantially restrained

by the buried oxide. The charge sharing is greatly decreased, ensuring an enhanced gate

control over the channel potential. The short channel effects are significantly suppressed in

SOI technology.

1.2 Design Issues in SOI CMOS Technology

1.2.1 Distinction between Partially and Fully Depleted SOI MOSFETs

Depending on the silicon film thickness, two kinds of MOSFETs cm be implemented

in SOI technology: Partially Depleted (PD) and Fully Depleted (FD) devices. With the same

Department of Electncai and Computer Engineering, University of Toronto 8

doping concentration, sourceldrain capacitance and layout density, FD and PD MOSFETs

exhibit considerable operating differences.

The Partially Depleted (PD) device is a thick film device. The thickness of silicon film

is larger than the maximum gate depletion width. There is no coupling between the front

gate and the buned oxide. In the middle of the active region, there is a piece of neutrai

region referred as "body". This is shown in Figure 1.7 (a). Floating body effects originate

from this region, which requires special considerations in device manufacturing and circuit

applications.

Gate f

Gate P

b Back gate

b Back gate

Figure 1.7 Cross Section of a Partially-depleted SOI (a) and a Fully-depleted SOI (b) MOSFETs

If the silicon film is thinner than the maximum depletion region, the silicon film is

completely depleted at threshold, irrespective of the biasing applied to the back gate, a s

shown in Figure 1.7 (b). FD SOI MOSFETs have demonstrated impressive characteristics,

such as high transconductance, no kink effect, excellent subthreshold behavior and

improved speed performance.


1.2.2 FIoating Body Effects in Partially Depleted SOI MOSFETs

The major parasitic effects in partially depleted SOI devices are floating body effects. if

there is no contact to the neutral region in the device, the body is then floating, resulting in

the kink effect and the single transistor latchup.

The !ch!! effect involves an abrupt increase in the drain current in the saturation reeion. - as displayed in Figure 1.8 (a). When the drain voltage is high enough, channel carriers can

acquire sufficient energy in the high electric field zone near the drain and create electron-

hole pain via impact ionization. The electrons are collected by the drain, while the holes

migrate towards the low-potential region -- the floating body. Because of the complete

isolation between the silicon film and the substrate, these holes cannot be removed rapidly.

They pile up in the body, gradually increasing the body potential, which in tum lowers the

ihreshold voltage and results in the increase in drain current [Ml.

V~ impact ionization ?

Figure 1.8 Floating Body Effects in SOI MOSFETs: (a) Kink Effect; @) Single Transistor Latchup. Ich is the channel cumnt, IB and PIB are the base and collecter current, respective1 y.

--

Department of Electncal and Computer Engineering, University of Toronto 10

The single transistor latchup is caused by the parasitic bipolar junction transistor (BJT)

parallel to the MOS structure as illustrated in Figure 1.8 (b). With the accumulation of holes

in the floating body, the body potential rises causing the body-source junction (emitter

junction) to tum on and the lateral bipolar transistor to become active. More minority

cmiers are injected €rom the source (emitter) into the body (base) and the base current IB is

arnplified [18-191. The terminal voltages lose control of the current and the current

increases dramatically. Latchup occurs. If there is no protection, the device will be

destroyed.

1.2.3 Challenges in Fully Depleted SOI Technology

In fully depleted SOI devices, the silicon film thickness is much smaller than the

depletion width. During the operation of the device, the channel potential is tightly

controlled by the gate. The Si film remains depleted.

Due to the entire depletion of the silicon film, the body potential remains unchanged;

therefore, the fioating body effects are substantiaily suppressed. Moreover, as discussed in

Section 1.1.3, fully depleted devices exhibits quasi-ideal subthreshold characteristic. The

steeper subthreshold dope permits a lower threshold voltage (V*) for the sarne off current,

making it possible to use the device at a lower voltage. The typical subthreshold slope is

less than 70 mV/dec. Because of the excellent control of the channel region by the gate,

fully depleted SOI devices have a better imrnunity to short channel effects than PD devices.

Furthemore, higher c h e r mobility and higher transconductance have been observed in

fully depleted devices, making them very attractive for high speed applications.

However, in fully depleted SOI technology, challenges exist in uniformity control and

parasitic reduction. The control of the ultra-thin film process and the uniforrnity of the

threshold voltage Vh in fabricated devices is difficult. As shown in Figure 1.9, when the

Department of Elecûical and Computer Engineering, University of Toronto

SOI film gets thinner, a minor variation of the thickness can make a significant shift of Vm.

Hence, rigid control of the film uniformity in the ultra-thin-film manufacture is necessary.

-0.11 O 50 100 150 100 30 300 350

SOI Thin Film Thickness (nm)

Figure 1.9 Threshold Voltage Variation versus SOI Film Thickness in FD SOI MOSFETs

Another severe problem in FD SOI technology is the parasitic source/drain resistance

associated with the ultra-thin film. This high series resistance can easily offset the

advantages obtained from using ultra-thin SOI materials and reduce the circuit speed. In

order to solve the problem, novel techniques have been developed, such as thin salicide

1201, recessed-channel structure [21] and Ge prearnorphization salicide [22]. These

techniques increase the complexity of the process and have limited applications.

In summary, the partially and fully depleted SOI technologies discussed above have

strengths and weaknesses. Their properties are sumrnarized in Table 1.1. The fully depleted

devices have excellent performance, while stringent control of the process is dernanded.

The PD devices have poorer performance, but they exhibit less sensitivity to the thin film

thickness resulting in more controllability and more unifomiity in the process.

~ e ~ a r & e n t of Electrical and Cornputer Engineering, University of Toronto 12

Table 1 .1 Comparison of Bulk MOS, Partially Depleted and FuIly Depleted SOI MOSFETS*

Electrical Properties

Carrier Mobility

Transconductmce

S hort-channel Effect

S / D Capacitance

Bulk MOSFET

S/D Resistance

SubthreshoId Slope

Vh Sensitivity on Film Thickness tsi

* The bulk device is used as a reference: "0" means similar, "+" means better and "-" means worse.

I

O

O

O

Kink Effect

Hot Carrier

Pamitic Bipolar

1.3 Novel F d y Depleted Structures

O

Partiaiiy Depleted SOI

O

O

O

Compared with partially depleted SOI MOSFETs, fully depleted SOI devices possess

superior characteristics. However, the rigid requirement for the manufacture impedes its

application. In order to hamess the full potentid of FD SOI technology, innovative

Fuily Depleted SOI

O

O

+

O

O

O

structures have been proposed to achieve fully depleted device

thick SOI nIms (> 100 nm). One such structure is the DEpleted

(DELTA) (23-251.

I I I O

i-

+

+

O

O

O

performance on relatively

Lean-charnel TRAnsistor

+

-

+

-

O / +

-

Depariment of Electrical and Cornputer Engineering, University of Toronto 13

+

+

+

DELTA (DEpleted Lean-channel TRAnsistor) is implemented using the conventional

CMOS process [25]. The cross section of the device is shown in Figure 1.10. A very nmow

(0.15 pm) silicon island is anisotropicaily etched on the bulk-Si wafer. Subsequent LOCOS-

like oxidation proceeds undemeath the island and forms the SOI structure. The gate

electrode surrounds both sides of the channel. providing an excellent control over the

channel potential. The DEpleted Lean-channel TRAsistor exhibits attractive fully depleted

device behavion including: absence of fioating body effects, quasi-ided subrhreshold

characteristics and enhanced transconductance. However, it is obvious that advanced fine-

line photolithography is required to pattern the ultra-narrow device island, which rnay not

be universaily available and may impact the cost of manufacturing.

Cumnt, direction

Figure 1.10 Cross Section of DELTA Structure

1.4 Objectives and Outline of the Thesis

The objective of this thesis is to implement a fully depleted A-channel SOI NMOSFET.

This device effectively reduces the floating body effects in the thick-film SOI technology,

and fidiy depleted performance is achieved.

~ e ~ a r t m e n t of Electrical and Computer Engineering, University of Toronto 14

The new SOI NMOSFET structure proposed in this thesis involves creating the

triangle-shaped silicon island (A-channel) located on the buried oxide using the anisotropic

etching technique. The gate electrode envelops the two sides of the silicon island, thus,

providing good control over the channel potential. The complete depletion of the device

region is obtained.

The proposed process is fully compatible with the conventional Si CMOS process. It

provides a practical solution to minimize parasitic effects in SOI technology. The device is

designed to work in fully depleted mode, with a threshold voltage of 300 mV, a

subthreshold swing of Iess than 70 mV/decade and no kinks in the output characteristics.

Chapter 2 covers the design of the device. The device structure and the fabrication

issues are discussed in detail. The process parameters are optirnized using a two-

dimensional process sirnulator. A three dimensional device simulaton is used to evaluate

device performance.

Chapter 3 describes the fabrication and characterization of the proposed device in

detail. The cntical process steps are discussed and verified. The fabricated device is tested

and the performance is fully investigated.

Finally, conclusions are drawn, and suggestions for further work are discussed in

Chapter 4.

Department of ~ l e c t r i c i and &mputer Engineering, University of Toronto 15

References

Y. Taur and T. H. Ning, Fundamentais of Modern VLSI Devices, Cambridge University Press, Cambridge, 1998.

K. Izurni, M. Doken and H. Ariyoshi, "CMOS Devices Fabricated on Buned SiOz Lay- ers formed by Oxygen Implantation into Silicon," Elecrronics Letter, vol. 14, pp. 593- 594, 1978.

M. P. Maszara, "SOI Material by Wafer Bonding: an Overview," SOS/SOI Technology Workîhop Proceeding, pp. 18- 19, 199 1.

IBM News, "Laying the Foundation for more Powefil Chips," East Fishkill, N. Y., Aug.3, 1998.

M. Bohr, "MOS Transistors: Scaling and Performance Trends" Semiconductor Interna- tional, vol. 18, pp. 75-78, 1995.

S. Cnstoloveanu and S. S. Li. Electrical Characterizarion of Silicon-On-Insulator Marerials and Devices, Kluwer Academic Pubiisher, Norwell, USA. 1995.

B. E. Forbes, "Silicon-on-Sapphire Technology Produces High-speed Single-chip Pro- cessor," Hewlett-Packard Journal, pp.2, April 1977.

A. G. F. Dingwall, R. G. Stewart, B. C. Leung and R. E. Stricker, "High-density, Bur- ied-contact CMOSISOS Static RAM's," Intemarional Electron Device Meeting (IEDM) Digest, pp. 193- 196, 1978.

B. Y. Tsaur, "Zone-Melting-RecrystaIIization Silicon-on-Insulator Technology," IEEE Circuits and Devices Magazine, vo 1.3, pp. 1 2- 16, 1 987.

(101 S. S. Tsao, "Porous Silicon Techniques for SOI Structure," IEEE Circuits and Devices Magazine, pp. 3-7, November 1987.

[Il] M. Bruel, B. Aspar, B. Charlet, C. Maleville, T. Poumeyrol, A. Soubie, A. J. Auberton- Herve, J. M. Lamure, T. Barge, F. Metrai, S. Trucchi, "Smart Cut: A Promising New SOI Material Technology," International Symposium on SOI Technology and Devices Proceedings, pp. 178- 179, 1995.

[12]S. Cnstoloveanu, S. Gardner, C. Jaussaud, J. Margail, A. J. Auberton-Herve and M. Bruel, "Silicon on hsulator Material Formed by Oxygen Implantation and High-temperature Annealing: Carrier Transport, Oxygen Activity, and Interface Properties," Journal of Applied Physics, vol. 62, pp. 2793-2798, 1987.

[13] L. J. Spangler and K. D. Wise, "A Technology for High-performance Singer-crystal Sil- icon-on-insulator Transistors,'' IEEE Electron Device Letters, vol. 8, pp. 137-139, 1987.

- -- - - -


[14] J. B. Lasky, "Wafer Bonding for Silicon-on-insulator Technologies," Applied Physics Ltters, vol. 48, pp. 78- 80, 1986.

[15] J. B. Kuo and K. W. Su, CMOS VLTI Engineering: Silicon-on-lnsulator (SOI), Kluwer Academic hblisher, Norwell, USA, 1998.

[16] A. J. Auberton-Herve, "SIMOX-SOI Technologies for High Speed and Radiation Hard Technologies: Status and Trends in VLSI and ULSI Applications," International Sym- posium on SOI TechnoZogy and Devices Pmceedings, pp. 455478, 1990.

[17]B. Mazhari, S. Cristoloveanu, D. E. Ioannou and A. L. Caviglia, "Properties of Ultra- thin Wafer-bonded Silicon on Insulator MOSFETs," IEEE Trans. Electron Devices, vol. 38, pp. 1289-1295, 199 1.

[18] H. K. Yu, J. S. Lyu, S. W. Kang, C. K. Kim, "A Physical Mode1 of Roating Body Thin Film Silicon-on-Insulator NMOSFET with Parasitic Bipolar Transistor," IEEE Trans. on Electron Devices. vol. 4 1, pp. 726-733, 1994.

[19] J. Y Choi, J. G. Fossum, b'Analysis and Control of Floating-body Bipolar Effects in Fully Dep leted Submicrometer SOI MOSFETs," IEEE Trans. on Electmn Devices, vol. 38, pp. 1384-1391, 1991.

[20] H. 1. Liu, J. A. Burns, C. L. Keast and P. W. Wyatt, "Thin Saiicide Development for Fully-depleted SOI CMOS Technology," IEEEE Trans. on Electron Devices, vol. 45, no. 5, pp. 1099-1 104, 1998.

[21]M. Chan, F. Assaderaghi, S. A. Parke, C. Hu and P. K. Ko, "Recessedchannel Struc- ture for Fabricating Ultrathin SOI MOSFET with Low Series Resistance," IEEE Elec- fron Device Letiers, vol. 15, pp. 22-24, 1994.

[22]T. C. Hsiao, P. Liu and J. C. S. Woo, "An Adiranced Ge Prearnorphization Salicide Technology for Ultra-thin-film SOI CMOS Devices," IEEE Electron Device Leuers, vol. 18, pp. 309-3 1 1, 1997.

[23] T. Tanaka, H. Horie, S. Ando and S. Hijiya, "Analysis of p+ Poly Si Double-gate Thin- film SOI MOSFETs,' International EIecrron Device Meeting (IEDM) Digest, pp. 683- 686, 1991.

[24] R. P. Zingg, B. Hofflinger and G. W. Neudeck, "Dual-gate SOI CMOS Technology by Local Overgrowîh (LOG),'' IEEE SOS/SûI Workshop Pmceedings, pp. 134- 135,1989.

(251 D. Hisamoto, T. Kaga, Y. Kawamoto and E. Takeda, "A Fully Depleted Lean-channel Transistor (DELTA) - A Novel Vertical Ultra Thin SOI MOSFETTT' International Elec- tron Device Meeting (IEDM) Digest, pp. 833-836, 1989.


CHAPTER 2

Fully Depleted A-Channel SOI NMOSFET

Process Design and Device Simulation

2.1 Introduction

Fully Depleted (FD) SOI CMOS is a promising technology for VLSI applications.

Compared with Partially Depleted (PD) SOI devices, FD devices possess many attractive

features including improved subthreshold dope, suppression of floating body effects and

enhanced transconductance. However, the threshold voltage is sensitive to the thin film

thickness. In order to mitigate the problem, a hilly depleted A-channel SOI MOSFET is

proposed and developed in this thesis.

The structure of the fully depleted A-channel SOI NMOSFET is presented in this

chapter. The key feature is the criangle-shaped channel implemented in a normally thick

SOI film using anisotropic etching technique of silicon. The gate electrode surrounds both

sides of the triangular structure, providing an effective control over the channel potential.

During the operation of the device, the channel rernains depleted. The floating body effects

present in a thick-film SOI MOSFET are substantially suppressed, and fully depleted ultra-

thin SOI behavior is achieved.

- -

Department of Electrical and cornput& Engineering, University of Toronto 18

This chapter is organized as follows. First, the A-channel SOI device structure is

descnbed. Then the fabrication process is discussed in detail, including process design

issues, process fiow and simulation. The device is evduated, and cornparisons between the

conventional SOI MOSFET and the proposed structure are presented.

2.2 Device Structure

The excellent performance of ultrathin Fully Depleted (FD) SOI devices originates

from the complete depletion induced by the gate potential, i.e., elimination of the neutral

region in the channel. Generally, the gate-induced depletion width is in the order of 100 nm.

If the film, where the potential distribution is controlled by the gate, is Iess than 100 nm

thick, entire depletion of the film is possible. This has been proven in the fully DEPleted

Lean-channel TRAnsistor (DELTA) and the double-gate structure, where a normal SOI thin

film (- 200 nm) is enveloped by the gate electrode [l-21.

In this thesis, a modified SOI MOSFET, the A-channel SOI structure shown in Figure

2.1 is proposed. The principal characteristic is the triangular silicon island located on the

buried oxide formed by anisotropic etching. It cm be seen that the delineation of this

structure depends on the etching process and the SOI film thickness, rather than advanced

photolithography [l]. A normally-thick SOI film with a starting thickness of 230 nm is

used. The gate surrounds the channel from two sides. Due to the interaction of the two sided

fields, the potential distribution in the channel region is uniform and full depletion of the

channel region is obtained.

Department of Elecaical and Cornputer Engineering, University of Toronto 19

Drain Gate oxide

"/ Som

Figure 2.1 Cross Section of the Fully Depleted A-channel SOI MOSFET

2.3 Process Structure

The objective of the proposed structure is to eliminate the floating body effects in a

thick-film SOI device and achieve fully depleted device performance. The process was

designed to be fully compatible with Si CMOS processes and is discussed in detail in the

following paragraphs.

The cross section of the fabricated A-channel SOI NMOSFET is shown in Figure 2.2.

A Bonded and Etched-back SOI (BESOI) wafer was used. The starting SOI thin film was

230 nm thick with a <100> orientation and a resistivity of 14 &cm, p-type. The low film

doping was chosen to leave room for future implementation of PMOSFETs, allowing the

process to be expanded to an SOI CMOS process.

The gate oxide thickness in the A-channel SOI MOSFET was chosen to be 20 nm. This

relatively thick gate oxide provides more flexibility in the following submicron gate

delineation process using Reactive Ion Etching (RIE) and leaves room for future scaling.

The in-situ doped n+ poly gate layer was 450 nm thick with a sheet resistance of 30

Nsquan. Self-digned titanium silicide was incorporated in the source and drain regions to

- -. . . - -

Department of Ëlectrkal and Cornputer Engineering, University of Toronto 20

reduce the parasitic resistance. Aluminum was used for the final metallization. The

specified process parameters are summarized in Table 2.1.

Side-wdl s pacer

Silicide

n+ I P I + Binied oxide

Figure 2.2 Fully Depleted A-channel SOI MOSFET (a) and Cross Section dong line AA'(b)

Table 2.1 A-channe1 SOI NMOSET Process Parameters

Department of Electrical and Compter Engineering, University of Toronto 21

Value

230

P-fYPe9 14

160

400

20

450

30

300

Parame t e r

Starting SOI Film Thickness

Starting SOI Film Resistivity

Final Height of the TrianguIar Channel

Buried Oxide Thickness

Gate Oxide Thickness

Nf Poly Gate Thickness

Poly Gate Sheet Resistance

Thres hold Voltage

Symbol

-

-

Tsi

T ~ o x

TOX

T ~ l ~

%IY

v t h

Unit

nrn

!&cm

nm

nm

nrn

nm

n/square

mV

2.4 Process Design Considerations

The conventional Si CMOS process was modified to implement the proposed structure.

During the process, there are some critical steps requinng careh1 design and control. These

steps are silicon etching, gate oxidation, submicron polysilicon gate delineation and

LOCOS isolation.

Silicon etching

The key processing step is the fabrication of the triangle-shaped device island located

on the buned oxide. Selective, anisotropic etching of silicon using TetraMethyl-

Ammonium-Hydroxide (TMAH) was utilized to obtain the desired structure [3-51.

Compared to potassium hydroxide (KOH), the most comrnonly used etchant for

anisotropic chernical etching of silicon, TMAH offers several advantages. It hardly attacks

the silicon dioxide. The thermal silicon dioxide ( S i 4 ) etch rate in TMAH is roughly ten

times lower than that in KOH [4]. Hence, high selectivity is achieved and the oxide can be

used as an etch mask and an etch stop. Furthemore, TMAH does not contain harmful ions.

Finally, it is often used as a developer for photoresist in VLSI processing, therefore, it is

fully compatible with the conventional silicon processing [SI.

The procedure for creating the A-channel structure is shown in Figure 2.3. A pad oxide

is thermally grown on the substrate, followed by a deposition of a nitride layer. On top of

the nitride, another layer of oxide is deposited by LPCVD. The LPCM) oxide is densified

and pattemed as the mask for nitride wet etching, as shown in Figure 2.3 (a). After the

nitride is pattemed, the LPCVD oxide is stripped over the whole wafer. The pad oxide

region not covered by the nitride is also rernoved, opening the window for silicon etching,

as shown in Figure 2.3 (b). The Si etching is then performed in TMAH. The exposed silicon

region undergoes anisotropic etching, while the regions protected by the pad oxide and the


nitride remain untouched. The (1 11) facets are gradudy exposed due to the anisotropy of

the chemical process and the etching stops at the buried oxide due to the etch rate selectivity

between Si and SiO2. One side of the triangular silicon island is obtained. Next, a selective

oxide is grown to protect the exposed planes, as shown in Figure 2.3 (c). The nitride layer is

stripped and the pad oxide is removed. Silicon etching is performed again to obtain the

other side of the channel. Finally, the selective oxide is removed. The triangular silicon

isiands are obtained on the buried oxide, as shown in Figure 2.3 (d).

l 1 . 4

d oxide P-Si P-Si ---+

Buried oxide

Si sub.

(a)

Pad oxidc

+ Buried oxide

Si sub.

- Buried oxide

Si sub.

Figure 2.3 Fabrication of the Triangular Silicon Islands Located on the Buried Oxide

Gate oxîdation

For dl MOS devices, the propeny of the gate oxide is of critical importance in

determining device performance. In the proposed A-channel structure, there is a sharp

convex corner. The gate oxidation, performed over the non-planar silicon surface, requires

special consideration.


It is commonly acknowledged that due to the stress increase following the volume

increase during conversion from Si to SiO2, the thermal oxide grown at silicon convex

corners might be as much as 30% thinner than that on a planar surface at a medium

temperature (cl000 OC) 161. The thinning of the oxide at the corners results in higher

leakage current, causing reliability problem. At higher temperatures, oxidation inhibition

becomes less because of the reiief of die stress by viscous Bow of die oxide. A high-

temperature oxidation process (> 1000 OC) prior to gate oxidation was therefore used to

effectively round off the convex corner and ensure that a highquality gate oxide can be

grown [7,8].

The gate oxidation, in this work, incorporates the following steps. A sacrificial oxide is

first grown at 1100 O C before the threshold adjust implantation. This oxide also acts as the

screen oxide for ion implantation. Then the BF2+ implantation is performed to adjust the

threshold voltage of the device. After the implantation, the sacrificial oxide is removed and

the gate oxide is regrown at 1 1 0 O C in a diluted oxygen-nitrogen ambient [9]. The

advanced hydrogen annealing technique for rounding off corners at a lower temperature,

was not adopted due to the incompatibility of the available oxidation equipment [IO].

A small amount of HCI is introduced to reduce the arnount of the mobile ionic charge

in the oxide, hence, increasing the stability under thermal and bias stresses.

Submicron polysilicon gate delineation

In the process, the subrnicron polysilicon gate is patterned using Reactive Ion Etching

(EUE). A chlorine based plasma is used. Etching silicon dioxide with chlorine is not a

thermodynamically favored reaction, hence, Cl atoms etch SiOz very slowly. On the other

hand, heaviiy doped n-type polysilicon is etched at high rates in the presence of Cl [Il-121.

Therefore, high selectivity of etch rate ratio between n+ polysilicon and silicon dioxide is

obtained in the chlorine plasma. The high selectivity provides two benefits: (1) the etching

pp --

Department of Elechical and Cornputer ~ngineehn~, University of Toronto 24

of the polysilicon cm be controlled to stop on the thin gate oxide, protecting the source and

drain substrates from ion bombardment, and (2) an oxide layer can be deposited and

patterned on top of the polysilicon as the etching mask instead of the photoresist because

the latter suffers severe erosion in the presence of chlorine.

In order to ensure anisotropic etch profiles, BC13, an inhibitor fonning gas, is

introciuced into the chlorine plasma to generate sidewall polymerization. The lateral etching

c m thus be prevented and nearly-vertical etch profile can be obtained[l2].

LOCOS oxidation

LOCal Oxidation of Silicon (LOCOS) was utilized to provide device isolation. LOCOS

in SOI is much the same as LOCOS in bulk silicon except that over-oxidation is necessary.

For a bulk MOS process, where a field oxide layer is formed, a silicon layer with a thickness

equal to 0.45 times the thickness of the field oxide layer is consumed. In SOI technology,

however, the time needed for oxidation is equal to the time required to grow a thermal oxide

with a thickness 3 times the thickness of the silicon film for a bulk device. If the oxidation

time is shorter than this required amount, LOCOS is incomplete and silicon filaments may

remain, leading to failure of device isolation [ 131.

2.5 Process Flow

Cross-section diagrarns at various stages of the process are illustrated in Figure 2.4. A

total of eight masks are used for this experimental process. The process involves the

following steps.

First, a screen oxide is grown and boron implantation is performed to set the doping

1eveI in the substrate. After the implantation, the screen oxide is removed.

Next, the wafer is prepared for Si etching. A thin oxide is grown on the bare wafer and

a nitride layer is deposited in the LPCVD. Another oxide layer is deposited on top of the

Deparmient of Electricd and Computer Engineering, University of Toronto 25

nitride. Then, the LPCVD oxide is patterned with mask #l (1st Si Etch). Chemicai etching

of nitride is carried out using the pattemed oxide as the mask. After the nitride is pattemed,

the LPCVD oxide is stripped al1 over the wafer. The pad oxide region which is not covered

by the nitride is dso removed, opening the window for silicon etching, as s h o w in Figure

2.4 (a).

Anisotropic etching of silicon is performed in TMAH. The pad oxide acts as the

etching mask and the buned oxide as the etch stop. The etching of the (1 11) facets is so

slow that Si etching stops on these planes. One side of the triangular silicon island is

obtained, as shown in Figure 2.4 (b).

A thermal oxide is selectively grown on the exposed (1 1 1) planes as shown in Figure

2.4 (c). The nitride layer is stripped after the oxidation. The pad oxide is pattemed using

mask #2 (2nd Si Etch). The silicon etching is carried out again. After rernoving the selective

oxide, the triangle-shape silicon island located on the buried oxide is created as shown in

Figure 2.4 (d).

Following is the LOCOS process. A thin oxide is grown for stress relief followed by a

nitride Iayer deposition and an oxide deposition in LPCVD. Using the sarne methods as

opening the window for the first silicon etching, the device active region is defined with

mask #3 (Active Region). Wet oxidation is performed to grow the LOCOS oxide, providing

isolation between devices. The nitride and the thin oxide protecting the device region is

chernically removed.

A sacrificial oxide is grown. This oxide helps to round off the convex corners and

hinctions as the screen oxide for ion implantation. BF2+ implantation is carried out to adjust

the threshold voltage.

The gate oxide is regrown &ter the implantation. An in-situ phosphorus-doped

polysilicon is deposited as the gate materid, foiiowed by the deposition of masking oxide in

Department of Elecmcd and Cornputer Engineering, University of Toronto 26

LPCVD. The LPCVD oxide is pattemed with mask #4 (Gate). The photoresist is stripped

cornpletely and the wafer is reloaded in RIE. After a short (15 seconds) pretreatrnent in

fieon plasma, the polysilicon is etched in chlorine-based plasma with the oxide as the mask.

Due to the high selectivity, the etching stops on the gate oxide, as shown in Figure 2.4 (e).

Next. a screen oxide for sourcefdrain implantation is deposited. Arsenic implantation is

cax-ried out to form the n-type heavily-doped source and drain regions. The photoresist is

used as the mask pattemed with Mask #5 (Source/drain).

The sidewall spacer is fabricated as follows. A layer of oxide is deposited in LPCVD

and densified in Rapid Thermal Annealing (RTA). The thermal treatment also activates the

implanted ions. Then, the oxide is anisotropically etched in freon plasma to f o m the

sidewdl spacer.

A titanium silicide process is utilized to form ohrnic contact to the source and drain

regions [14]. A blanket titanium film is deposited. A low-temperature treatrnent (675 O C ) is

performed in an nitrogen arnbient to form titanium silide (Tisi2) with a C49 crystal

structure. There is no reaction between Ti and SiO2. Hence, Tisi2 only forms in the source

and drain region. The unreacted titanium, which is deposited on the field oxide and on the

sidewall spacer, is selectively removed in H202:NH40H water solution. A high-temperature

annealing (850 OC) is cmied out to convert the silicide structure from the high-resistivity

C49 phase to the low-resistivity CS4 phase, as shown in Figure 2.4 (0.

A 500 nm oxide is deposited for passivation. After densification, the oxide is pattemed

to open the contact window on the polysilicon gate and the source/drain region with mask

#6 (Contact on Gate) and mask #7 (Contact on Silicide), respectively. An 800 nm alurninum

film is sputtered on the wafer and pattemed with mask #8 (Metal). Finally, the aluminum is

anneaied in f o d n g gas to reduce the contact resistance and the amount of the interface-

trapped charge.

Department of Elecuical and Cornputer Engineering, University of Toronto 27

Buried oxide Si sub.

(a)

Poly \ oxid

Oxide Si N s Buried oxide

Si sub.

(bl

(~uried oxide I/ / Si sub.

Buried oxide

( f )

Figure 2.4 Process Flow of Fabricating A-channel SOI MOSFETs

Department of Elecaical and Compter Engineering, University of Toronto 28

A summary of the process flow of the A-channel SOI MOSFET is presented in Table

2.2. The process parameters indicated in the table were initially obtained from simulation.

Table 2.2 A-channel SOI MOSFET Process Flow

Sacrificial Oxide 1 Growth

1 S tep II Process Description

Dry Oxidation: Temperature = 1 Oûû°C,

Thickness = 50 nm

Scarting Material

1 Bomn Implantation II Energy = 25 keV, Dose = 9e12 cm-'

BESOI wafer: 14 Gan, p-type, 4 O(k

II Dry Oxidative: Temperature = 1 0 O C

Pad Oxide Growth Thickness = 20 nm

II LPCM: Temperature = 800 OC. Gas = NH3 + SiHfi12 Nitride Deposition

Thickness = 100 nm

Oxide Deposition

1 Nitride Etching 11 Wet Etching: phosphoric a d , Temperature = 180 OC

LPCVD: Temperature = 41 5 OC, Gas = SiH4 + Oz Thickness = 100 nm

1 st Si-Etch Definition

I d e Stripping II Wet Etching: Buffered HF

Photolithognphy: Mask #i ( 1 st Si Etch),

Wet Etching of LPCVD oxide in Buffered HF (BHF)

1 Si Etching II Si Etching: TMAH (10%). Temperature = 75 OC - -

Protective Oxide Wet Oxidation: Temperature = 100 O C

Thickness = 100 nm

Photolithography: Mask #2 (2nd Si Etch), 2nd Si-etch Definition

Removal of pad oxide: 5% HF

Nitride Removal

Si Etching: TMAH (IO%), Temperature = 75 O C

Stripping pmtective oxide

Wet Etching: Phosphonc Acid,

Temperature = 180 O C

- - - -


S tep Process Description -

Stress Relief Oxide Growth

Dry Oxidation: Temperanire = 1 100 OC

ïhickness = 24 nm - -

LPCVD: Temperature = 800 OC, Gas = NH3 + SiHfl12

ïhickness = 100 nrn Nitride Deposition

LPCVD: Tempenture = 425 OC, Gas = SiHo + O2

ïhickness = 100 nm Oxide Deposition

Photolithography : Mask #3 (Active Region)

Wet Etching of LPCVD Oxide in Buffered HF LOCOS Definition

Nitride Etching Wet Etching: phosphoric acid, Temperature = 180 OC -- -

Oxide Stripping Wet Etching: Buffered HF

Wet Oxidation: 1 100 OC,

Thickness = 600 nm (Bulk Si wafer) LOCOS growth

- - -

Wet Etching: Phosphoric Acid, Temperature = 180 OC Nitride Stripping

Dry Oxidation: Tempenture = 1 100 O C ,

Thickness = 35 nm

Sacrificial Oxide Growth

Bomn Implantation: Dose = 60 KeV

Energy = 3.4e 12

Threshold Voltage Adjustrnen t - -

Sacrificial Oxide Stripping

Wet Etching: Buffered HF

Dry Oxidation: Temperanire = 1100 OC

O2 = 0.8 LPM, N2 = 9 LPM, HCI = 10.1 SCCM

Thickness = 20 nm

Gate Oxide Growth

-

LPCVD: Tempenhm = 600 OC, Gas = PH3 + S N 4

Thickness = 500 nm Gate Poly Deposition

LPCVD: Temperature = 425 OC, Gas = S a 4 + O2 Thickness = 5 0 nrn

Oxide Deposition

-

Photolithography : Mask #4 (Gate)

RIE oxide: Gas = CZFs + CHF3

RIE polysilicon: Gas = Cl2 + BCS Gate Definition


Process Description - --

LPCVD: Temperature = 425 O C , Gas = SiH4 + O2 Thickness = 300 nm,

RIE Oxide: Gas = c2F6 + CEE3

LPCM: Temperature = 4 15 OC, Gas = SiHd + O2 Thickness = 50 nm

Photolithognphy: Mask #5 (SID Imp)

Arsenic Implantation: Dose = Se 15 cm",

Energy = lûûKeV

Removal of Screen Oxide in 5% HF - - - -

Sputtering: Titantinurn, Thickness = 30 nm,

1st Annealing at 675 OC for 30 seconds,

Wei Erching of Ti in (H202 + NH40H),

2nd Annealing at 850 O C for 30 seconds

LPCVD: Ternpennire = 425 OC. Gas = SiH4 + Or

Thickness = 500 nm

Photolithognphy: Mask #6 (Contact on Silicide),

RIE Oxide: Gas = C2F6 + CHF3

Photolithography : Mask #7 (Contact on Gate),

RIE Oxide: Gas = c2F6 + CHF3 - -

Sputtering: AiSi, Thickness = 800 nm - - --

Photolithognphy: Mask #8 (Metai),

Wet Etching of Al

Annealing: Forming Gas = 5% Hz + 95% N2

Temperature = 435 OC

2.6 Process Simulation

The two-dimensional process simulation using TSUPREM-4 [IS] was carried out for

the cross section dong the line A-A', as shown in Figure 2.5 (a), to set up the initial process

Department of Electricd and Cornputer Engineering, University of Toronto 3 1

parameters. Figure 2.5 (b) presents the simulated structure using TSUPREM-4.

Figure 2.5 A-channel SOI MOSFET: Cross Section (a) and TSUPREM-4 Structure (b)

The doping profile in the channel region is shown in Figure 2.6 (a). The doping is

approxirnately uniform with a concentration of 5 x 1 0 ' ~ cm-3. Figure 2.6 (b) shows the

doping profile in the sourceldrain region. The concentration at the surface is greater than

10" cm".

Figure 2.6 Doping Profiles in the Channel Region (a) and in the source/drain region (b)


2.7 Device Simulation Setup

The device performance was evaluated using a three-dimensional device simulator

DAVINCI [16]. The doping concentration in the channel region was chosen to be p-type,

5e16 cm3. This is close to the result of the process simulation. The doping profile in the

source/drain region was dcfincd to be üniforn, n-type, 5e 19 cn i3 for simplific~tion. This

value is approximately the average of the process simulation result. The simulation

parameters are listed in Table 2.3. The parameters of a conventional SOI NMOSFET are

also presented in the table.

Table 2.3 Parameters in Device Simulation

Pararne ter

1 SOI Thin Film Thieknerr (Tsi) - -

Gate Oxide Thickness (T,,)

Doping in Channei

Doping in SourceIDrain

Unit Conventional A-channel SOINMOSFET SOINMOSFET

cmJ p-type, Se16 1 p-type. 5e16

n- type, Se 1 9 n-type, sel 9

The half device structure generated in DAVINCI is show in Figure 2.7. Sorne

simplifications were made to simplify the simulation, as discussed in the following

paragrap hs .

Department of ElecaicaI and Cornputer Engineering, University of Toronto 33

Source (or Drain) Q

Figure 2.7 Device Structure in DAVINCI Simulation

The silicon island fabricated by anistotropic etching is isosceles, as shown in Figure 2.8

(a). In the simulation, it was approxirnated by a right-angled triangle, as shown in Figure 2.8

(b). In this diagram, ddep is the width of the maximum depletion region controlled by the

gate and WeR is the effective channel width. The two sides of the structure, hence, are

defined parallel to y axis and z axis. The planes, dong which the current flows, are

specified in the x-y plane and the x-z plane as shown in Figure 2.7. The effective channel

width is the sum of the two sides in the triangular structure. This approach greatly

simplified the definition of the gate oxide region and the gate electrode region.


(a) (b)

Figure 2.8 Right-angled Triangle Approximation of the A channel

The tnangular channel, which is the light-grey part shown in the y-z plane in Figure 2.7,

is defined as follows. After a mesh is specified. the material in each grid square is identified

as either silicon or silicon dioxide, as shown in Figure 2.9. The number of the mesh points

m u t be reasonable. A finer mesh provides more accurate simulation, however, it may take

an unacceptable long time to complete one simulation cycle.

Figure 2.9 Definition of the Triangu Channel


The gate electrode is defined as two separate electrodes: one in the x-y plane and

another in the x-z plane as shown in Figure 2.7. In the simulation, the same voltage is

applied to the two electrodes, causing them to effectively act as one gate surrounding the

c hanneI.

2.8 Simulated Device Characteristics

The simulated Id, - Vg, transfer charactenstics for a A-channel SOI NMOSFET with an

effective gate length of 0.8 ym is shown in Figure 2.10 (a). The drain current (h) is

nomalized to a per micron effective gate width. The threshold voltage Vh is defined as the

value of Vg, intercepted by the tangent drawn at the inflection point on the h, - Vg, curve of

a MOSFET in the ohmic region of operation. The inflection point is where Vg, corresponds

to the maximum tramconductance. Using this technique, the threshold voltage was

extracted to be 308 mV.

Figure 2.10 (b) presents the subthreshold characteristics. In the weak inversion regime,

the drain current depends exponentially on gate voltages. The subthreshold swing or the

subthreshold slope is defined as the inverse of the slope which indicates the sharpness of the

current transition from the "off' state to the "on" state. The subthreshold dope in the

proposed SOI NMOSFET is 63 mV/dec. This is the typical value of fully depleted SOI

NMOSFETs [V I .

By cornparison, the gate transfer and subthreshold characteristics for a conventional

SOI NMOSFET are shown in Figure 2.1 1. The threshold voltage is 495 mV and the

subthreshold swing is 87 mV/dec.

~epartrnent of Electncal and Cornputer Engineering, University of Toronto 36

Figure 2.10 Transfer (a) and Subthreshold (b) Characteristics for a A-channel SOI NMOSFET Vd, = 0.05 V

Figure 2.1 1 Transfer (a) and Subthreshold @) Characteristics for a Conventional SOI NMOSFET Vd, = 0.05 V

Department of Electricai and Cornputer Engineering, University of Toronto 37

Simulation of the threshold voltage as a function of the gate length (L) is shown in

Figure 2.12. It can be seen that threshold voltage roll-off in the A-channel SOI MOSFET is

significantly smaller than that in the conventional SOI device, indicating that the proposed

device possesses better imrnunity from the short channel effects.

I I - ' 1 ,, 1 Conventional SOI NMOSET 1

-J 0 2 3 4 06 38 12 4 i f ' 9 2

Gate Length L (pn)

Figure 2.12 Threshold Voltage as a Function of Gate Length in t Conventional SOI and the A-channel NMOSFETs

The simulated output characteristics for a A-channel and a conventional SOI

NMOSFETs are shown in Figure 2.13. It is clearly seen that the kink in a conventional SOI

NMOSFET is suppressed in the A-channel structure, because the potentiai in the channel

region is tightly controlled by the gate electrode and the channel remains hIly depleted

duhg operation. The potential b k e r between the source and the body is smaller in the

depleted film. The majonty carriers (holes), which are generated by impact ionization, can

peoetrate more easily into the source. Therefore, excess accumulation of holes, which

reduces the threshold voltage and results in kinks in the drain curent, is prevented.


Figure 2.13 Output Characteristics of a Conventional SOI (a) and a A-channel (b) SOI NMOSFET Vg, - Vih=0.2 V, 0.4 V, 0.6 V, 0.8 V, 1.0 V

The breakdown characteristics were simulated when Vg, = O V. Figure 2.14 shows the

simulation result. The breakdown voltage o f the A-channel device is 3.86 V, while it is 4.44

V for the conventional MOSFET. The breakdown voltage of the A-channel structure is

lower than that of the conventional devices due to the higher electrical field in the three

dimensional structure. n ta-!

Figure 2.14 Breakdown Characteristics when Vg, = O V

Department of Electlical and Cornputer Engineering, University of Toronto 39

The performance of the fùlly depleted A-channel SOI NMOSFET was evaluated in this

section. Table 2.4 summarizes the simulation results and the cornparison with a

conventionai SOI device.

Table 2.4 Simulated Device Performance of a Conventional SOI NMOSFET and a A-channel SOI NMOSFET

1 unit i Conventional SOI NMOSFET

SOI Film Thickness (Tsi)

Gate Oxide Thickness (T,,)

Threshold Voltage (Vd

nm

nm

I& (V, -v, = 1.0 v* v, = 1.0 v)

Kink in Output Chiuacteristics

A-channel SOI NMosFET i

160

20

mV

.. - - pp

Breakdown Voltage (V* = O V)

2.9 Enhanced Conduction in bchannel SOI NMOSFETs

495

Ww ---

In the above simulation. the surface-mobility model was chosen for the analysis of both

the proposed structure and the conventional device. However, the surface-rnobility model,

which provides a reasonable prediction of the conduction in a thick-film SOI channel,

underestimates the carrier mobility behavior and the current drivability in a hilly depleted

SOI device. In the triangle-shaped structure, due to the excellent coupling between the two

side gates, greatly enhanced mobility, as a result of carrier spreading in the volume, is

expected [2,21-221. The majority carrien are no longer confined at interfaces, and many of

hem flow in the volume of the siIicon island. The surface related scattering, which reduces

the carrier mobility dong the insulator-serniconductor interface, are substantially

42

Yes

V

- - -


4.44

suppressed and the effective carrier mobility and the current driving capability are

enhanced.

In order to predict the performance of the proposed device, the surface-mobility model

was rnodified to the concentration dependent mobilityf to take the enhanced mobility in the

SOI films into account [2, 21-24]. Figure 3.15 shows the simulated transfer and output

characteristics of the device using this mobility model. The threshold voltage is 327 mV.

The drain current is 69 pA/pm. at (Vgs - Vrh) = 1 .O V and Vd, = 1 .O V. As will be seen in

Chapter 3, these simulations provide a reasonable agreement with the experimental results.

Fig. 3.15 Gate Transfer (a) and Output Characterisitcs (b) of the A-channel SOI NMOSFET using the Concentration Dependent Mobility Mode1

Department of Electncal and Computer Engineering, University of Toronto 41

* Mobility versus Irnpuity Concentration for Silicon (T = 300 K) 1161

6e 16

760 - Concentration (cm-3) Eleç tron Mo bili ty ( C ~ - ~ N - S )

4e16

845

This chapter presented the device fabrication process and the simulated device

performance. A process Row was designed to implement the fully depleted A-channel SOI

MOSFET. Fabrication issues were discussed. The process parameten were verified using a

two-dimensional process simulator. The process is compatible with the conventional Si

CMOS process .

The performance of the A-channel SOI MOSFET was evaluated using a three-

dimensional device simulator. The simulation results show that the proposed device works

in the fully depleted SOI mode. The floating body effect was substantially suppressed and

ultrathin SOI device behavior was achieved including quasi-ideal subthreshold swing and

absence of kink effect in the output characteristics. The enhanced conduction in the

proposed structure was also analyzed.


Reference

[l] D. Hisamoto, T. Kaya, Y. Kawarnoto and E. Takeda, "A Fully DEPleted Lean-channel TRAsistor (DELTA) - A Novel Vertical Ultra Thin SOI MOSFET," International Elec- tmn Device Meeting (IEDM) Digest, pp. 833-836, 1989.

[2] F. Balestra, S. Cristoloveanu, M. Benachir, J. Brini and T. Eiewa, "Double-gate Silicon- on-Insulator Trasistor with Volume Inversion: A New Device with Greatly Enhanced Performance," IEEE Electron Device Letters, vol. 8, pp. 4 10-4 12, 1987.

[3] K. Tokoro, D. Uchikawa, M. Shikida and K. Sato, "Anisotropic Etching Properties of Silicon in KOH and TMAH Solutions," International Symposium on Micromechatron- ics and Hwnnn Science, pp. 65-70, 1998.

(41 0. Tabata, "Anisotropy and Selectivity Control of TMAH," International Worhhop on Micro Electro Mechanical Systems (MEMS) Proceedings, pp. 229-233, 1998.

[SI H. Shimada, S. Shimonura, R. Au, M. Miyawaki and T. Ohmi, "Enhancement of Reso- lution and Linearity Control of Contact-hole Resist Patterns with Surface-active Devel- oper," IEEE Trans. Semiconductor Manufacturing, vol. 7, pp. 389-393, 1994.

[6] R. B. Marcus and T. T. Sheng, "The Oxidation of Shaped Silicon Surfaces," Journal of the Electmchemical Sociery, vol. 29, pp. 1289- 1282, 1982.

[7] K. Yarnabe and K. Irnai, "Nonplanar Oxidation and Reduction of Oxide Leakage Cur- rent at Silicon Corners by Rounding-off Oxidation,?' IEEE Trans. Elec~on Devices, vol. 34, pp. 168 1-1686, 1987.

[8] K. Nakarnara, T. Minato and T. Takahashi, 'Evaluation of Thick Silicon Dioxide Grown on Trench MOS Gate Structures," International Symposium on Power Semicon- ductor Sevices and ICs (ISPSD) Proceedings, pp. 79-82, 1996.

[9] J. C. Ranaweera, Development of a Flash EEPROM Ce11 Suitable for EV Operation, M. A. Sc. Thesis, University of Toronto, 1995.

[IO] S. Matsuda, T. Sato, H. Yoshimura, Y Takegawa, A. sudo, 1. Mimshima, Y. Tsunash- ima and Y. toyoshima, "'Novel Corner Rounding Process for Shallow Trench Isolation utilizing MSTS (Micro-Stmcture Transformation of Silicon," International Electron Device Meeting (IEDM) Digest, pp. 137-140, 1998.

[Il] C. Y. Chang and S. M. Sze, ULSI Technology, The Mcgraw-Hill Companies, Inc. 1996.

[12] S. A. Campbell, The Science and Engineering of Micmelectronic Fabrication, Oxford University Press, New York, 1996.

[13] .J. B. Kuo and K. W. Su, CMOS VLSI Engineering: Silicon-on-lnsulator (SOI), Kluwer Academic Publisher, Norwell, USA. 1998.

--


[14]L. D. Pede, A I V h w Power CMOS Process, M. A. Sc Thesis, University of Toronto, 1998.

[ 151 Tsuprem-4 User's Manual: Version 6.5. Technology Modeling Associates, Inc.

1161 Davinci User's Manual: Version 9 1 14, Technology Modeling Associates, Inc.

[17] J. P. Colinge, Silicon-On-Insulator Technology: Materials to VLII , Kluwer Academic hblishers, Norwell, L997.

[ISIS. C. fiehne, A. B. Y. Chan, C. T. Nguyen and S. S. Wong, "SOI MOSFET with Bur- ied Body Strap by Wafer BondinglT' IEEE Trans. Electron Devices, vol. 45, pp. 1084- 1091, 1998.

[19] W. Chen, Y. Taur, D. Sadan, K. A. Jenkins, J. Sun and S. Cohen, "Suppression of the SOI Floating-body Effects by Linked-body Device Structure," iEEE Symposium on M S I Techno[ogy Digest of Technical Papers, pp. 92-93, 1996.

[20]A. Nishiyama, O. Arisumi and M. Yoshimi, "Mechanism of the Suppression of the Floating-body Effect for SOI MOSFETs with SiGe Source Structure," IEEE Interna- tional SOI Conference Proceedings, pp. 68-69, 1996.

[21] D. Hisamoto, T. Kaga and E. Takeda, "Impact of the Vertical SOI "DELTA" Structure on Planar Device Technology," IEEE Trm. Electron Devices, vol. 38, pp. 14 19- 1424, 1991.

[22] J. P. Colinge, M. H. Ga, A. Romano-Rodngues, H. Maes and C. Claeys, "Silicon-on- Insulator "Gate-dl-around" Device," International Electron Device Meeting (IEDM) Digest, pp. 595-598, 1990.

[23] Y. S. Chang and S. S. Li, "Modeling and Parameter Extraction of Gate-ail-around nMOS/SOI Transistors in the Linear Region," Solid-State Electronics, vol. 39, pp. 991- 997, 1996.

[24] K. K. Young, "Analysis of Conduction in Fully Depleted SOI MOSFET," IEEE Trans. Electron Devices, vol. 36, pp. 504-506, 1989.

Department of EIectncaI and Computer Engineering, University of Toronto 44

CHAPTER 3

Fully Depleted A-Channel SOI MOSFET Fabrication and Characterization

3.1 Introduction

The purpose of this chapter is to present the expenmental work dealing with the

implementation of the proposed A chmnel SOI MOSFET. Using a conventionai CMOS-

compatible process, the proposed device was successfully manufactured and the device

performance was investigated.

This chapter is organized as follows. The development and characterization of the

silicon etching, the critical processing step, is presented first. Then, the design of the test

chip is described. The characteristics of the fabricated devices are presented and the results

are discussed. Fully depleted SOI device performance was obtained including excellent

subthreshold characteristics, absence of kinks in the drain current, enhanced

transconductance and higher current driving capability.

3.2 Development of the Etching Process

The key feature of the proposed structure is the generation of the tRangu1a.r shaped

silicon island located on the buried oxide. Anisotropic etching of silicon was utilized to

implement the structure. The development and characterization of this process are discussed

in the foilowing paragraphs.


Etch rate selectivity

In this work, the silicon islands were delineated by anisotropic etching of silicon using

a 10% TMAH (tetrarnethyl-ammonium-hydroxide) water solution as the etchant [l-41.

Compared with the KOH etchant [34], commonly used for chemical etching of silicon,

TMAH is highly-selective. non-toxic and fully-compatible with current Si processing.

The etching was tested using a (100)-onented wafer. By measuring the etch rate of the

(100) and (1 11) planes, the selectivity of the etchant was obtained. The etch rate of the

(LOO) plane was simply extracted by measuring the etch depth (Letch(lOO)) using the Alpha

Step 200 surface profiling system. The etch rate of the ( 1 1 1) plane was determined using the

geometry of the trench illustrated in Figure 3.1 [2]. The lateral etch (Lunderetch) W ~ S

measured by examining the undercut under a high-resolution optical microscope. Through

simple geometricai cdculation, the etching in the cl 11> direction (Letch(lll)) was

determined, and the etch rate of the ( 1 I l ) plane was obtained. Table 3.1 lists the etch rates

obtained using the TMAH process and confirms that high etch rate selectivity was achieved.

Lundcrctch ( 100) etch depth 4 ;+ Leich( fW)

Oxidc

(1 1 1 ) Etch Lach(l11) D

Si

Figure 3.1 Cross Section of the Etched Trench ïîlustrating Relevant Dimensions

Department of Electncal and Computet Engineering, University of Toronto 46

Table 3.1 Etch Rates for 10% TMAH at 75OC -- -

1 Material 1 Orientation 1 Etch Rate (ndmin.) 1 Nonnalized Etch Rate 1

Characterization of the etch profile

Following the procedure discussed in Section 2.4, the implementation of the triangle-

shaped silicon islands was verified using a (100)-oriented SOI wafer. The etch profiles were

examined by Scanning Electron Microscopy (SEM). Figures 3.2 and 3.3 presents the SEM

micrographs foilowing some of the criticai steps in the process. Figure 3.2 (a) shows the

cross section of the silicon island after patteming of the nitride and oxide layers, and

anisotropically etching of silicon. It cm be seen that the exposed (1 1 1) planes have a

inclination of about 54.7' from the horizontal direction. Figure 3.2 (b) presents the cross

section after the selective oxide growth. This oxide protects the exposed facets dunng the

subsequent silicon etching. The cross section after the second silicon etching is shown in

Figure 3.3 (a). Figure 3.3 (b) shows the cross section of the delineated silicon islands.

Figure 3.2 SEM Micrographs of Cross Sections in the Silicon Etching Rocess (#1) (a) After Fint Silicon Etching; (b) After Selective Oxide Growth


Figure 3.3 SEM Micrographs of Cross Sections in the Silicon Etching Process (#2) (a) After Second Silicon Etching; (b) Fabricated Silicon Islands

3.3 Test Pattern Design

The test patterns were designed using a 0.8 prn minimum Iine width. Eight masks were

involved in the process. The detailed description of the mask and the layout rules are

presented in Appendix A.

Fig. 3.4 illustrates the test mask layout. The test chip occupies an area of 3500 pm x

4400 ym. It consists of A-channel SOI MOSFETs as well as conventional SOI MOSFETs

with different dimensions. Test structures for sheet resistance and contact resistance

measurements, capacitor structures and structures for Scanning Electron Microscopy

(SEM) of the etch profiles are also included. Specifically, the structures included on the test

chip are:

(a) Twenty-eight A channel SOI MOSFETs, composed by 1, 10, and 50 silicon islands,

with gate Iengths of 0.8 Pm. 1 Pm, 2 p and 5 Pm.

(b) Four interdigitated A-channel structures, consisting of 10 silicon islands, with gate

lengths of 0.8 pm and 2 Pm.

Department of Elecaical and Cornputer Engineering, University of Toronto 48

(c) Sixteen conventional SOI MOSFETs with the gate lengths of 0.8 Pm, I Pm, 2 Pm, 5

Pm, and gate widths of 10 pn and 20 ym.

(ci) Four conventional interdigitated structures with the gate lengths of 0.8 pm and 2

pm, and a gate width of 10 Pm.

(e) Two A-channel capaciton (e') and two planar capacitors (et') for C-V profiling.

(f) One structure to monitor the etching process.

(g) Ten structures to measure the sheet and contact resistances.

Figure 3.4 Test Chip Layout (a) A-channel SOI MOSFETs; (b) Interdigitated A-channel Struchires; (c) Conventional SOI MOSFETs; (d) Interdigitated Conventional Structures; (e') A-channel Capacitors; (e") Planar Capacitors; (f) Structure for Etching ; (g) Structures for Resistance Measurernents

-


3.4 Test Chip Implementation

The CMOS-compatible process developed in Chapter 2 was used to irnplement the test

chip. Figure 3.5 shows the micrograph of the fabricated chip. The top views of individual

devices are shown in Figure 3.6. Figure 3.6 (a) presents a A-channel SOI NMOSFET which

consists of one silicon island, and Figure 3.6 (b) shows a A-channel device cornposed by

fifty siiicon islands in parallel.

Figure 3.5 Micrograph of the Fabricated Test Chip


Figure 3.6 Top Views of Fabncated A-channel SOI NMOSFETs (a) One Silicon Island, L = 0.8 prn, W = 0.32 pm (b) 50 Silicon Islands in Parallel, L = 0.8 Pm, W = 16 pm

3.5 Process Characterization

The process parameters were monitored using different test structures during the

process and are sumrnarized in Table 3.2. The thickness of the gate oxide was determined

by measuring a dummy wafer using the Nanospec 4000. The four-point probe system was

used to measure the sheet resistance of the n+ poly gate. The thicknesses of the polysilicon,

oxide, nitride and metal layer were measured using the Alpha Step 200. A six-terminai test

structure was used to measure the specific contact resistance [5].

Department of Electncal and Cornputer Engineering, University of Toronto 51

Table 3.2 Process Characterization

3.6 Device Characterization

Figures 3.7 (a) and (b) present the SEM micrograph of a fabricated A-channel SOI

MOSFET with one silicon island and a conventional MOSFET. Both the proposed and the

conventional devices were investigated and their characteristics are discussed in the

following paragraphs. All the measurements were normaijzed to a per micron effective gate

width. The gate length of the devices was 0.8 pm.

Value

230

ptw, 14

130

22

450

3 1.2

550

1.2

4 . 1 ~ 1 0 ~

1 .5x 1 o ' ~

Parme ter

Starting BESOI Layer Thickness

Starting BESOI Resistivity

SOI Layer Thickness after Processing

Gate Oxide Thickness

n+ Paly Gate Thickness

n+ Poly Gate Sheet Resistance

Passivation Oxide Layer Thickness

Metd Layer Thickness

M d - n + Poly Specific Contact Resistance

Me taldiffision Speci fic Contact Resistance

Figure 3.7 SEM Micrographs of a Fabricated A-channel (a) and Conventional (b) SOI NMOSFET

Unit

nm

R-crn

nm

nm

nm

Nsquare

nm

Pm

&cm2

h m '

Department of Elecûical and Cornputer Engineering, University of Toronto 52

Gate transfer and subthreshold characteristics

The h, - Vgs transfer characteristic for the SOI NMOSFET is shown in Figure 3.8 (a).

By extrapolating the linear region of the Id, - V, curve, the threshold voltage is extracted to

be 690 mV. Figure 3.8 (b) presents the subthreshold characteristic of the conventional

device. The subthreshold slope is 95 mV/dec.

The transfer and subthreshold characteristics of the A-channel SOI NMOSFET are

shown in Figure 3.9. Due to the interaction between the two side gates in the proposed

structure, lower threshold voltage and nearly ideal subthreshold characteristic were

observed. The extracted threshold voltage and the subthreshold swing are 370 mV and 67

mV/dec, respec tivel y.

In the above results, the threshold voltages are higher than the simulation results. This

is attributed to the simplifications utilized in the process and device simulations. The

subthreshold dopes are in agreement with the simulation results.

Figure 3.8 Transfer (a) and Subthreshold (b) Characteristics for the Conventional SOI NMOSFET Vd, = 0.05 V

-- --

Department of Elechicd and Cornputer Engineering, University of Toronto 53

Figure 3.9 Transfer (a) and Su bthreshold (b) Characteristics for the A-channel SOI NMOSFET Vds = 0.05 V

The transconductance was extracted for the conventional and the A-channel SOI

NMOSFETs. The results are compared in Figure 3.10. The maximum transconductance

obtained in the A-channel MOSFET (7.2 pS/pm) is significantly larger (63%) than that of

the conventional device (4.4 pS1pm). As discussed in the following paragraphs, this

increase in transconductance is related to the effective carrier mobility in the triangular

silicon island which exhibits a volume-like behavior and is much higher than the surface

mo bility.


(a) (b) Figure 3.10 Transconductance g, as a Function of V, for the Conventional (a)

and the A-channel (b) SOI NMOSFETs vd, = 0.05 V

Ids - Vas output characteristics

The output characteristics of the conventional and the A-channel SOI MOSFETs were

measured with (Vg, - V*) = 0.2 V, 0.4 V, 0.6 V, 0.8 V and 1.0 V and are illustrated in Figure

3.1 1. It can be seen that the conventional device suffers from severe kinks in the drain

current. In the A-channel structure, however, the output current remains flat and no kink is

observed. The absence of kinks in the output characteristics, in addition to the improved

subthreshold swing and enhanced transconductance, indicates that complete depletion is

achieved in the triangle-shaped channel [6]. The gate electrode, which overlaps both sides

of the rriangular structure, provides a tight control over the channel potential and maintains

the channel in full depletion. Moreover, the current dnving capability in the A-channel

structure is much higher than in the conventional device due to enhanced electron mobility

prevails in the proposed structure. The drain current is 73 iIA/pm, at (Vg, - Vrh) = 1 .O V and


Vds = 1.0 V, agreeing well with the simulation results using the concentration dependent

mobility model. For the conventional MOSFET, the drain current is 39 clA/~m.

Figure 3.1 1 Output Characteristics of the Conventionai (a) and A-channel (b) SOINMOSFETS Vg,-Vlh=0.2 V,0.4 V,0.6V,O.8 V, 1.0V

Mobility evaluation

As shown in Figures 3.10 and 3.1 1, the A-channel device exhibits a much higher

transconductance and much higher current driving capability than the conventionai

MOSFET. This effect originates from the bulk electron mobility present in the triangular

channel[7]. By measunng the small signal output conductance g h as a function of the gate-

to-source biasing Vg,, the effective mobility &R can be extracted.

In the Iinear region, the drain current can be approximated by


where k n is the effective electron mobility, Weff and Len are the effective channel width

and length, respectively.

When a very small voltage is provided between the source and the drain, the output

conductance g k can be expressed as

It can be seen that g k varies linearly with Vg,. Therefore, knowing the physical

parameters of the device, the effective mobility can be extracted from the slope of the g h

The output conductance g b as a hnction of Vg, at small Vd, for the conventional

device and the A-channe1 structure are shown in Figure 3.12. B y measuring the slope of g k

in the linear region, p , ~ is extracted. The extracted value is 729 cm2/Vs for the A-channel

structure, and 438 c m 2 ~ s for the conventional SOI device. It c m be seen that the effective

mobility in the proposed device is significantly higher than the surface mobility which

dominates the conduction in a conventional MOSFET, and is in close agreement with the

simulation using concentration dependent mobility mode1 (see Chapter 2, Section 2.9). The

mobility values obtained are comparable to the effective electron mobility for the gate-all-

around, N l y depleted SOI structure and the ultrathin-film SOI MOSFETs reported in the

literatures [8- 1 11.

- pp -

Department of Electricd and Cornputer Engineering, University of Toronto 57

Figure 3.12 Output Conductances gds as a Function of Vg, for the Conventional (a) and the A-channel (b) SOI NMOSFET when Vds Approaches O V

Breakdom characteristic

The breakdown characteristics for the conventionai and the A-channel SOI

NMOSFETs were rneasured when Vgs = O V. The results are shown in Figure 3.13. For the

conventional device, the breakdown voltage is about 5.8 V, while it is 4.1 V in the A-channel

structure. The lower breakdown voltage in the triangular structure is attributed to the higher

electrical field present in the tnangular structure, which is consistent with the simulation

results.

Department of ElectricaI and Computer Engineering, University of Toronto 58

Figure 3.13 Breakdown Characteristics for the A-channel and the Conventional SOI NMOSFETs when Vgs = O V

A hlly depleted A-channel SOI NMOSFET process was developed and the proposed

device was fabricated. The expenmental results including the characterization of the

process and the device were discussed in this chapter. Compared with the conventional SOI

NMOSFET, the A-channel SOI NMOSFET exhibits an excellent subthreshold swing and

absence of kinks in the drain cunent. Higher transconductance and higher current

dnvability were observed as a result of significantly higher effective bulk mobility. These

results indicate that the proposed A-channel SOI NMOSFET successfully suppresses the

floating body effects in a thick-film SOI device. Due to the excellent coupling of the two

side gates, the gate electrode provides improved control over the channel potential and fully

depleted device performance is achieved.

Deparmient of Elecûical and Cornputer Engineering, University of Toronto 59

References

O. Tabata, b'Anisotropy and Selectivity Control of TMAH," Intemationd Workrhop on Micro Electro Mechanical System (MEMS) Proceedings, pp. 229-233, 1998.

L. M. Landsberger, S. Naseh, M. Kahnzi and M. Paranjape, "On Hillocks Generated during Anisotropic Etching of Si in TMAH," J. of Microelectrochemical Systems, vol. 5, pp. 106- 1 16, 1996.

K. Tokoro, D. Uchikawa, M. Shikida and K. Sato, "Anisotropic Etching Properties of Silicon in KOH and TMAH Solutions," International Symposium on Micromechanics and Human Science, pp. 65-70, 1998.

H. Shimada, S. Shimonun, R. Au, M. Miyawaki and T. Ohmi, "Enhancement of Reso- lution and Linearity Control of Contact-hole Resistance Patterns with Surface-active De~eloper,~' IEEE Trans. Semiconductor Manufacturing, vol. 7, pp. 389-393, 1994.

D. K. Schroder, "Semiconductor Material and Device Characterization," Wiley-Inter- science Publication, 1990.

J. P. Colinge, "Fully-depleted SOI CMOS for Analog Applications," IEEEE Trans. Ekc- tron Devices, vol. 45, pp. 1010-1016, 1998.

S. Cristoloveanu and S. S. Li, "EIectricd Chamcterization of Silicon-on-insulator Materials and DevicesTT' Kltrwer Academic Prtblishers, 1995.

Y. S. Chang and S. S. Li, "Modeling and Parameter Extraction of Gate-all-around nMOSlSOI Transistors in the Linear Region," Solid-State Electmnics, vol. 39, pp. 99 1- 997, 1996.

M. Yoshimi, H. Hazama, M. Takahashi, S. Kambayashi and H. Tango, "Observation of Mobility Enhancement in Ultrathin SOI MOSFETs," Electronics Letters, vol. 24, pp. 1078-1079, 1988.

[IO] B. Mazhiari, S. Cnstoloveanu, D. E. Ioannou and A. L. Caviglia, "Properties of Ultra- thin Wafer-bonded Silicon-on-insulator MOSFET's," IEEE Trans. Electron Devices, vol. 38, pp. 1289-1296, 199 1.

1111 K. K. Young, "Analysis of Conductance in Fully Depieted SOI MOSFET's," IEEE Tram. Ekctron Devices, vol. 36, pp. 504-506, 1989.

Department of Electricd and Computer Engineering, University of Toronto 60

Conclusions

Due to complete dielectric isolation, SOI CMOS technology offers simplified process,

enhanced performance and increased integration density, and is likely to becorne the

dominant technology for future generations of VLSI systems.

Partially depleted SOI devices are easier to manufacture but suffer €rom fioating body

effects. Fully depleted SOI has the advantage of no floating body effects and improved

performance, but requires very thin silicon films making manufacturing more challenging.

This thesis has targeted the development and implementation of a fully depleted A-

channel SOI NMOSFET in a thick SOI film. A new uiangular-channel SOI NMOSFET

structure was proposed. A CMOS-compatible process was developed to fabncate the

structure. Simulation results showed that the gate exhibits improved control over the

channel, and fully depleted device behavior, including excellent subthreshold

characteristics, absence of kink in the output charactenstics and enhanced current

drivability, were achieved.

The proposed fully depleted A-channel SOI NMOSFET structure was manufactured

and the experimental results demonstrated that the new structure successfully suppressed

ffoating body effects. The A-channel SOI NMOSFET exhibited a threshold voltage of 370

mV and an excellent subthreshold swing of 67 mvidecade. No kink was evident in the

output characteristics. Enhanced mobility, enhanced transconductance and current driving


capability, due to the bulk effective mobility in the channel, were observed. Fully depleted

SOI device behavior was obtained.

Aside from optirnization of the processing steps, future research work should include

high-frequency characterization of the device. A practical technique to predict the volume

mobility in the structure is also needed. Furthemore, systematic calibration of

implantation, difision and segregation models would bnng a closer agreement between

simulated and experimental results.


Layout Design Rule

The mask was designed based on the 0.8 pm minimum line width. imposed by the

fabrication facility at the University of Toronto. A total of 8 masks were used. The layout

design niles for a A-channel SOI NMOSFET are illustrated in Figure A. 1 and are presented

in Table A. 1.

GATE

Figure A. 1 Illustration of Layout Design Rules

Table A.1 Summary of Layout Design Rules

Layout Rule 1 # 1 Description Dimension l (/lm)

1st 1 1.2 1 Minimum spacing 1 1.1

- - - 1 1

/ Minimum clearance to ACïKE KGION 1 i 1 1.4 1 Minimum overhang of 2nd ETCHING 1

Minimum width

1 2.1 1 Minimum width 1

2

2nd ETCWING

A C T N E

2.2

2.3

2.4

REGION 3.1

4.1

1 5.1 1 Minimum width 1

Minimum spacing to 1st ETCHNG

Minimum spacing to ACTIVE REGION

Minimum spricing to GATE

3.2

GATE

2

2

2

Minimum width

t

Minimum width

10 1

0.8

4.2

4.3

S/D iMP

Minimum overlap of CONTACT1

6.1

2

Minimum overlap of CONTACTî

Minimum overhang of ACTNE REGION

5.2

CONTACT1 (on Sourcel

2

2

Minimum width

Drain)

CONTACT2

Minimum overlap of ACïTlE REGION

5

6.2

(on Gate)

2

6.3

7.1

I

8.1

Minimum spacing of 1st ETCHTNG

7.2

METAL

2

Minimum spacing to 2nd ETCHING

Minimum width

Minimum width

2

5

Minimum spacing of 2nd ETCHING (outside)

5

8 -2

2

Minimum overlap of CONTACT1 or CONTAC?=, 2

implementation fully depleted a-channel soi nmosfet and software problems. my appreciation extends...

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