implementation adaptive noise canceler

ASIC Implementation of Adaptive Noise Canceller

IMPLEMENTATION OF ADAPTIVE NOISE CANCELLER

UNDER THE GUIDANCE OF: PROFESSOR P.PRABHAVATI

B.N.M Institute of Technology Bangalore

BY: Akshatha Suresh

Bhaskar Ravishankar

Belur Prajwal Taranath Shetty

Bharath M.P

Department of ECE, BNMIT


LIST OF ACRONYMS

ANC Adaptive noise canceller

LMS Least mean square

SNR Signal to noise ratio

HDL Hardware description language

RTL Register transfer logic

FIR Finite impulse response

IIR Infinite impulse response

FSM Finite state machine

MAC Multiply and accumulate

RAM Random access memory

FC FSM Controller

DP RAM Dual port RAM

FIFO First in first out



LIST OF FIGURES

Figure 2.2: The basic block diagram of adaptive noise canceller

Figure 2.3: The behavioral model of the adaptive noise canceller

Figure 2.5: The simulation results for behavioral model

Figure 3.1: The primitive block diagram of FSM

Figure 3.2: The FSM

Figure 3.3: The functional units of FSM

Figure 3.4: The FPGA design flow

Figure 4.4.1: Adder Unit

Figure 4.4.2: Single Port RAM

Figure 4.4.3: The dual port RAM



Chapter-1

Introduction

1.1 Preamble

Acoustic problems in an environment has gained more attention due to the tremendous

growth of technology that lead to noisy engines, heavy machineries, pumps, air condition,

music and other noise sources. Normally human ears are very sensitive at audio range (lower

frequency) from 20 Hz to 20 kHz. So, any sound within these frequencies has the tendency to

disturb human hearing and can be classified as noise. The reduction of acoustic noise in

speech has been investigated for many Years .The major application of noise reduction is by

improving voice communication and eliminating the noise using adaptive noise canceller.

1.1 Problem Statement

In many areas of today's communication environments, we often encounter situations where

clarity and intelligibility of speech is impaired due to ubiquitous noise. Since speech has

always been one of the most important carriers of information for people it becomes a

challenge to maintain its high quality. It is therefore desirable that noise and, as a matter of

fact everything which is not pertinent to the speech information carried is canceled or

suppressed. In such situation, the approach of adaptive noise cancellation (ANC) is

applicable. ANC, also called noise reduction is one of such approach that has been proposed

for reduction of steady state noise. There are many algorithms that can be use for adaptive

filter in ANC, but the simplest and effective algorithm for the operation of adaptive filter is

least mean square (LMS) algorithm. The LMS algorithm is a stochastic gradient algorithm

that iterates each tap weight of a transversal filter in the direction of the gradient of mean

square error of an error signal. The LMS algorithm uses a fixed step size parameter to

control the correction applied to each tap weight from one iteration to the next. , a filter code

with least means square (LMS) algorithm using MATLAB is generated which is able to

eliminate or reduce periodic noise from input signal.



1.3 Objective of Study

The main objective of this project is:

● To obtain the SNRs of adaptive digital filters.

● To design and implement adaptive filter based noise canceller and related functional

blocks.

The above objectives include analysis of different performance parameters and a behavioral

simulation is done to analyze the performance of the proposed architecture using Simulink

available in MATLAB.

1.4 Scope

Acoustic problems in the environment have gained attention due to the tremendous growth of

technology that has led to noisy engines, heavy machinery, pumps, high speed wind buffeting

and a myriad other noise sources. The problem of controlling the noise level in the

environment has been the focus of a tremendous amount of research over the years. One of

the classical approaches to noise cancellation is passive noise reduction methods. Passive

silencing techniques such as sound absorption and isolation are inherently stable and

effective over a broad range of frequencies. However, these tend to be expensive, bulky and

generally ineffective for canceling noise at the lower frequencies. The performance of these

systems is also limited to a fixed structure and proves impractical in a number of situations.

The shortcomings of the passive noise reduction methods have given impetus to the

research and applications of alternate methods of controlling noise in the environment. This

led to the development of noise canceller using adaptive filter. It cancels the noise using

various algorithms among which one is the Least Mean Squared (LMS); The LMS class of

algorithms provides a robust and computationally acceptable option for most of the

applications. Most of the research in the area of adaptive filters today is performed on the

LMS class of algorithms.



Compared to traditional digital filters, adaptive filters have the following advantages:

● Additional signal processing tasks. For example, adaptive filters can be used to remove

noise that traditional digital filters cannot remove, such as noise whose power

spectrum changes over time.

● Some real-time or online modeling tasks. For example, adaptive filters can be used to

identify an unknown system online mode. Typically, adaptive filters are useful when you

perform real-time or online signal processing applications.

● Conceptual and computational simplicity.

The above advantages help in overcoming many problems and thus are widely used in

various applications.

1.5 MethodologyThe implementation of the proposed ANC begins with:

● Modeling using Simulink available in MATLAB 7.5 (r2008a). Simulink is an

environment for multidomain simulation and Model-Based Design for dynamic and

embedded systems. It provides an interactive graphical environment and a

customizable set of block libraries that let us design, simulate, implement, and test a

variety of time-varying systems, including communications, controls, signal

processing, video processing, and image processing.

● The resulting filter coefficients are then used for implementation.

● Implementation of ANC using adaptive filters is done by making use of Xilinx ISE.

Xilinx ISE is a software tool produced by Xilinx for synthesis and analysis of HDL

designs, which enables the developer to synthesize their designs, perform timing

analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and

configure the target device with the program.



1.6 Report organization

This dissertation covers a detailed analysis of implementation of Adaptive Noise Canceller.

The remaining dissertation is as follows:-

The chapter 2 includes the noise canceller primitives and the basic implementation of the

adaptive noise canceller and the detailed analysis of the LMS algorithm. The analysis is also

extended by constructing a behavioral model of the ANC with the appropriate specifications

and the simulation results were obtained.

The chapter 3 describes the basic idea of the implementation of the modeling done and also

includes the detailed analysis of the FSM and its functional units. it includes the details of the

tools used for the implementation of the model.

The chapter 4 includes the RTL of individual blocks of the FSM, conclusion and the future

scope of the Adaptive noise cancellers.



Chapter 2

Noise Canceller

2.1 Noise cancellation primitives:

The use of adaptive filters for reducing the noise content is based on the assumption that the

justified for the case in which the background noise is continuous and the event is transient.

The transient behavior implies that the frequency content of the event shall be spread out

over many frequency bins due to its impulsive temporal characteristics. Additionally, for

many sources of background noise, the spectral content is quite low. The frequency

components for these sources can be isolated and matched to appropriately tuned FIR or IIR

filter banks to reduce their amplitude but the problems is stability and convergence . The feed

forward variety (FIR) formulations offer a higher degree of stability but typically require

many more taps to realize a given frequency response.

2.2 Noise Canceller

The block diagram of an adaptive noise canceller is as shown in the next page:

Primary p (k) system output e (k) Signal of interest



Plus interference

W(k)

Reference x (k) Attained version of Filter output y (k) Interfering signal Estimate of interference Seen at primary input

Error e (k)

Fig 2.2 Basic block diagram of Adaptive Noise Canceller

● The ANC has two inputs and a single output.

● The primary input p (k) contains the signal of interest plus one or more interfering

signals.

● The second input, termed the reference input x (k), is applied to the input of the

adaptive filter. This reference input should be as rich as possible in the signals

interfering with the signal of interest and should contain as little of the signal of

interest as possible.

● The objective in adapting the coefficients of the filter is to produce a filter output y

(k) that matches, to the greatest extent possible, the exact wave shape of the

interference signals appearing in the primary input.

● The filter output is subtracted from the primary input to produce the system output e

(k).

● If the filter can be adjusted to achieve a perfect match between the filter output and

the interference present in the primary signal, then the system output contains only

the signal of interest. To the extent that filters cannot be so adjusted, then certain

amount of the interference remains.



● The ANC uses the system output e (k) as the error signal to drive the filter’s

adaptation. When the filter’s coefficients are optimally adjusted, the presence of the

interference in the error is minimized. By using an adaptive algorithm that minimizes

the presence of the interference, the best coefficients can be found.

● The most commonly used adaptive algorithm is least mean squared (LMS) algorithm.

2.1.1 LMS Adaptation algorithm In order to determine an optimal set of filter parameters w (weight coefficient ) for the

minimization of the error signal, we consider the filter output y(n) of a filter of order M-1 for

the sample index n.

y (n) = wT (n) u (n) (2.1)

Where u (n) is the vector of the M most recent input samples at sampling point n,

u (n) = [ u(n),u(n-1),…… u(n-M+1)] (2.2)

And w (n) is the tap-weight vector of filter coefficients.

w (n) = [w0 (n), w1 (n),……. wM-1(n)] (2.3)

The error signal is given by comparing this output with the primary signal d (n) which is the

superposition of noise signal s (n) and the wanted signal n (n), we get estimation error as

e (n) = d (n) – y (n) (2.4)

and for the squared error we get,

e2 (n) = d2(n) – 2 d(n)u T(n) w(n) + wT (n) u(n) uT(n) w(n) (2.5)



The method require the use of a gradient vector, whose value depends on two parameters R

& P

VJ (n) = -2 P + 2R w (n) (2.6)

where R is the autocorrelation matrix of u (n), and P is the cross correlation matrix of d (n)

and u (n).

The instantaneous estimates for R and P respectively

Rˆ (n) = u (n) u H (n) (2.7)

Pˆ (n) = u (n) d* (n) (2.8)

Minimizing the expectation value of e2 in eq. (2.5) under the assumption of a stationary and

zero-mean reference signal u (n) finally leads to the Wiener-Hopf equation

Wopt= R-1P (2.9)

This is the Condition for Optimal FIR Parameters.

The Wiener-Hopf equation (2.9) is not directly suitable for real-time embedded applications,

because R and p are neither known in advance, nor are they time-invariant. In addition, the

inversion of R is time-consuming for higher filter orders. The Widrow-Hoff Least Mean-

Squared (LMS) algorithm [2] provides a means of calculating wopt without the need of

knowing R and P, and without performing a matrix inversion. In this algorithm the target

function for the minimization is the running average of the squared error signal (e2) instead of

the expectation value E {e2}. In an iterative way the next FIR coefficient set w (M+1) is

computed from the values at step n. A factor μ is introduced to control the step width of the

iteration and thus the speed of convergence of the algorithm [4, 5]. Stability bound on μ of

LMS algorithm

0 < μ < (2 / (M x Smax)) (2.10)



Where , Smax is the max value of Power Spectral Density of tap inputs and M is Filter length.

A new recursive relation for updating the tap weight vector is given by

w (n+1) = w (n) + μ ∆ e 2(n) (2.11)

with equation (2.4) we get

w (n+1) = w (n) + 2 μ u (n) e(n) (2.12)

2.3 Behavioral simulation

Simulink is an environment for multidomain simulation and Model-Based Design for

dynamic and embedded systems. It provides an interactive graphical environment and

a customizable set of block libraries that let us design, simulate, implement, and test a

variety of time-varying systems, including communications, controls, signal

processing, video processing, and image processing.



Figure 2.3: Behavioral model of ANC

2.4 Parameters:

We set the LMS Filter block parameters to model the output of the

Digital Filter Design block. Set of block parameters are as follows:

● Algorithm = Normalized LMS

● Filter length = 32

● Specify step size via = Dialog

● Step size (µ) = 0.0285

● Leakage factor (0 to 1) = 1.0

● Initial value of filter weights = 0

● Clear the Adapt port check box.

● Reset port = None


http://www.kxcad.net/cae_MATLAB/toolbox/dspblks/gs/f7-6281.html




Based on these parameters, the LMS Filter block computes the filter weights using the

normalized LMS equations. The Step size (µ) parameter defines the granularity of the filter

update steps. Because the Leakage factor (0 to 1) parameter is set to 1.0, the current filter

coefficient values depend on the filter's initial conditions and all of the previous input values.

The initial value of the filter weights (coefficients) is zero. Since we selected the Output filter

weights check box, the Wts port appears on the block. The block outputs the filter weights

from this port.

2.5 Modeling Results

The simulation results are as shown below:

Figure 2.5: Simulation results of the behavioral model



Figure 2.6 : Simulation results of the behavioral model

● The input signal is a sinusoidal signal with amplitude 1v and frequency 1kHz

● The reference signal is the noise

● Adaptation process in order to remove the noise

● The noise eliminated signal is obtained



Chapter -3

Finite State Machine

3.1 FSM Implementation

Fig 3.1 Primitive Block Diagram

The basic block diagram for the implementation of the adaptive noise canceller model is as

shown above. The functions of each block are as follows:-

● The input signal is an analog signal and has to be converted into digital in order to

process it thus an ADC is used at the input



● The signal that is processed is given to the DAC in order to convert the digital signal

back to the analog form

● It also consists of a processor that does the normal FIR and MAC operation

● The memory is required in order to store the coefficients obtained

● The FSM block produces the control signal for each of the block connected to it

As digital circuit elements decrease in physical size, resulting in increasingly complex

systems, a basic logic model that can be used in the control and design of a range of

semiconductor devices is vital. Finite State Machines (FSM) have numerous advantages; they

can be applied to many areas (including motor control, and signal and serial data

identification to name a few) and they use less logic than their alternatives, leading to the

development of faster digital hardware systems.



The FSM used here is as shown in the figure 3.2 :

Fig 3.2 Finite State Machine

The FSM shown in the previous page has 5 states which are as follows:-

1. IDLE :a. Signals active:

i. men - master enable

ii. clr_reg – clear registers



b. Operation:

Here, no operations take place. The ANC system does not perform any

action apart from clearing the registers and resetting the counters of

the RAMs to the starting address. If the men is at 0, the FSM

Controller (FC) remains in IDLE state. If men is set, the FC moves to

the next state.

2. EMUL :

a. Signals active:

i. req0 – request 0

ii. en_reg_emue – error multiplication enable register

b. Operation:

The FC provides the signal for the register to hold the multiplied value

of the error signal e (n) and the step size µ (mu). The error signal is a

16 bit random number sequence. Step size µ is a real number which is

determined by trial and error method in Simulink. The value of this

used here is 0.0285. This happens for every iteration and is essential in

adjusting the coefficients for the progressive cancellation of the noise

at the input. This output of the above multiplication is a 32 bit number.

It is stored in the error multiplication register (reg_emue) and is given

to the next state once the req0 signal goes high.

3. MAC_WRITE :

a. Signals active:


ii. status – status of the counter

iii. en_reg_y – output [y(n)] register enable

iv. en_cnt_cr – enable count coefficient read

v. en_cnt_cw – enable count coefficient write



vi. we_r_c – write enable RAM coefficient

vii. we_r_s – write enable RAM sample

b. Operation:

There are a number of control signals involved in this state. Also, the

input samples x(n) are considered. Each input sample is a 16 bit

number. The output of reg_emue is rounded off only to 16 bits and is

given as one of the inputs to the next multiplication block. The number

of coefficients chosen is 32 as the number of filter taps. Hence all the

address counters have a maximum count of 32 and they are 5 bit

counters.

There are a number of operations that take place in this state:-

i. The output of error multiplication register is a 32 bit number.

This output is rounded off to 16 bits. This number is multiplied

with the delayed input x(n) and the output is a 32 bit number.

ii. The output of the above multiplication is again rounded off to

16 bits. This number is added with the previous coefficient

w(n) to give the next coefficient w(n+1)

iii. The above output is stored (written) back to the Dual Port

RAM for future use

iv. Meanwhile, the actual input x(n) is multiplied with the updated

coefficient w(n)

v. The above output is added with the system output feedback

y(n) before saturation with the help of register enable signal

vi. For all the above operations, the address counters are essential

and their pointers are periodically updated to the next memory

location after each successful FIR and LMS MAC operation

Hence this state has a number of dedicated control signals for each of

the above operations that are carried out. Once the operations are

completed, the status signal is set which indicates the FC to go to the

next state.



4. STOP :

a. Signals active:


ii. en_cnt_cr - enable count coefficient read

iii. status - status of the counter

b. Operation:

This state is only attained by the system after every successful

MAC_WRITE operation i.e. when the input signal is filtered with a set

of coefficients. In this state, the coefficient read counter of the Dual

Port RAM resets to zero and hence the coefficient read pointer now

points to the initial location. If the req1 signal is not set, the FC

remains in the same state, else it changes to the next state. There is no

real operation happening in this state.

5. UPDATE :

a. Signals active:

i. en_sat – enable saturation logic

ii. req1 – request 1

iii. en_cnt_cw - enable count coefficient read

iv. men – master enable

v. req2 – request 2

b. Operation:

Once the coefficient read pointer resets to the initial location, the req1

signal is made high and this state is attained. Here, the coefficient-

write counter resets and the corresponding pointer resets to the initial

location. Also, the saturation logic unit operates here. In this unit, the

system output y (n) obtained from the output register will be limited to

the MSBs and the LSBs are discarded. In doing so, the error occurring



due the arithmetic operations i.e. multiplication and addition are

minimized.

This operation is completed and the req2 signal is made high. The

update state is the last state stained by the FC during the course of one

full cycle of operation. Once this state is attained, the main counter

increments its count by one and checks whether the maximum count

limit reached. If so, the men signal is set and the FC goes to IDLE

state wherein all the registers and the memory blocks are cleared.

3.2 Functional Units of the ANC System

The ANC is a versatile system with the ability to cancel noise progressively and to a greater

extent without the use of more than one filter. Here, the LMS algorithm is used along with

the FIR filter which together form the Adaptive Filter system. The FSM Controller (FC) is

the brain of the system controlling the actions of various functional blocks present in the

system. The functional units are represented in the block diagram as shown:-

Fig 3.3 Functional units



Each block here is equipped suitably to execute a specific function and there are control

signals from the FC which constantly monitor the functionality of these blocks. Each of these

blocks is defined in the verilog HDL as modules which are mapped onto the FPGA suitably.

There are various blocks in the diagram which are described as follows:-

1. FSM CONTROLLER (FC)

This unit is the Control unit of the system. All activities of the system are

controlled by this unit. The storage of coefficients and input samples in the

RAMs, multiplication, addition and updating the count of the address counters

are the functions that are controlled by this unit. The FC has various control

signals associated with it. These control signals are specifically assigned to

various blocks in the system as seen clearly in the block diagram. Each one of

these signals is updated periodically as per the FSM flow. Thus a smooth

transition of states is ensured by the FC. In each of the states, only few

signals are active.

2. MULTIPLIER

This unit is a simple multiplier which performs multiplication of two 16-bit

numbers. There are 2 multiplier blocks in the system.

● LMS Multiplier

This block is used to multiply the step size µ and the error

signal e(n). The multiplication results in a 32-bit number which

is further stored in the error register, reg_emue. This number is

rounded off to a 16 bit number and again multiplied with the

delayed input sample x(n). This output is added with the

previous coefficient to obtain the latest coefficient. This again

is a 17-bit number.

● FIR Multiplier

This block is used for the normal FIR operation i.e. the

multiplication of the input sample set x(n) and the filter



coefficient set w(n). The output thus obtained is the 32-bit

output y(n).

3. ADDERThis block is a simple adder which adds 2 numbers of 16 bits. There are 2

adder blocks in the system. One of the adders performs the addition of the

LMS multiplier output and stored coefficient to give the updated coefficient..

The other adder is present in the FIR block. This block performs the addition

of the FIR Multiplier output and the feedback system output y(n).

4. SATURATION LOGICAs the name indicates, this block performs saturation of the system output

y(n). This process is essential for the system to prevent the overflow error of

the system output. The input to this block is a 40-bit number which is given

from the output register. The saturation logic operates by right shifting this

40-bit number by 24 places. Hence the more significant 16 bits of the output

are retained. The place value of these bits matter more than those of the lesser

significant bits. Hence the error at the output is minimized.

5. SINGLE PORT RAMThis RAM is used to store the delayed input samples x(n) and also the current

input samples. The delayed samples are used in the LMS multiplication to

update the coefficients for every iteration. The normal input samples are used

in the FIR multiplication operation to give the system output. The RAM used

here is a single port RAM. Here, either READ operation or WRITE operation

can happen at a single time but never both. Simultaneous accessing and also

writing new data is not possible. The RAM used here is of the type 16X32.

There are 32 input samples to be stored and each sample is of 16 bits. A



counter keeps track of the memory location that will be accessed at a given

time and hence the correct sample is chosen for access.

6. DUAL PORT RAMThe DP RAM block has advantages when compared to the single port RAM.

Here, there are two different address pointers each for READ and WRITE

operations. The configuration of this DP RAM is again 16X32. Here, at a

single instant of time, a coefficient can be read and another updated

coefficient can be written to 2 different memory locations of the RAM. Due to

this very advantage of simultaneous READ and WRITE facility, this RAM is

used to both store the updated coefficients and also read the coefficients for

the LMS MAC operation. This DP RAM has a FIFO structure i.e. the first

updated sample is written to the RAM for a particular cycle followed by later

updated samples. The sample is accessed first during the next cycle and hence

gets the name FIFO.

3.3 Algorithms of functional units

3.3.1 Adder algorithm

Step 1: Take two inputs of definite length.

Step 2: ADD two inputs.

Step 3: Store the result.

3.3.2 Multiplier algorithm

Step 1: Take two inputs of definite length.

Step 2: MULTIPLY two inputs.



Step 3: Store the result.

3.3.3 Multiplexer algorithm

Step 1: Here we are using 2:1 multiplexer.

Step 2: Initialize the required inputs to the input ports.

Step 3: Control the select input to pass the required input to the output.

3.3.4 DPRAM algorithm

Step 1: Initialize the RAM locations i.e., 64 locations of each 16 bits.

Step 2: Give the clock as input.

Step 3: Give the input data to data in port.

Step 4: Make write enable high to write the data to the RAM

Step 5: Make write enable low to read data from the RAM from the output port.

Step 6: Two different address pointers are used , one for write address and one for read

address.

Step 7: Use counters to update addresses of the DPRAM.

3.3.4 RAM algorithm

Step1: Initialize the RAM locations i.e., 64 locations of each 16 bits.

Step1: Give the clock as input.

Step2: Give the input data to data in port.



Step3: Make write enable high to write the data to the RAM

Step4: Make write enable low to read data from the RAM from the output port.

Step5: Address pointer is used and is incremented using counter.

3.3.5 Saturation Logic algorithm


Step2: Make control enable high to enable the saturation logic block.

Step3: Give the input to the input port.

Step4: Shift right the input bits by required number to retain the required MSBs of the input.

Step5: Obtain the result from the output port.

3.3.6 Counter algorithm


Step2: Select the number of bits required depending on the required count.

Step3: Here we are using 5 bits, as the required count is 32.

Step4: Make reset high to make the count as zero.



3.4 TOOLS USED IN OUR PROJECT-XILINX

3.4.1: XILINX 9.1i

Xilinx, Inc (NASDAQ: XLNX) is the world’s largest supplier of programmable logic

devices, the inventor of the Field Programmable Gate Array(FPGA) and the first

semiconductor company with a fables manufacturing model.

The features described below are most suited for our requirement, and hence Xilinx package

is used throughout to implement the adder structure on FPGA.

● FPGA Industry’s Most Complete Design Solution for Windows.

● Increased Productivity.

● Faster Timing Closure.

● Low Power Optimization

● Placement optimizations

● Usage of lower capacitance nets

● Power-aware logic optimization using Xilinx Synthesis Technology(XST)

The FPGA design flow is as shown below and features of ISE simulator is given in

the next section.



Fig 3.4 FPGA design flow

3.4.2: ISE Simulator

ISE simulator provides a complete. Fully featured HDL simulator integrated within

the ISEenvironment.ISE simulator comes in two versions. ISE simulator Lite is included at

no charge with all ISE configurations, providing an ideal solution for CPLD and low density

FPGA designs that is limited to 10,000 lines of HDL source code. The full ISE simulator

version supports any design density and available as a low cost-add-on option to ISE

foundation.

ISE controls all aspects of the design flow. Through the Project Navigator interface,

it gives access all of the design entry and design implementation tools. It also gives access to

the files and documents associated with our project.

3.5 Synthesis Results

3.5.1 AdderDevice utilization summary

Selected Device: 2vp30ff896-7

Number of Slices: 8 out of 13696 0%

Number of 4 input LUTs: 16 out of 27392 0%

Number of IOs: 49

Number of bonded IOBs: 49 out of 556 8%

IOB Flip Flops: 16



Number of GCLKs: 1 out of 16 6%

Saturation logic:



Number of Slice Flip Flops: 16 out of 27392 0%

Number of IOs: 58


IOB Flip Flops: 16


Timing Summary:

---------------

Speed Grade: -7

Minimum period: No path found

Minimum input arrival time before clock: 1.418ns

Maximum output required time after clock: 3.293ns

Maximum combinational path delay: No path found

Cell: in->out fanout Delay Delay Logical Name (Net Name)

---------------------------------------- ------------

IBUF:I->O 1 0.878 0.331 DISA_24_IBUF (DISA_24_IBUF)

FD:D 0.208 YN_0

----------------------------------------

Total 1.418ns (1.086ns logic, 0.331ns route) (76.6% logic, 23.4% route)

3.5.2 DP RAM:



HDL Synthesis Report

Macro Statistics

# RAMs : 1

32x16-bit dual-port RAM : 1

# Counters : 2

5-bit up counter : 2

# Registers : 3

16-bit register : 1

5-bit register : 2

Device utilization summary:





Number used as logic: 0

Number used as RAMs: 64

Number of IOs: 44



Timing Summary:

Speed Grade: -7

Minimum period: 2.109ns (Maximum Frequency: 474.271MHz)






3.5.3 Ram SamplesDevice utilization summary:





Number used as logic: 0

Number used as RAMs: 32

Number of IOs: 39



Timing Summary:

Speed Grade: -7

Minimum period: 2.109ns (Maximum Frequency: 474.271MHz)






Chapter 4

Simulation Results4.4.1 Adder Unit



4.4.2 Single Port RAM

4.4.3 Saturation Logic



4.4.4 Dual Port RAM



Conclusion and Future Scope

Adaptive Noise Cancellation is an alternative way of canceling noise present in a corrupted

signal. The principal advantage of the method is its adaptive capability, its low output noise,

and its low signal distortion. The adaptive capability allows the processing of inputs whose

properties are unknown and in some cases non-stationary. Output noise and signal distortion

are generally lower than can be achieved with conventional optimal filter configurations.

This Project indicates the wide range of applications in which Adaptive Noise Canceling can

be used. The simulation results verify the advantages of adaptive noise cancellation. In each

instance canceling was accomplished with little signal distortion even though the frequencies

of the signal and interference overlapped. Thus it establishes the usefulness of adaptive noise

cancellation techniques and its diverse applications.

Scope for Further Work

In this project, only the Least-Mean-Squares Algorithm has been used. Other adaptive

algorithms can be studied and their suitability for application to Adaptive Noise Cancellation

can be compared. Other algorithms that can be used include Recursive Least Squares,

Normalized LMS, Variable Step-size algorithm etc. Moreover, this project does not consider

the effect of finite-length filters and the causal approximation. The effects due to these

practical constraints can be studied.



Bibiliography1.

2. “Theory and Design of Adaptive Filters” by John R. Treichler, C. Richard Johnson,

Jr. Michael G. Larimore.

3. “Adaptive Filter Architectures for FPGA Implementation” by Joseph Petrone.

4. “Adaptive Filters” by Bernard Widrow.

5. “Adaptive Filter Theory” by Simon Haykin.


implementation adaptive noise canceler

Engineering