HighHigh--Performance Digital Performance Digital Integrated CircuitsIntegrated Circuits

Instructor: Mohab Anis

Course TopicsCourse TopicsLectures: Friday 9:30-12:30pm

Office hours: Friday 3-4pm (course and project)

Prerequisites: senior undergrad course on IC design (437,438) or a graduate course on IC design (637)

[1] J. Rabaey, A. Chandrakasan, B. Nikolic, Digital Integrated Circuits: A Design Perspective , 2nd Edition, Prentice Hall, 2003

[2] A. Chandrakasan, W. Bowhill, F. Fox, Design of High-Performance Microprocessor Circuits, IEEE Press, 2001.

[3] Selected journal and conference papers

* Most notes are adapted for the slides of the Rabaey book

Switching Power1) Low-Power Design Trade-offs2) Low switching power techniques and low-voltage techniques 3) Power Management concepts: dynamic supply voltage scaling (DVS), and dynamic threshold

scaling (DTS)Leakage Power1) Transistor leakage components2) Subthreshold leakage current – 1) transistor stack effect, 2) steady-state leakage model of

stacks 3) Leakage control techniques – 1) input vector activation, 2) dual-Vt design, 3) high -Vt

sleep transistors, 4) body biasing4) Impact of parameter variations

Weeks 8, 9, 10, 11,

12

Low Power Design

1) Synchronous Timing: 1) basics, 2) clock skew, 3) clock jitter2) Sources of skew and jitter: clock-signal generation, device variations,

interconnect variations, environmental variations, coupling capacitance3) Clock distribution techniques 4) Self-Timed Design5) Practical examples of Self-Timed Design

Weeks 6, 7

Timing Issues

1) Device, interconnect, supply voltage, and temperature variations2) Characterizing, modeling and addressing variations 3) Applications – clock distributions networks4) Managing parameter variations

Week 5

Parameter Variations

1) Interconnect Parameters – Capacitance, Resistance, and Inductance2) Electrical Wire Models – Ideal, Lumped, Lumped RC, Distributed RC,

and Transmission line3) Capacitive parasitics: Reliability – crosstalk, impact on delay and power4) Resistive parasitics: Reliability – ohmic voltage drop, electro-migration,

impact on delay5) Inductive parasitics: 1) inductance and reliability – Ldi/dt voltage drop, 2)

impact on delay6) Interconnect Techniques

Weeks 2, 3, 4

Interconnects / Signal Integrity Issues

1) Fundamental Design Criteria2) MOS Transistor: Operation, Static and dynamic behavior3) MOS and Interconnect Scaling theory

Week1

Introduction and the scaling of the MOS Transistor

Project TopicsProject Topics

Creditq Literature Survey – 20 referencesq Design project – 10-15 referencesq Clock Distribution and Design (accounting for skew/parameter variations)q Power Delivery Issuesq Design for variability (statistical design of ICs – timing/power)q Design for testability in DSM.q Physical Design – Placement/Floorplanningq Design for low power – dynamic/static (trade-offs)q Interconnect-aware design (design optimization/buffer insertion/retiming)q Very High speed design (optical communication circuits)q Ultra-low voltage/power design

Audit15 page project – Literature survey

What will you learn?What will you learn?

§ Understanding, designing, and optimizing digital circuits in the deep-submicron regime with respect to different quality metrics: cost, speed, power dissipation, and reliability

Introduction and MOSFET TransistorIntroduction and MOSFET Transistor

IntroductionIntroduction

qWhy is designing digital ICs different today than it was before?

qWill it change in future?

Intel 4004 MicroIntel 4004 Micro--Processor (1971)Processor (1971)

19711000 transistors1 MHz operationNMOS only replacing PMOS based integrated circuits (higher speed)

Intel Pentium (IV) microprocessor (2000)Intel Pentium (IV) microprocessor (2000)

In the early 1970s, CMOS technology replaced NMOS-only logic which started suffering from high power consumption. Ever since, CMOS has been the dominant digital technology. Interestingly enough, power consumption concerns are rapidly becoming dominant in CMOS designs as well, and this time there does not seem to be a new technology around the corner to alleviate this problem.

Issues in Digital IC Design Issues in Digital IC Design -- Moore’s LawMoore’s LawlIn 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months. He made a prediction that semiconductor technology will double its effectiveness every 18 months (# of transistors that can be integrated on a single die would grow exponentially with time).

1 61 51 41 31 21 11 0

9876543210

1959

1960

1961

1962

1963

1964

1965

1966

1967

1968

1969

1970

1971

1972

1973

1974

1975

LO

G2

OF

TH

E N

UM

BE

R O

F

CO

MP

ON

EN

TS

PE

R IN

TE

GR

AT

ED

FU

NC

TIO

N

Electronics, April 19, 1965.

Transistor CountsTransistor Counts

Courtesy, Intel

An intriguing case study is offered by the microprocessor. From its inception in theearly seventies, the microprocessor has grown in performance and complexity at a steadyand predictable pace. The number of transistors and the clock frequency for a number oflandmark designs are collected in Figure 1.3. The million-transistor/chip barrier wascrossed in the late eighties. Clock frequencies double every three years and have reached

40048008

80808085 8086

286386

486Pentium® proc

P6

0.001

0.01

0.1

1

10

100

1000

1970 1980 1990 2000 2010Year

Tra

nsi

sto

rs (

MT

) 2X growth in 1.96 years!

Transistors on Lead Microprocessors double every 2 yearsTransistors on Lead Microprocessors double every 2 years

Die Size GrowthDie Size Growth

40048008

80808085

8086286

386486 Pentium ® proc

P6

1

10

100

1970 1980 1990 2000 2010Year

Die

siz

e (m

m)

~7% growth per year~2X growth in 10 years

Die size grows by 14% to satisfy Moore’s LawDie size grows by 14% to satisfy Moore’s Law

Courtesy, Intel

FrequencyFrequency

P6Pentium ® proc

48638628680868085

8080800840040.1

1

10

100

1000

10000

1970 1980 1990 2000 2010Year

Fre

qu

ency

(M

hz)

Lead Microprocessors frequency doubles every 2 yearsLead Microprocessors frequency doubles every 2 years

Doubles every2 years

Courtesy, Intel

Clock frequencies doubled every 3 years in the past decade and have reached the GHz range.

This trend has not shown any signs of a slowdown.

Impact on Design => Hierarchical approachImpact on Design => Hierarchical approachCustom/HandcraftedThis revolution has had a profound impact on how digital circuits are designed. Early designs were truly hand-crafted. Every transistor was laid out and optimized individually and carefully fitted into its environment, for example the design of the Intel 4004 microprocessor. This approach is, obviously, not appropriate when more than a million devices have to be created and assembled. With the rapid evolution of the design technology, time-to-market is one of the crucial factors in the ultimate success of a component.

HierarchicalDesigners have, therefore, increasingly adhered to rigid design methodologies and strategies that are more amenable to design automation. The impact of this approach is apparent from the layout of one of the later Intel microprocessors, the Pentium IV. Instead of the individualized approach of the earlier designs, a circuit is constructed in a hierarchical way: a processor is a collection of modules, each of which consists of a number of cells on its own. Cells are reused as much as possible to reduce the design effort and to enhance the chances for a first-time-right implementation. The fact that this hierarchical approach is at all possible is the key ingredient for the success of digital circuit design and also explains why, for instance, very large scale analog design has never caught on.

Design Abstraction LevelsDesign Abstraction Levels

n+n+S

GD

+

DEVICE

CIRCUIT

GATE

MODULE

SYSTEM

Question: Why hierarchal design approach is feasible in digital world and not in analog designs?

Answer: Abstraction ! At each design level, the internal details of a complex module can be abstracted away and replaced by a black box view or model. This model contains virtually all the information needed to dealwith the block at the next level of hierarchy. For instance, once a designer has implemented a multiplier module, its performance can be defined very accurately and can be captured in a model. The performance of this multiplier is in general only marginally influenced by the way it is utilized in a larger system. For all purposes, it can hence be considered a black box with known characteristics. As there exists no compelling need for the system designer to look inside this box, design complexity is substantially reduced.

(Analogous to to a library of software routines)

Cell libraries: contain complete documentation and characterization of the behavior of the cells. Typically stacked in rows and interconnected by routing channels.

This abstraction facilitated the design of Computer-aided frameworks for digital ICs

Concerns Concerns Question: CAD tools effectively address some complexity issues incurred in digital design. If that’s the case, why should we be concerned about digital design at all ?

Answer: The reality is more complex!1) Module libraries still have to be designed and implemented with every advancement in technology. 2) For high-performance modules in microprocessors, technology needs to be pushed to its limits, making the hierarchical approach less attractive. 3) The performance of certain blocks can be substantially influenced by the way it is connected in its environment. Interconnection wires contribute to delay (parasitics), which is bound to increase as technology scales (will be discussed later in more detail). 4) Increasing the size of the digital design has a profound effect on global signals such as clock and supply lines. For example, connecting more cells to a supply line can cause voltage drop over the wire, which in turn slows down all the connected cells. Clock and power distribution and circuit synchronization are becoming more and more critical. 5) New design issues emerge as technology scales, such as power dissipation and the changing ratio between device and interconnect parasitics. Thus, accurate modeling and analysis is needed. 6) Variations can significantly alter the performance of ICs.

Example Example –– Power Distribution NetworksPower Distribution NetworksThe resistive nature of on-chip wires and the inductance of the IC package pins make this adifficult proposition. For example, the average DC current to be supplied to a 100W-1V microprocessor equals 100A! The peak current can be twice as large, and the current demand can change from 0 to this peak in 1nsec or less, leading to current variation of 100GA/sec!

For a current of 100A, a wire resistance of 1.25mΩ leads to a 5% drop in Vdd for Vdd=2.5V. Making the wires wider reduces the resistance and thus voltage drop, but at expense of area.

A B

A B

Routing through the block (larger IR drop occurs in Block B)

Routing around the block ( low IR drop occurs in Block B, but at expense of extra area)

The large metal trunks of power have to be sized to handle all current of each block. Thus, designers set aside area for power rails that take awayFrom available routing area.

As more blocks are added, the complexInteraction between these blocks determineThe actual voltage drops (simultaneous Peaks, current direction)

Design MetricsDesign Metrics

q How to evaluate performance of a digital circuit (gate, block, …)?§ Reliability§ Scalability§ Speed (delay, operating frequency) § Power dissipation§ Energy to perform a functionDepending on the application, more significance is

given to one design criterion over another.

ReliabilityReliability?? VariabilityVariability and Noise in Digital ICsand Noise in Digital ICsVariability - The dimensions and device parameters vary on a single wafer or die.Noise – Unwanted variation of voltage and currents at the logic nodes.

i(t)

Inductive coupling(mutual inductance)

Capacitive coupling(coupling capacitor)

Power and groundnoise

v(t) VDD

A change in voltage or current on one of the wires can influence the signals on the neighboring wire.

Internally generated noise: capacitive and inductive crosstalk, and internally generated power supply noise (as % of signal/power level).Externally generated noise: Input power supply noise (in V or A)

DC OperationDC OperationVoltage Transfer CharacteristicVoltage Transfer Characteristic

Vin

Vout

‘1’ = VOH

‘0’ = VOL

VM

VIHVIL

fVout=Vin

Switching Threshold: midpoint of switching characteristics

Nominal Voltage Levels

VOH = f(VOL)VOL = f(VOH)VM = f(VM)

Noise Margins Noise Margins –– A measure of the A measure of the sensitivity of a gate to noisesensitivity of a gate to noise

Noise margin high

Noise margin low

VIH

VIL

UndefinedRegion

"1"

"0"

VOH

VOL

NMH

NML

Gate Output Gate Input

The noise margins represent the levels of noise that can be sustained when gates are cascaded.

Power DissipationPower Dissipation

Instantaneous power: p(t) = v(t)i(t) = Vsupplyi(t)

Peak power (supply line sizings): Ppeak = Vsupplyipeak

Average power (cooling and battery requirements):

( )∫ ∫+ +

==Tt

t

Tt

t supplysupply

ave dttiT

Vdttp

TP )(

1

The power consumption of a design determines how much energy is consumed per operation,and how much heat the circuit dissipates. These factors influence a great number of criticaldesign decisions, such as the power-supply capacity, the battery lifetime, supply-linesizing, packaging and cooling requirements. Therefore, power dissipation is an importantproperty of a design that affects feasibility, cost, and reliability. In the world of high-performancecomputing, power consumption limits, dictated by the chip package and the heatremoval system, determine the number of circuits that can be integrated onto a single chip,and how fast they are allowed to switch. With the increasing popularity of mobile and distributedcomputation, energy limitations put a firm restriction on the number of computationsthat can be performed given a minimum time between battery recharges.

Power DissipationPower Dissipation

P6Pentium ® proc

486

3862868086

80858080

80084004

0.1

1

10

100

1971 1974 1978 1985 1992 2000Year

Po

wer

(W

atts

)

Lead Microprocessors power continues to increaseLead Microprocessors power continues to increase

Courtesy, Intel

Power will be a major problemPower will be a major problem

5KW 18KW

1.5KW 500W

40048008

80808085

8086286

386486

Pentium® proc

0.1

1

10

100

1000

10000

100000

1971 1974 1978 1985 1992 2000 2004 2008Year

Po

wer

(W

atts

)

Power delivery and dissipation will be prohibitivePower delivery and dissipation will be prohibitive

Courtesy, Intel

Power densityPower density

400480088080

8085

8086

286 386486

Pentium® procP6

1

10

100

1000

10000

1970 1980 1990 2000 2010Year

Po

wer

Den

sity

(W

/cm

2)

Hot Plate

NuclearReactor

RocketNozzle

Power density too high to keep junctions at low tempPower density too high to keep junctions at low temp

Courtesy, Intel

Not Only MicroprocessorsNot Only Microprocessors

Digital Cellular Market(Phones Shipped)

1996 1997 1998 1999 2000

Units 48M 86M 162M 260M 435M Analog Baseband

Digital Baseband

(DSP + MCU)

PowerManagement

Small Signal RF

PowerRF

(data from Texas Instruments)(data from Texas Instruments)

CellPhone

Challenges in Digital DesignChallenges in Digital Design

“Microscopic Problems”• Ultra-high speed design• Interconnect• Noise, Crosstalk• Reliability, Manufacturability• Power Dissipation• Clock distribution.

Everything Looks a Little Different

“Macroscopic Issues”• Time-to-Market• Millions of Gates• High-Level Abstractions• Reuse & IP: Portability• Predictability• etc.

…and There’s a Lot of Them!

?

SummarySummary

q Digital integrated circuits have come a long way and still have quite some potential left for the coming decades

q Some interesting challenges ahead§ Getting a clear perspective on the challenges and

potential solutions is the purpose of this course

q Understanding the design metrics that govern digital design is crucial§ Reliability, speed, power and energy dissipation

The MOSFETThe MOSFET

What is an MOS Transistor?What is an MOS Transistor?

VGS ≥ VT

RonS D

A Switch!

|VGS|

An MOS Transistor

When the voltage applied to the gate is larger than VT, a conducting channel is formed between the drain and source. In the presence of a voltage difference between D & S, electrical current flows between them. When the gate voltage is lower than the threshold, no channel exists, and the switch is considered open.

Very few parasitic effects, high integration density, relatively simple manufacturing process

Threshold Voltage: ConceptThreshold Voltage: Concept

n+n+

p-substrate

DSG

B

VGS

+

-

DepletionRegion

n-channel

The Threshold Voltage The Threshold Voltage –– Body EffectBody Effect

- 2 . 5 - 2 - 1 . 5 - 1 - 0 . 5 00 . 4

0 . 4 5

0 . 5

0 . 5 5

0 . 6

0 . 6 5

0 . 7

0 . 7 5

0 . 8

0 . 8 5

0 . 9

VB S

( V )

VT

(V

)

VT is the VGS value where strong inversion occurs.Note that VBS should never exceed 0.6V, otherwise the source-body becomes forward biased, which deteriorates the transistor’s operation

( )FSBFTT VVV Φ−+Φ−+= 220 γ

Function in manufacturing process (oxide thickness, fermi voltage, ion implants)

Transistor in LinearTransistor in Linear

n+n+

p-substrate

D

SG

B

VGS

xL

V(x) +–

VDS

ID

With VGS>VT, and a small VDS is applied, a current ID flows from the drain to source.Using simple analysis, a first order expression of ID is obtained.

For small VDS values, the MOS acts as a resistor ( )

−−=

2

2

DSDSTGSnD

VVVV

LW

kI

( )TGSn

DS

VVL

Wk

R−

=1

Transistor in SaturationTransistor in Saturation

n +n +

S

G

V G S

D

V D S > V G S - V T

V G S - V T+-

Pinch-offWith VGS>VT, and a larger VDS applied, the channel thickness gradually is reduced from sourceto drain until pinch-off occurs (channel depth depends on the voltage from G to channel). This occurs when pinch-off condition meets the drain region,

and current remains constant

TDSGS VVV ≤−

( )2

2 TGSn

D VVL

WkI −=

CurrentCurrent--Voltage RelationsVoltage RelationsA good A good olol’ transistor’ transistor

QuadraticRelationship

0 0.5 1 1.5 2 2.50

1

2

3

4

5

6x 10

-4

VDS (V)

I D(A

)VGS= 2.5 V

VGS= 2.0 V

VGS= 1.5 V

VGS= 1.0 V

Resistive Saturation

VDS = VGS - VT

ChannelChannel--Length ModulationLength Modulation

Equation suggests that the transistor in the

saturation mode acts as a perfect current source. This is not entirely correct. The effective length of the conductive channel is modulated by the applied VDS: increasing VDS causes the depletion region at the drain to grow, reducing the length of the effective channel.

λ is the channel-length modulation ∝ 1/L

In short channels, the drain-junction depletion region presents a larger fraction of the channel, and the channel-modulation effect is more pronounced. That’s why long channel transistors are used when high-impedance current sources are designed.

( )2

2 TGSn

D VVL

WkI −=

( ) ( )DSTGSn

D VVVL

WkI λ+−= 1

22

Velocity Saturation in short channel devicesVelocity Saturation in short channel devices

ξ (V/µm)ξc= 1.5

υn

(m/s

)

υsat= 105

Constant mobility (slope = µ)

Constant velocity

The behavior of transistors with very short channel lengths deviates considerably from the resistive and saturation models just presented, mainly due to the velocity saturation effect.

Equation states that the carrier velocity is proportional to the electrical field, where the carrier

mobility is constant. However, at high (horizontal) field strengths, the carriers fail to follow this linear model. When the electrical field along the channel reaches a critical value ξC, the velocity of the carriers tend to saturate due to scattering effects (collisions suffered by the carriers). For a ξC = 1.5V/µm, 0.5V is required for velocity saturation in a 0.25µm device. This conditionIs very easily met in contemporary short-channeldevices.

This phenomenon has a profound impact on the operation of the device. This is illustrated with a first-order derivation of the device characteristicsUnder velocity saturation. The velocity can be roughlyapproximated by:

for ξ ≤ ξC

= νsat for ξ ≥ ξC

dxdV

nn µυ =

C

nn ξξ

ξµυ

/1+=

Velocity SaturationVelocity Saturation

( ) ( )DSDS

DSTGSnD VV

VVVL

WkI Κ

−−=

2

2

In the resistive region, the drain current can be expressed as:

The Κ(V) factor measures the degree of velocity saturation and is defined as

ξC=2γsat/µnΚ(V) = 1 for long channels or small VDS values. For short channels, Κ is less than 1, which means that the delivered current is less than what would normally be expected.

When increasing VDS, the electrical field in the channel ultimately reaches the cri tical value, and the carriers at the drain become velocity saturated. The saturation drain voltage VDSAT can be calculated by equating the current at the drain under saturation conditions to the resistive current for VDS=VDSAT.

We get

( )LVV

Cξ/11

)(+

=Κ

( )DSATTGSoxsatDSAT VVVWCI −−=ν

( )

−−Κ=

2)(

2DSAT

DSATTGSoxnDSAT

VVVV

LW

CV µ

Velocity SaturationVelocity SaturationIncreasing the drain-source voltage does not yield more current, and the transistor current saturates at IDSAT. This leads to two observations:

1) For a short-channel device and for large enough values of VGS-VT, Κ(VGS-VT) is substantially less than 1, and thus VDSAT<VGS-VT. The device enters saturation before VDS reaches VGS-VT. Short-channel devices therefore experience an extended saturation region, and tend to operate more often in saturation conditions that long-channels.

2) The saturation current IDSAT displays a linear dependence with respect to VGS, which is in contrast with the squared dependence in the long-channel device. This reduces the amount of current a transistor can deliver for a given control voltage

IDLong-channel device

Short-channel device

VDSVDSAT VGS- VT

VGS = VDD

CurrentCurrent--Voltage RelationsVoltage RelationsThe DeepThe Deep--Submicron EraSubmicron Era

LinearRelationship

-4

VDS (V)0 0.5 1 1.5 2 2.5

0

0.5

1

1.5

2

2.5x 10

I D(A

)

VGS= 2.5 V

VGS= 2.0 V

VGS= 1.5 V

VGS= 1.0 V

Early Saturation

IIDD versus Vversus VDSDS

-4

VDS(V)0 0.5 1 1.5 2 2.5

0

0.5

1

1.5

2

2.5x 10

I D(A

)

VGS= 2.5 V

VGS= 2.0 V

VGS= 1.5 V

VGS= 1.0 V

0 0.5 1 1.5 2 2.50

1

2

3

4

5

6x 10

-4

VDS(V)

I D(A

)

VGS= 2.5 V

VGS= 2.0 V

VGS= 1.5 V

VGS= 1.0 V

Resistive Saturation

VDS = VGS - VT

Long Channel (quadratic dependency bet. ID and VGS) Short Channel (linear dependency bet. ID and VGS, and small VDSAT )

Same technology, and identical W/L ratio

Velocity saturation

IIDD versus Vversus VGSGS

0 0.5 1 1.5 2 2.50

1

2

3

4

5

6x 10

-4

VGS(V)

I D(A

)

0 0.5 1 1.5 2 2.50

0.5

1

1.5

2

2.5x 10-4

VGS(V)

I D(A

)

quadratic

quadratic

linear

Long Channel Short Channel

Saturated devices (VDS=2.5V): Same technology, and identical W/L ratio

The SubThe Sub--Micron MOS Transistor Micron MOS Transistor --

qSubthreshold ConductionqThreshold VariationsqParasitic Resistances

SubthresholdSubthreshold ConductionConductionCurrent does not drop abruptly to 0 at VGS=VT. The device is partly conducting -> subthreshold conduction or weak-inversion conduction. Current decays in an exponential fashion for VGS< VT (similar to a bipolar transistor – in essence, in the absence of a conducting channel, the n+ (source)-p (bulk)-n+ (drain) terminals actually form a parasitic bipolar transistor. The current in this region is approximated by:

( )DSqkT

VqnkT

V

SD VeeIIDSGS

λ+

−= 11 //

0 0.5 1 1.5 2 2.510-12

10-10

10-8

10-6

10-4

10-2

VGS(V)

I D(A

)

VT

Linear

Exponential

Quadratic

SubSub--Threshold ConductionThreshold Conduction

Typically, we prefer that the current drop as fast as possible once VGS < VT . The rate of decline of the current at VGS < VT is a quality measure of a device => well known as subthreshold slope factor (S). This factor can be quantified as

By how much does VGS have to be reduced for an order of magnitude reduction in drain current (mV/decade)?

)10ln(

=

qkT

nS

S=60mV/decade = sharpest possible roll-off (n=1). Typical values are in the 90mV/decade rangeImmediate problems due to subthreshold leakage exist in dynamic circuits and memory, which reply on the storage of charge on a capacitor.

Threshold VariationsThreshold VariationsVT

L

Long-channel threshold Low VDSthreshold

Threshold as a function of the length (for low VDS)

Drain-induced barrier lowering (for low L)

VDS

VT

Typically, the channel depletion region is solely due to the applied gate voltage, and that all depletion charge beneath the gate originates from the MOS field effects. This ignores the depletion regions of the source and reverse-biased drain junction, which become important with shrinking channel lengths. Since a part of the region below the gate is already depleted (by the source and drain fields), a smaller threshold voltage suffices to cause strong inversion. Thus, VT0 decreases with L for short-channel devices. A similar effect is obtained by raising the VDS, as this increases the width of the drain-junction depletion region. Consequently, VT decreases with increasing VDS. The effect is known as drain-induced barrier lowering (DIBL), causing VT to be a function of VDS. For high enough values of VD, the source and drain regions can even be shorted together, and normal device operation ceases to exist. The sharp increase in current that results from this effect is called punchthrough. It defines an upper bound of VDS that can be applied to a device, before causing permanent damage to the device.

Hot CarriersHot Carriers

Due to scaling of device dimensions, while the power supply and operating voltages have not scaled accordingly, has resulted in large electrical fields. This has caused an increase in the electrons’ velocity, which can leave the silicon and tunnel into the gate oxide upon reaching a sufficiently high level of energy. Electrons trapped in the oxide change the threshold voltage (increasing VT for NMOS devices). For an electron to become hot, an electrical field of at least 104

V/cm is necessary. This condition is easily met in submicron devices.

The channel hot electrons effect is mainly caused by electrons flowing in the channel region, from source to drain. This effect is more pronounced at large VDS, as which the lateral electric field in the drain end of the channel accelerates the electrons. The electrons arriving at the Si-SiO2 interface with enough kinetic energy to surmount the surface potential barrier are injected into the oxide.

Process VariationsProcess Variations

333633141016472006

323430121012402005

273028101010352002

24332610108331999

22252510108321997

ρHWVtVddToxLeffYear

H=ILDH=ILD

WW

TT

SS

Ground planeGround plane

% variation from mean value% variation from mean value

Process VariationsProcess Variations

Example: Minimum sized NMOS device in 0.25µm CMOS technology. VGS=VDS=2.5V => ID= 220µA.Using fast & slow models, modify the length and width by ±10%, threshold ±60mV, and oxide thickness ±5%.

Thus for fast: ID = 265µA: +20%slow: ID = 182µA: -17%