digital integrated circuits - adders

7/29/2019 Digital Integrated Circuits - Adders

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DIC-Lec11 [email protected] 1

Digital Integrated Circuits

Lecture 11: Adders

Chih-Wei Liu

VLSI Signal Processing LAB

National Chiao Tung University

[email protected]


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Outline

Single-bit Addition

Carry-Ripple Adder

Carry-Skip Adder

Carry-Lookahead Adder Carry-Select Adder

Carry-Increment Adder

Tree Adder


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Single-Bit Addition

Half Adder Full Adder

11

01

10

00

SCoutBA

111

011

101

001

110

010

100

000

SCoutCBA

A B

S

Cout

A B

C

S

Cout

out

S

C

=

= out

S

C

=

=


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A B

C

S

Cout

Single-Bit Addition

Half Adder Full Adder

BCACAB

ABCCABCBAABCBCAABC

ABCCABCBABCACout

++=+++++=

+++=

)()()(

0111

1001

1010

0000

SCoutBA

11111

01011

01101

10001

01110

10010

10100

00000

SCoutCBA

A B

S

Cout

out

S A B

C A B

=

= out ( , , )S A B C

C MAJ A B C

=

=


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Remarks


6/49


PGK

For a full adder, define what happens to carries

Generate: Cout = 1 independent of C G =

Propagate: Cout = C

P =

Kill: Cout = 0 independent of C

K =


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PGK

For a full adder, define what happens to carries

Generate: Cout

= 1 independent of C

G = A B

Propagate: Cout = C

P = A B

Kill: Cout = 0 independent of C

BBAK +==


8/49


Remarks

)(

),,(MAJ2.

BACBA

CBACout

++=

=

outCCBAABC

CBCABACBAABC

CBACBACBAABC

ABCCBACBACBAS

)(

))((

+++=

+++++=

+++=

+++=

)(),,(MIN

)(),,(MAJ.1

BACABCBA

BACBACBA

++=

++=Q

),,(MAJ

)(

)()(

)(

)(

CBA

BACAB

BACBA

BACAB

BACAB

BCACABCout

=++=

++=

++=++=

++=


9/49


Full Adder Design I

Brute force implementation from eqns

out ( , , )S A B C

C MAJ A B C = =

ABC

S

Cout

MAJ

ABC

A

B BB

A

CS

C

CC

B BB

A A

A B

C

B

A

CBA A B C

Cout

C

A

A

BB

32 transistors

)( BACBACout ++=gate


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Full Adder Design II

Factor S in terms of Cout

S = ABC + (A + B + C)(~Cout) Critical path is usually C to Cout in ripple adder

SS

Cout

AB

C

Cout

MINORITY 28 transistors


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Remarks

Feed the carry-in signal to the inner inputs

Make all transistors in the sum logic whose gate signals

are connected to the carry-in and carry logic minimum

size (This will minimize the branching effort on the critical

path)

Build an asymmetric gate that reduces the logical effort

from C to ~Cout at the expense of effort to S

Use relatively large transistors on the critical path


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Layout

Clever layout circumvents usual line of diffusion

Use wide transistors on critical path Eliminate output inverters


13/49


CPL

Complementary Pass-transistor Logic

Dual-rail form of pass transistor logic Avoids need for ratioed feedback

Optional cross-coupling for rail-to-rail swing

B

S

S

S

S

A

B

AY

YL

L


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A

C

S

S

B

B

C

C

C

B

BC

out

Cout

C

C

C

C

B

B

B

B

B

B

B

B

A

A

A

Full Adder Design III

Complementary Pass Transistor Logic (CPL)

Using transmission gate to form multiplexers and XORs

Slightly faster, but more area

CPCBAS == )(

)(

)(

BACAB

ABBABAC

ABCCABCBABCACout

+=

++=

+++=


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Full Adder Design IV

Dual-rail domino

Very fast, but large and power hungry

Used in very fast multipliers

Cout

_h

A_h B_h

C_h

B_h

A_h

Cout_l

A_l B_l

C_l

B_l

A_l

S_hS_l

A_h

B_h B_hB_l

A_l

C_lC_h C_h

out ( , , )

S A B C

C MAJ A B C

=

=


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Carry Propagate Adders (CPAs)

N-bit adder called CPA

Each sum bit depends on all previous carries How do we compute all these carries quickly?

+

BN...1AN...1

SN...1

Cin

Cout

11111

1111

+0000

0000

A4...1

carries

B4...1

S4...1

CinCout

00000

1111

+0000

1111

Cin

Cout


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Carry-Ripple Adder

Simplest design: cascade full adders

Critical path goes from Cin to Cout Design full adder to have fast carry delay

Cin

Cout

B1A1B2A2B3A3B4A4

S1

S2

S3

S4

C1

C2

C3


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Inversions

Critical path passes through majority gate

Built from minority + inverter

Eliminate inverter and use inverting full adder

Because addition is a symmetric function, an inverting full

adder receiving complementary inputs produces true outputs

Cout

Cin

B1

A1

B2

A2

B3

A3

B4

A4

S1

S2

S3

S4

C1

C2

C3


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Generate / Propagate

Equations often factored into G and P

Generate and propagate for groups spanning i:j

Base case

Sum:

:

:

i j

i j

G

P

=

=

:

:

i i i

i i i

G G

P P

=

=

0:0 0

0:0 0

G G

P P

=

=

iS =


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Propagate & Generate in Full Adder

For a full adder,

Generate: Cout = 1 independent of C

G = A B

Propagate: Cout = C

P = A B

A group of bits generates a carry if its carry-out is trueindependent of the carry-in

A group of bits propagates a carry if its carry-out is truewhen there is a carry-in


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Generate / Propagate

Equations often factored into G and P

Generate and propagate for groups spanning i:j

Base case

Sum:

: : : 1:

: : 1:

i j i k i k k j

i j i k k j

G G P G

P P P

= +

=

:

:

i i i i i

i i i i i

G G A B

P P A B

=

=

0:0 0

0:0 0 0

inG G C

P P

=

=

1:0i i iS P G =

Step-1

Step-2

Step-3


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PG Logic

S1

B1

A1

P1

G1

G0:0

S2

B2

P2

G2

G1:0

A2

S3

B3

A3

P3

G3

G2:0

S4

B4

P4

G4

G3:0

A4

Cin

G0

P0

1: Bitwise PG logic

2: Group PG logic

3: Sum logicC

0C

1C

2C

3

Cout

C4

Routine steps


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Carry-Ripple Revisited

:0 1:0

i i i iG G P G = +

S1

B1

A1

P1

G1

G0:0

S2

B2

P2

G2

G1:0

A2

S3

B3

A3

P3

G3

G2:0

S4

B4

P4

G4

G3:0

A4

Cin

G0

P0

C0

C1

C2

C3

Cout

C4

An extreme case

One-bit group

4-bit carry-ripple adders

3 AND-OR gates


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Carry-Ripple PG Diagram

Delay

0123456789101112131415

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

Bit Position

ripple xor( 1)pg AOt t N t t = + +

AND-OR gate


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PG Diagram Notation

: : : 1:

: : 1:

i j i k i k k j

i j i k k j

G G P G

P P P

= +

=

i:j

i:j

i:k k-1:j

i:j

i:k k-1:j

i:j

Gi:k

Pk-1:j

Gk-1:j

Gi:j

Pi:j

Pi:k

Gi:k

Gk-1:j

Gi:j G

i:j

Pi:j

Gi:j

Pi:j

Pi:k

Black cell Gray cell Buffer


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Carry-Skip Adder

Carry-ripple is slow through all N stages

Carry-skip allows carry to skip over groups of n bits Decision based on n-bit propagate signal

Cin

+

S4:1

P4:1

A4:1

B4:1

+

S8:5

P8:5

A8:5

B8:5

+

S12:9

P12:9

A12:9

B12:9

+

S16:13

P16:13

A16:13

B16:13

Cout

C4

1

0

C8

1

0

C12

1

0

1

0

Also called Carry-bypass Adder

4-bit group

SkipMultiplexor


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Carry-Skip PG Diagram

For k n-bit groups (N = nk)

skipt =

012345678910111213141516

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:016:0


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Remarks

The critical path begins with generating a carry from bit-1, and

then propagating it through the remainder of the adder. The carry must ripple through the first n-bit group adder, but then

may skip across the other n-bit group adder

Finally, the carry must ripple through the final n-bit group adder

to produce the sum.

The final AND-OR and column 16 are not strictly necessary

because Cout can be computed in parallel with the sum XORs


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Carry-Skip PG Diagram

For k n-bit groups (N = nk)

( )skip xor2 1 ( 1)pg AOt t n k t t = + + +

012345678910111213141516

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:016:0

Depend on the first and thelast group and the numberof groups

Delay grows as O(sqrt(N))


30/49


Variable Group Size

Delay grows as O(sqrt(N))

012345678910111213141516

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:016:0

Groups of length [2, 3, 4, 4, 3]


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Carry-Lookahead Adder

Carry-lookahead adder computes Gi:0 for many bits inparallel.

Uses higher-valency cells with more than two inputs.

Cin

+

S4:1

G4:1

P4:1

A4:1 B4:1

+

S8:5

G8:5

P8:5

A8:5 B8:5

+

S12:9

G12:9

P12:9

A12:9 B12:9

+

S16:13

G16:13

P16:13

A16:13 B16:13

C4

C8

C12

Cout

Tempt to replace the skip multiplexer with AND-OR gate to reduce delay


32/49


CLA PG Diagram

012345678910111213141516

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:016:0

higher-valency cells


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Higher-Valency Cells

i:j

i:k k-1:l l-1:m m-1:j

Gi:k

Gk-1:l

Gl-1:m

Gm-1:j

Gi:j

Pi:j

Pi:k

Pk-1:l

Pl-1:m

Pm-1:j


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Carry-Select Adder

Trick for critical paths dependent on late input X

Precompute two possible outputs for X = 0, 1 Select proper output when X arrives

Carry-select adder precomputes n-bit sums

For both possible carries into n-bit group

Cin+

A4:1

B4:1

S4:1

C4

+

+

01

A8:5

B8:5

S8:5

C8

+

+

01

A12:9

B12:9

S12:9

C12

+

+

01

A16:13

B16:13

S16:13

Cout

0

1

0

1

0

1

One assumes the carry-in of 0The other is carry-in of 1


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Remarks

The two n-bit adders are redundant in that both

contain the initial PG logic and final sum XOR.

S1

B1

A1

P1G1

G0:0

S2

B2

P2G2

G1:0

A2

S3

B3

A3

P3G3

G2:0

S4

B4

P4G4

G3:0

A4

Cin

G0 P0

1: Bitwise PG logic

2: Group PG logic

3: Sum logicC

0C

1C

2C

3

Cout

C4


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Carry-Increment Adder

Factor initial PG and final XOR out of carry-select

5:4

6:4

7:4

9:8

10:8

11:8

13:12

14:12

15:12

0123456789101112131415

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

( )increment xor1 ( 1)pg AOt t n k t t = + + +

Black cells areused tocompute PGsignals

About twice asmany cells ascarry-ripple

adder


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Variable Group Size

Also buffer

noncriticalsignals

3:25:4

6:4

8:7

9:7

12:11

13:11

14:11

15:11

10:7

3:25:4

6:4

8:7

9:7

12:11

13:11

14:11

15:11

10:7 6:0

3:0

1:0

0123456789101112131415

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

0123456789101112131415

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0


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Tree Adder

The delay of passing the carry through the lookahead stagesdominate the delay of carry-lookahead (or carry-skip, carry-select)

adder

If lookahead is good, lookahead across lookahead!

Recursive lookahead gives O(log N) delay

Many variations on tree adders

xor)2( ttNtt AOpgadder ++

xor2 )(log ttNtt AOpgadder ++


39/49


Brent-Kung

1:03:25:47:69:811:1013:1215:14

3:07:411:815:12

7:015:8

11:0

5:09:013:0

0123456789101112131415

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

2-bit group


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Sklansky

1:0

2:03:0

3:25:47:69:811:1013:1215:14

6:47:410:811:814:1215:12

12:813:814:815:8

0123456789101112131415

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0


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Kogge-Stone

1:02:13:24:35:46:57:68:79:810:911:1012:1113:1214:1315:14

3:04:15:26:37:48:59:610:711:812:913:1014:1115:12

4:05:06:07:08:19:210:311:412:513:614:715:8

2:0

0123456789101112131415

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0


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Tree Adder Taxonomy

Ideal N-bit tree adder would have

L= log2 N logic levels

Fanout never exceeding 2

No more than one wiring track between levels

Describe adder with 3-D taxonomy (l, f, t)

Logic levels: L + l

Fanout: 2f+ 1

Wiring tracks: 2t

Known tree adders sit on plane defined by

l+ f+ t= L-1


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Tree Adder Taxonomy

f(Fanout)

t(Wire Tracks)

l(Logic Levels)

0 (2)

1 (3)

2 (5)

3 (9)

0 (4)

1 (5)

2 (6)

3 (8)

2 (4)

1 (2)

0 (1)

3 (7)


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Tree Adder Taxonomy

f(Fanout)

t(Wire Tracks)

l(Logic Levels)

0 (2)

1 (3)

2 (5)

3 (9)

0 (4)

1 (5)

2 (6)

3 (8)

2 (4)

1 (2)

0 (1)

3 (7)

Kogge-Stone

Brent-Kung

Sklansky

C l


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Han-Carlson

1:03:25:47:69:811:1013:1215:14

3:05:27:49:611:813:1015:12

5:07:09:211:413:615:8

0123456789101112131415

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

K l [2 1 1 1]


46/49


Knowles [2, 1, 1, 1]

1:02:13:24:35:46:57:68:79:810:911:1012:1113:1214:1315:14

3:04:15:26:37:48:59:610:711:812:913:1014:1115:12

4:05:06:07:08:19:210:311:412:513:614:715:8

2:0

0123456789101112131415

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

L d Fi h


47/49


Ladner-Fischer

1:03:25:47:69:811:1013:12

3:07:411:815:12

5:07:013:815:8

15:14

15:8 13:0 11:0 9:0

0123456789101112131415

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

T R i i d


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Taxonomy Revisited

f(Fanout)

t(Wire Tracks)

l(Logic Levels)

0 (2)

1 (3)

2 (5)

3 (9)

0 (4)

1 (5)

2 (6)

3 (8)

2 (4)

1 (2)

0 (1)

3 (7)

Kogge-

Stone

Sklansky

Brent-

Kung

Han-

CarlsonKnowles

[2,1,1,1]

Knowles

[4,2,1,1]

Ladner-Fischer

Han-

Carlson

Ladner-

Fischer

New

(1,1,1)

(c) Kogge-Stone

1:02:13:24:35:46:57:68:79:810:911:1012:1113:1214:1315:14

3:04:15:26:37:48:59:610:711:812:913:1014:1115:12

4:05:06:07:08:19:210:311:412:513:614:715:8

2:0

0123456789101112131415

15:014:013:012:011:010:0 9 :0 8 :0 7 :0 6 :0 5 :0 4 :0 3 :0 2 :0 1 :0 0 :0

(e) Knowles [2,1,1,1]

1:02:13:24:35:46:57:68:79:810:911:1012:1113:1214:1315:14

3:04:15:26:37:48:59:610:711:812:913:1014:1115:12

4:05:06:07:08:19:210:311:412:513:614:715:8

2:0

0123456789101112131415

15:014 :013:012 :011:010 :0 9 :0 8 :0 7 :0 6 :0 5 :0 4 :0 3 :0 2 :0 1 :0 0 :0

(b) Sklansky

1:0

2:03:0

3:25:47:69:811:1013:1215:14

6:47:410:811:814:1215:12

12:813:814:815:8

0123456789101112131415

15:014 :013 :012:011 :010 :0 9 :0 8 :0 7 :0 6 :0 5 :0 4 :0 3 :0 2 :0 1 :0 0 :0

1:03:25:47:69:811:1013:12

3:07:411:815:12

5:07:013:815:8

15:14

15:8 13:0 11:0 9:0

0123456789101112131415

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

(f) Ladner-Fischer

(a) Brent-Kung

1:03:25:47:69:811:1013:1215:14

3:07:411:815:12

7:015:8

11:0

5:09:013:0

0123456789101112131415

15:014:013:012:011:010:0 9 :0 8 :0 7 :0 6 :0 5 :0 4 :0 3 :0 2 :0 1 :0 0 :0

1:03:25:47:69:811:1013:1215:14

3:05:27:49:611:813:1015:12

5:07:09:211:413:615:8

0123456789101112131415

15:014:013:012:011:010:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

(d) Han-Carlson

S


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Summary

Nlog2NN/22log2N(0, 0, L-1)Kogge-Stone

0.5 Nlog2N1N/2 + 1log2N(0, L-1, 0)Sklansky

2N122log2N 1(L-1, 0, 0)Brent-Kung

2N14N/4 + 2Carry-Inc. n=4

1.25N12N/4 + 5Carry-Skip n=4

N11N-1Carry-Ripple

CellsTracksMaxFanout

LogicLevels

ClassificationArchitecture

Adder architectures offer area / power / delay tradeoffs.

Choose the best one for your application.

digital integrated circuits - adders

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